From b9bc815c2c01e8cbc6fe894e3b4ff6bb4313ebcb Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 11 May 2012 13:30:34 -0700 Subject: mtd: cafe_nand: spelling mistake Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/cafe_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c index f3f6cfedd69e..ac0d967ee3fd 100644 --- a/drivers/mtd/nand/cafe_nand.c +++ b/drivers/mtd/nand/cafe_nand.c @@ -377,7 +377,7 @@ static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, * @buf: buffer to store read data * @oob_required: caller expects OOB data read to chip->oob_poi * - * The hw generator calculates the error syndrome automatically. Therefor + * The hw generator calculates the error syndrome automatically. Therefore * we need a special oob layout and handling. */ static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, -- cgit v1.2.3 From 271b874ba1512a1b3bd24edbd4e4116c3b5c15ae Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 11 May 2012 13:30:35 -0700 Subject: mtd: nand: gpmi: need to use {read,write}_oob_raw This patch is simply an added warning in the comments. Ideally, this patch need not be merged, but rather, a developer will write a proper solution that can use the ecc.read_oob_raw and ecc.write_oob_raw interfaces. Signed-off-by: Brian Norris Cc: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index a6cad5caba78..6574c6f51b8b 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -1064,6 +1064,9 @@ exit_auxiliary: * ECC-based or raw view of the page is implicit in which function it calls * (there is a similar pair of ECC-based/raw functions for writing). * + * FIXME: The following paragraph is incorrect, now that there exist + * ecc.read_oob_raw and ecc.write_oob_raw functions. + * * Since MTD assumes the OOB is not covered by ECC, there is no pair of * ECC-based/raw functions for reading or or writing the OOB. The fact that the * caller wants an ECC-based or raw view of the page is not propagated down to -- cgit v1.2.3 From cb54751d7a706b4a068b798b97e8a815b99fa835 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:40 +0200 Subject: mtd: sh_flctl: Add missing iounmap() Add the unmapping for the error case and for the driver removal. Signed-off-by: Bastian Hecht Acked-by: Laurent Pinchart Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index aa9b8a5e0b8f..a5a60cac7e70 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -918,6 +918,7 @@ static int __devinit flctl_probe(struct platform_device *pdev) err_chip: pm_runtime_disable(&pdev->dev); + iounmap(flctl->reg); err_iomap: kfree(flctl); return ret; @@ -929,6 +930,7 @@ static int __devexit flctl_remove(struct platform_device *pdev) nand_release(&flctl->mtd); pm_runtime_disable(&pdev->dev); + iounmap(flctl->reg); kfree(flctl); return 0; -- cgit v1.2.3 From 3c7ea4eccfd2e209ba666d217a2993b8a084a429 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:41 +0200 Subject: mtd: sh_flctl: Add support for error IRQ When the data transfer between the controller and the NAND chip fails, we now get notified. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index a5a60cac7e70..c835b136e7cb 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -68,8 +69,8 @@ static struct nand_bbt_descr flctl_4secc_largepage = { static void empty_fifo(struct sh_flctl *flctl) { - writel(0x000c0000, FLINTDMACR(flctl)); /* FIFO Clear */ - writel(0x00000000, FLINTDMACR(flctl)); /* Clear Error flags */ + writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl)); + writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); } static void start_translation(struct sh_flctl *flctl) @@ -839,6 +840,16 @@ static int flctl_chip_init_tail(struct mtd_info *mtd) return 0; } +static irqreturn_t flctl_handle_flste(int irq, void *dev_id) +{ + struct sh_flctl *flctl = dev_id; + + dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl))); + writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); + + return IRQ_HANDLED; +} + static int __devinit flctl_probe(struct platform_device *pdev) { struct resource *res; @@ -847,6 +858,7 @@ static int __devinit flctl_probe(struct platform_device *pdev) struct nand_chip *nand; struct sh_flctl_platform_data *pdata; int ret = -ENXIO; + int irq; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -872,14 +884,27 @@ static int __devinit flctl_probe(struct platform_device *pdev) goto err_iomap; } + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "failed to get flste irq data\n"); + goto err_flste; + } + + ret = request_irq(irq, flctl_handle_flste, IRQF_SHARED, "flste", flctl); + if (ret) { + dev_err(&pdev->dev, "request interrupt failed.\n"); + goto err_flste; + } + platform_set_drvdata(pdev, flctl); flctl_mtd = &flctl->mtd; nand = &flctl->chip; flctl_mtd->priv = nand; flctl->pdev = pdev; - flctl->flcmncr_base = pdata->flcmncr_val; flctl->hwecc = pdata->has_hwecc; flctl->holden = pdata->use_holden; + flctl->flcmncr_base = pdata->flcmncr_val; + flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE; /* Set address of hardware control function */ /* 20 us command delay time */ @@ -918,6 +943,8 @@ static int __devinit flctl_probe(struct platform_device *pdev) err_chip: pm_runtime_disable(&pdev->dev); + free_irq(irq, flctl); +err_flste: iounmap(flctl->reg); err_iomap: kfree(flctl); @@ -930,6 +957,7 @@ static int __devexit flctl_remove(struct platform_device *pdev) nand_release(&flctl->mtd); pm_runtime_disable(&pdev->dev); + free_irq(platform_get_irq(pdev, 0), flctl); iounmap(flctl->reg); kfree(flctl); -- cgit v1.2.3 From aa32d1f0601ac2f5f69520175b8d2cea42caa025 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:42 +0200 Subject: mtd: sh_flctl: Use different OOB layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The flctl hardware has changed and a new OOB layout must be adapted for 2KiB page size NAND chips when using hardware ECC. The related bit fields ECCPOS[0-2] are gone — the bits are marked as reserved now in the datasheet. As there are no official users of the hardware ECC so far, they are completely removed. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index c835b136e7cb..b3666be0ccfc 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -44,11 +44,17 @@ static struct nand_ecclayout flctl_4secc_oob_16 = { }; static struct nand_ecclayout flctl_4secc_oob_64 = { - .eccbytes = 10, - .eccpos = {48, 49, 50, 51, 52, 53, 54, 55, 56, 57}, + .eccbytes = 4 * 10, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, .oobfree = { - {.offset = 60, - . length = 4} }, + {.offset = 2, .length = 4}, + {.offset = 16, .length = 6}, + {.offset = 32, .length = 6}, + {.offset = 48, .length = 6} }, }; static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; @@ -62,7 +68,7 @@ static struct nand_bbt_descr flctl_4secc_smallpage = { static struct nand_bbt_descr flctl_4secc_largepage = { .options = NAND_BBT_SCAN2NDPAGE, - .offs = 58, + .offs = 0, .len = 2, .pattern = scan_ff_pattern, }; @@ -832,7 +838,7 @@ static int flctl_chip_init_tail(struct mtd_info *mtd) chip->ecc.mode = NAND_ECC_HW; /* 4 symbols ECC enabled */ - flctl->flcmncr_base |= _4ECCEN | ECCPOS2 | ECCPOS_02; + flctl->flcmncr_base |= _4ECCEN; } else { chip->ecc.mode = NAND_ECC_SOFT; } -- cgit v1.2.3 From ef4ce0bcb3c91375d2bdefd7a0e2fead95c97620 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:43 +0200 Subject: mtd: sh_flctl: Fix hardware ECC behaviour The flctl uses 10 bytes ECC data for every 512 bytes sector. This patch makes the controller write all 40 bytes instead of 10 bytes only. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index b3666be0ccfc..8633b5b98a13 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -427,30 +427,20 @@ static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) static void execmd_read_oob(struct mtd_info *mtd, int page_addr) { struct sh_flctl *flctl = mtd_to_flctl(mtd); + int page_sectors = flctl->page_size ? 4 : 1; + int i; set_cmd_regs(mtd, NAND_CMD_READ0, (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); empty_fifo(flctl); - if (flctl->page_size) { - int i; - /* In case that the page size is 2k */ - for (i = 0; i < 16 * 3; i++) - flctl->done_buff[i] = 0xFF; - - set_addr(mtd, 3 * 528 + 512, page_addr); - writel(16, FLDTCNTR(flctl)); - start_translation(flctl); - read_fiforeg(flctl, 16, 16 * 3); - wait_completion(flctl); - } else { - /* In case that the page size is 512b */ - set_addr(mtd, 512, page_addr); + for (i = 0; i < page_sectors; i++) { + set_addr(mtd, (512 + 16) * i + 512 , page_addr); writel(16, FLDTCNTR(flctl)); start_translation(flctl); - read_fiforeg(flctl, 16, 0); + read_fiforeg(flctl, 16, 16 * i); wait_completion(flctl); } } @@ -495,18 +485,12 @@ static void execmd_write_oob(struct mtd_info *mtd) int page_addr = flctl->seqin_page_addr; int sector, page_sectors; - if (flctl->page_size) { - sector = 3; - page_sectors = 4; - } else { - sector = 0; - page_sectors = 1; - } + page_sectors = flctl->page_size ? 4 : 1; set_cmd_regs(mtd, NAND_CMD_PAGEPROG, (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN); - for (; sector < page_sectors; sector++) { + for (sector = 0; sector < page_sectors; sector++) { empty_fifo(flctl); set_addr(mtd, sector * 528 + 512, page_addr); writel(16, FLDTCNTR(flctl)); /* set read size */ -- cgit v1.2.3 From 50ed399cc3fbe5e16de78f7b62a39b8280f9001b Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:44 +0200 Subject: mtd: sh_flctl: Simplify the hardware ecc page read/write As the equation mtd->writesize == eccsteps * eccsize holds, we can simplify the code. The second loop of the 1st hunk is never entered, so we delete it. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 8633b5b98a13..1cc19eb1c302 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -353,35 +353,14 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - int i, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - struct sh_flctl *flctl = mtd_to_flctl(mtd); - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - chip->read_buf(mtd, p, eccsize); - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - if (flctl->hwecc_cant_correct[i]) - mtd->ecc_stats.failed++; - else - mtd->ecc_stats.corrected += 0; /* FIXME */ - } - + chip->read_buf(mtd, buf, mtd->writesize); return 0; } static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { - int i, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - const uint8_t *p = buf; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - chip->write_buf(mtd, p, eccsize); + chip->write_buf(mtd, buf, mtd->writesize); } static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) -- cgit v1.2.3 From 623c55caa37203ece6b4450daa0d2d058255da30 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:45 +0200 Subject: mtd: sh_flctl: Group sector accesses into a single transfer When we use hardware ecc, the flctl is run in so-called "sector access mode". We can bundle 4 sector accesses when using 2KiB page sizes to read a whole page at once and speed up things. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 1cc19eb1c302..96e242adda6a 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -368,25 +368,21 @@ static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) struct sh_flctl *flctl = mtd_to_flctl(mtd); int sector, page_sectors; - if (flctl->page_size) - page_sectors = 4; - else - page_sectors = 1; + page_sectors = flctl->page_size ? 4 : 1; + + set_cmd_regs(mtd, NAND_CMD_READ0, + (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT, FLCMNCR(flctl)); + writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl)); + writel(page_addr << 2, FLADR(flctl)); - set_cmd_regs(mtd, NAND_CMD_READ0, - (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); + empty_fifo(flctl); + start_translation(flctl); for (sector = 0; sector < page_sectors; sector++) { int ret; - - empty_fifo(flctl); - writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl)); - writel(page_addr << 2 | sector, FLADR(flctl)); - - start_translation(flctl); read_fiforeg(flctl, 512, 512 * sector); ret = read_ecfiforeg(flctl, @@ -397,8 +393,10 @@ static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) flctl->hwecc_cant_correct[sector] = 1; writel(0x0, FL4ECCCR(flctl)); - wait_completion(flctl); } + + wait_completion(flctl); + writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT), FLCMNCR(flctl)); } @@ -430,31 +428,27 @@ static void execmd_write_page_sector(struct mtd_info *mtd) int i, page_addr = flctl->seqin_page_addr; int sector, page_sectors; - if (flctl->page_size) - page_sectors = 4; - else - page_sectors = 1; - - writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl)); + page_sectors = flctl->page_size ? 4 : 1; set_cmd_regs(mtd, NAND_CMD_PAGEPROG, (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN); - for (sector = 0; sector < page_sectors; sector++) { - empty_fifo(flctl); - writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl)); - writel(page_addr << 2 | sector, FLADR(flctl)); + empty_fifo(flctl); + writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl)); + writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl)); + writel(page_addr << 2, FLADR(flctl)); + start_translation(flctl); - start_translation(flctl); + for (sector = 0; sector < page_sectors; sector++) { write_fiforeg(flctl, 512, 512 * sector); for (i = 0; i < 4; i++) { wait_wecfifo_ready(flctl); /* wait for write ready */ writel(0xFFFFFFFF, FLECFIFO(flctl)); } - wait_completion(flctl); } + wait_completion(flctl); writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl)); } -- cgit v1.2.3 From 6667a6d58e25d351d8fce7a628a8c9c139a8bdc9 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:46 +0200 Subject: mtd: sh_flctl: Restructure the hardware ECC handling There are multiple reasons for a rewrite: - a race exists: when _4ECCEND is set, _4ECCFA may become true too meanwhile, which is lost and a non-correctable error is treated as correctable. - the ECC statistics don't get properly propagated to the base code. - empty pages would get marked as corrupted The rewrite resolves the issues and I hope it gives a more explicit code flow structure. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 121 +++++++++++++++++++++++++++++--------------- 1 file changed, 81 insertions(+), 40 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 96e242adda6a..bc50e83336bb 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -165,27 +165,56 @@ static void wait_wfifo_ready(struct sh_flctl *flctl) timeout_error(flctl, __func__); } -static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number) +static enum flctl_ecc_res_t wait_recfifo_ready + (struct sh_flctl *flctl, int sector_number) { uint32_t timeout = LOOP_TIMEOUT_MAX; - int checked[4]; void __iomem *ecc_reg[4]; int i; + int state = FL_SUCCESS; uint32_t data, size; - memset(checked, 0, sizeof(checked)); - + /* + * First this loops checks in FLDTCNTR if we are ready to read out the + * oob data. This is the case if either all went fine without errors or + * if the bottom part of the loop corrected the errors or marked them as + * uncorrectable and the controller is given time to push the data into + * the FIFO. + */ while (timeout--) { + /* check if all is ok and we can read out the OOB */ size = readl(FLDTCNTR(flctl)) >> 24; - if (size & 0xFF) - return 0; /* success */ + if ((size & 0xFF) == 4) + return state; + + /* check if a correction code has been calculated */ + if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) { + /* + * either we wait for the fifo to be filled or a + * correction pattern is being generated + */ + udelay(1); + continue; + } - if (readl(FL4ECCCR(flctl)) & _4ECCFA) - return 1; /* can't correct */ + /* check for an uncorrectable error */ + if (readl(FL4ECCCR(flctl)) & _4ECCFA) { + /* check if we face a non-empty page */ + for (i = 0; i < 512; i++) { + if (flctl->done_buff[i] != 0xff) { + state = FL_ERROR; /* can't correct */ + break; + } + } - udelay(1); - if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) + if (state == FL_SUCCESS) + dev_dbg(&flctl->pdev->dev, + "reading empty sector %d, ecc error ignored\n", + sector_number); + + writel(0, FL4ECCCR(flctl)); continue; + } /* start error correction */ ecc_reg[0] = FL4ECCRESULT0(flctl); @@ -194,28 +223,26 @@ static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number) ecc_reg[3] = FL4ECCRESULT3(flctl); for (i = 0; i < 3; i++) { + uint8_t org; + int index; + data = readl(ecc_reg[i]); - if (data != INIT_FL4ECCRESULT_VAL && !checked[i]) { - uint8_t org; - int index; - - if (flctl->page_size) - index = (512 * sector_number) + - (data >> 16); - else - index = data >> 16; - - org = flctl->done_buff[index]; - flctl->done_buff[index] = org ^ (data & 0xFF); - checked[i] = 1; - } - } + if (flctl->page_size) + index = (512 * sector_number) + + (data >> 16); + else + index = data >> 16; + + org = flctl->done_buff[index]; + flctl->done_buff[index] = org ^ (data & 0xFF); + } + state = FL_REPAIRABLE; writel(0, FL4ECCCR(flctl)); } timeout_error(flctl, __func__); - return 1; /* timeout */ + return FL_TIMEOUT; /* timeout */ } static void wait_wecfifo_ready(struct sh_flctl *flctl) @@ -259,20 +286,23 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset) } } -static int read_ecfiforeg(struct sh_flctl *flctl, uint8_t *buff, int sector) +static enum flctl_ecc_res_t read_ecfiforeg + (struct sh_flctl *flctl, uint8_t *buff, int sector) { int i; + enum flctl_ecc_res_t res; unsigned long *ecc_buf = (unsigned long *)buff; - void *fifo_addr = (void *)FLECFIFO(flctl); - for (i = 0; i < 4; i++) { - if (wait_recfifo_ready(flctl , sector)) - return 1; - ecc_buf[i] = readl(fifo_addr); - ecc_buf[i] = be32_to_cpu(ecc_buf[i]); + res = wait_recfifo_ready(flctl , sector); + + if (res != FL_ERROR) { + for (i = 0; i < 4; i++) { + ecc_buf[i] = readl(FLECFIFO(flctl)); + ecc_buf[i] = be32_to_cpu(ecc_buf[i]); + } } - return 0; + return res; } static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset) @@ -367,6 +397,7 @@ static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) { struct sh_flctl *flctl = mtd_to_flctl(mtd); int sector, page_sectors; + enum flctl_ecc_res_t ecc_result; page_sectors = flctl->page_size ? 4 : 1; @@ -382,17 +413,27 @@ static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) start_translation(flctl); for (sector = 0; sector < page_sectors; sector++) { - int ret; read_fiforeg(flctl, 512, 512 * sector); - ret = read_ecfiforeg(flctl, + ecc_result = read_ecfiforeg(flctl, &flctl->done_buff[mtd->writesize + 16 * sector], sector); - if (ret) - flctl->hwecc_cant_correct[sector] = 1; - - writel(0x0, FL4ECCCR(flctl)); + switch (ecc_result) { + case FL_REPAIRABLE: + dev_info(&flctl->pdev->dev, + "applied ecc on page 0x%x", page_addr); + flctl->mtd.ecc_stats.corrected++; + break; + case FL_ERROR: + dev_warn(&flctl->pdev->dev, + "page 0x%x contains corrupted data\n", + page_addr); + flctl->mtd.ecc_stats.failed++; + break; + default: + ; + } } wait_completion(flctl); -- cgit v1.2.3 From 3166df0d0424ef5c742faba87775cfca99e8f2bf Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Mon, 14 May 2012 14:14:47 +0200 Subject: mtd: sh_flctl: Use user oob data in hardware ECC mode In hardware ecc mode, the flctl now writes and reads the oob data provided by the user. Additionally the ECC is now returned in normal page reads, not only when using the explicit NAND_CMD_READOOB command. Signed-off-by: Bastian Hecht Acked-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index bc50e83336bb..2eb15418c227 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -275,13 +275,12 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset) { int i, len_4align; unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; - void *fifo_addr = (void *)FLDTFIFO(flctl); len_4align = (rlen + 3) / 4; for (i = 0; i < len_4align; i++) { wait_rfifo_ready(flctl); - buf[i] = readl(fifo_addr); + buf[i] = readl(FLDTFIFO(flctl)); buf[i] = be32_to_cpu(buf[i]); } } @@ -318,6 +317,18 @@ static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset) } } +static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen, int offset) +{ + int i, len_4align; + unsigned long *data = (unsigned long *)&flctl->done_buff[offset]; + + len_4align = (rlen + 3) / 4; + for (i = 0; i < len_4align; i++) { + wait_wecfifo_ready(flctl); + writel(cpu_to_be32(data[i]), FLECFIFO(flctl)); + } +} + static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) { struct sh_flctl *flctl = mtd_to_flctl(mtd); @@ -384,6 +395,7 @@ static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { chip->read_buf(mtd, buf, mtd->writesize); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); return 0; } @@ -391,6 +403,7 @@ static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { chip->write_buf(mtd, buf, mtd->writesize); + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); } static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) @@ -466,7 +479,7 @@ static void execmd_read_oob(struct mtd_info *mtd, int page_addr) static void execmd_write_page_sector(struct mtd_info *mtd) { struct sh_flctl *flctl = mtd_to_flctl(mtd); - int i, page_addr = flctl->seqin_page_addr; + int page_addr = flctl->seqin_page_addr; int sector, page_sectors; page_sectors = flctl->page_size ? 4 : 1; @@ -482,11 +495,7 @@ static void execmd_write_page_sector(struct mtd_info *mtd) for (sector = 0; sector < page_sectors; sector++) { write_fiforeg(flctl, 512, 512 * sector); - - for (i = 0; i < 4; i++) { - wait_wecfifo_ready(flctl); /* wait for write ready */ - writel(0xFFFFFFFF, FLECFIFO(flctl)); - } + write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector); } wait_completion(flctl); -- cgit v1.2.3 From b1ccfab31a0bbcb103989cba3b08df0776ff90fe Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 22 May 2012 07:30:47 -0700 Subject: mtd: nand: add Eon Silicon Solutions manufacturer ID Eon's new NAND flash: EN27LN1G08. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_ids.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 621b70b7a159..509a9f6706f3 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -176,6 +176,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD"}, {NAND_MFR_MACRONIX, "Macronix"}, + {NAND_MFR_EON, "Eon"}, {0x0, "Unknown"} }; -- cgit v1.2.3 From 1696e6bc2ae83734e64e206ac99766ea19e9a14e Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 22 May 2012 23:50:00 -0700 Subject: mtd: nand: kill NAND_NO_READRDY According to its documentation, the NAND_NO_READRDY option is always used when autoincrement is not supported. Autoincrement support was recently dropped, so we can drop this options as well (defaulting to "no read ready check"). Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/fsl_elbc_nand.c | 1 - drivers/mtd/nand/fsl_ifc_nand.c | 1 - drivers/mtd/nand/nand_base.c | 17 ----------------- drivers/mtd/nand/nand_ids.c | 4 ++-- drivers/mtd/nand/pxa3xx_nand.c | 1 - 5 files changed, 2 insertions(+), 22 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 784293806110..1d8d111fa3ae 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -805,7 +805,6 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) chip->bbt_md = &bbt_mirror_descr; /* set up nand options */ - chip->options = NAND_NO_READRDY; chip->bbt_options = NAND_BBT_USE_FLASH; chip->controller = &elbc_fcm_ctrl->controller; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 9602c1b7e27e..c5d7f382759d 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -805,7 +805,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) out_be32(&ifc->ifc_nand.ncfgr, 0x0); /* set up nand options */ - chip->options = NAND_NO_READRDY; chip->bbt_options = NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index a11253a0fcab..0a8724e657d7 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1565,14 +1565,6 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, oobreadlen -= toread; } } - - if (!(chip->options & NAND_NO_READRDY)) { - /* Apply delay or wait for ready/busy pin */ - if (!chip->dev_ready) - udelay(chip->chip_delay); - else - nand_wait_ready(mtd); - } } else { memcpy(buf, chip->buffers->databuf + col, bytes); buf += bytes; @@ -1837,14 +1829,6 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, len = min(len, readlen); buf = nand_transfer_oob(chip, buf, ops, len); - if (!(chip->options & NAND_NO_READRDY)) { - /* Apply delay or wait for ready/busy pin */ - if (!chip->dev_ready) - udelay(chip->chip_delay); - else - nand_wait_ready(mtd); - } - readlen -= len; if (!readlen) break; @@ -2915,7 +2899,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, *busw = NAND_BUSWIDTH_16; chip->options &= ~NAND_CHIPOPTIONS_MSK; - chip->options |= NAND_NO_READRDY & NAND_CHIPOPTIONS_MSK; pr_info("ONFI flash detected\n"); return 1; diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 509a9f6706f3..e04c675bf609 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -70,7 +70,7 @@ struct nand_flash_dev nand_flash_ids[] = { * These are the new chips with large page size. The pagesize and the * erasesize is determined from the extended id bytes */ -#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY) +#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) /* 512 Megabit */ @@ -157,7 +157,7 @@ struct nand_flash_dev nand_flash_ids[] = { * writes possible, but not implemented now */ {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, - NAND_IS_AND | NAND_NO_READRDY | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH}, + NAND_IS_AND | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH}, {NULL,} }; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 252aaefcacfa..afc4681f44d7 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1005,7 +1005,6 @@ KEEP_CONFIG: chip->ecc.size = host->page_size; chip->ecc.strength = 1; - chip->options |= NAND_NO_READRDY; if (host->reg_ndcr & NDCR_DWIDTH_M) chip->options |= NAND_BUSWIDTH_16; -- cgit v1.2.3 From 3d059693f6e0489066a98f455601137fa003df77 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 25 May 2012 20:14:50 -0300 Subject: nand: mxc_nand: Use clk_prepare_enable/clk_disable_unprepare Prepare the clock before enabling it. Signed-off-by: Fabio Estevam Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/mxc_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 6acc790c2fbb..fc3b38c7ffb4 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -784,7 +784,7 @@ static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) if (chip == -1) { /* Disable the NFC clock */ if (host->clk_act) { - clk_disable(host->clk); + clk_disable_unprepare(host->clk); host->clk_act = 0; } return; @@ -792,7 +792,7 @@ static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) if (!host->clk_act) { /* Enable the NFC clock */ - clk_enable(host->clk); + clk_prepare_enable(host->clk); host->clk_act = 1; } -- cgit v1.2.3 From 874d72c4fe07713c4889c944d3c7ebbce352c762 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 6 Jun 2012 18:36:39 -0500 Subject: mtd: elbc nand: use drvdata to only remove the relevant chip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously the remove method was looping and removing all chips, which is obviously not the right thing to do — left over from when the driver was organized differently and that was the remove method for the entire controller. This would result in bad things happening if you have more than one NAND chip, and remove the module. This also fixes priv->dev to properly point to the chip's device rather than the controller's. Until now priv->dev was only used for error/debug prints (and it's an improvement there), so this shouldn't break anything. Signed-off-by: Scott Wood Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 1d8d111fa3ae..22bb5e6ddaca 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -915,7 +915,8 @@ static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev) elbc_fcm_ctrl->chips[bank] = priv; priv->bank = bank; priv->ctrl = fsl_lbc_ctrl_dev; - priv->dev = dev; + priv->dev = &pdev->dev; + dev_set_drvdata(priv->dev, priv); priv->vbase = ioremap(res.start, resource_size(&res)); if (!priv->vbase) { @@ -962,11 +963,10 @@ err: static int fsl_elbc_nand_remove(struct platform_device *pdev) { - int i; struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; - for (i = 0; i < MAX_BANKS; i++) - if (elbc_fcm_ctrl->chips[i]) - fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]); + struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev); + + fsl_elbc_chip_remove(priv); mutex_lock(&fsl_elbc_nand_mutex); elbc_fcm_ctrl->counter--; -- cgit v1.2.3 From e4a09cbf2dc7ba6c7fd7e07a3ab3d3f499a575e2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 6 Jun 2012 12:33:13 +0200 Subject: mtd: mxc_nand: Use managed resources To make the error path simpler and to make subsequent patches easier. Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/mxc_nand.c | 70 +++++++++++++++------------------------------ 1 file changed, 23 insertions(+), 47 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index fc3b38c7ffb4..db428c24e2c8 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1344,8 +1344,8 @@ static int __init mxcnd_probe(struct platform_device *pdev) int err = 0; /* Allocate memory for MTD device structure and private data */ - host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE + - NAND_MAX_OOBSIZE, GFP_KERNEL); + host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) + + NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL); if (!host) return -ENOMEM; @@ -1372,26 +1372,17 @@ static int __init mxcnd_probe(struct platform_device *pdev) this->read_buf = mxc_nand_read_buf; this->verify_buf = mxc_nand_verify_buf; - host->clk = clk_get(&pdev->dev, "nfc"); - if (IS_ERR(host->clk)) { - err = PTR_ERR(host->clk); - goto eclk; - } - - clk_prepare_enable(host->clk); - host->clk_act = 1; + host->clk = devm_clk_get(&pdev->dev, "nfc"); + if (IS_ERR(host->clk)) + return PTR_ERR(host->clk); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - err = -ENODEV; - goto eres; - } + if (!res) + return -ENODEV; - host->base = ioremap(res->start, resource_size(res)); - if (!host->base) { - err = -ENOMEM; - goto eres; - } + host->base = devm_request_and_ioremap(&pdev->dev, res); + if (!host->base) + return -ENOMEM; host->main_area0 = host->base; @@ -1399,7 +1390,7 @@ static int __init mxcnd_probe(struct platform_device *pdev) if (err > 0) err = mxcnd_probe_pdata(host); if (err < 0) - goto eirq; + return err; if (host->devtype_data->regs_offset) host->regs = host->base + host->devtype_data->regs_offset; @@ -1416,15 +1407,11 @@ static int __init mxcnd_probe(struct platform_device *pdev) if (host->devtype_data->needs_ip) { res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res) { - err = -ENODEV; - goto eirq; - } - host->regs_ip = ioremap(res->start, resource_size(res)); - if (!host->regs_ip) { - err = -ENOMEM; - goto eirq; - } + if (!res) + return -ENODEV; + host->regs_ip = devm_request_and_ioremap(&pdev->dev, res); + if (!host->regs_ip) + return -ENOMEM; } if (host->pdata.hw_ecc) { @@ -1458,9 +1445,13 @@ static int __init mxcnd_probe(struct platform_device *pdev) */ host->devtype_data->irq_control(host, 0); - err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host); + err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, + IRQF_DISABLED, DRIVER_NAME, host); if (err) - goto eirq; + return err; + + clk_prepare_enable(host->clk); + host->clk_act = 1; /* * Now that we "own" the interrupt make sure the interrupt mask bit is @@ -1512,15 +1503,7 @@ static int __init mxcnd_probe(struct platform_device *pdev) return 0; escan: - free_irq(host->irq, host); -eirq: - if (host->regs_ip) - iounmap(host->regs_ip); - iounmap(host->base); -eres: - clk_put(host->clk); -eclk: - kfree(host); + clk_disable_unprepare(host->clk); return err; } @@ -1529,16 +1512,9 @@ static int __devexit mxcnd_remove(struct platform_device *pdev) { struct mxc_nand_host *host = platform_get_drvdata(pdev); - clk_put(host->clk); - platform_set_drvdata(pdev, NULL); nand_release(&host->mtd); - free_irq(host->irq, host); - if (host->regs_ip) - iounmap(host->regs_ip); - iounmap(host->base); - kfree(host); return 0; } -- cgit v1.2.3 From 71885b650ab0fd9d2d35cd922bf949c07c171b04 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 6 Jun 2012 12:33:14 +0200 Subject: mtd: mxc_nand: swap iomem resource order The i.MX v3 nand controller (i.MX5) needs two memory resources. Traditionally we have the AXI resource first. For sorting in this driver into the devicetree it feels much more natural to have the IP resource first. This patch swaps the ordering of these two resources. Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index db428c24e2c8..48c57275001f 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1376,7 +1376,25 @@ static int __init mxcnd_probe(struct platform_device *pdev) if (IS_ERR(host->clk)) return PTR_ERR(host->clk); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + err = mxcnd_probe_dt(host); + if (err > 0) + err = mxcnd_probe_pdata(host); + if (err < 0) + return err; + + if (host->devtype_data->needs_ip) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + host->regs_ip = devm_request_and_ioremap(&pdev->dev, res); + if (!host->regs_ip) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + } else { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + } + if (!res) return -ENODEV; @@ -1386,12 +1404,6 @@ static int __init mxcnd_probe(struct platform_device *pdev) host->main_area0 = host->base; - err = mxcnd_probe_dt(host); - if (err > 0) - err = mxcnd_probe_pdata(host); - if (err < 0) - return err; - if (host->devtype_data->regs_offset) host->regs = host->base + host->devtype_data->regs_offset; host->spare0 = host->base + host->devtype_data->spare0_offset; @@ -1405,15 +1417,6 @@ static int __init mxcnd_probe(struct platform_device *pdev) this->ecc.size = 512; this->ecc.layout = host->devtype_data->ecclayout_512; - if (host->devtype_data->needs_ip) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res) - return -ENODEV; - host->regs_ip = devm_request_and_ioremap(&pdev->dev, res); - if (!host->regs_ip) - return -ENOMEM; - } - if (host->pdata.hw_ecc) { this->ecc.calculate = mxc_nand_calculate_ecc; this->ecc.hwctl = mxc_nand_enable_hwecc; -- cgit v1.2.3 From 71718a8edf688eb02a9475b7f567e3ec383c9734 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 6 Jun 2012 12:33:15 +0200 Subject: mtd: mxc_nand: add i.MX53 support The only relevant change between i.MX51 and i.MX53 is that a bitfield is shifted one bit to the left. Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/mxc_nand.c | 48 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 6 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 48c57275001f..3f94e1f13231 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -43,8 +43,8 @@ #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) -#define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53()) -#define nfc_is_v3() nfc_is_v3_2() +#define nfc_is_v3_2a() cpu_is_mx51() +#define nfc_is_v3_2b() cpu_is_mx53() /* Addresses for NFC registers */ #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) @@ -122,7 +122,7 @@ #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) -#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) +#define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) #define NFC_V3_CONFIG2_INT_MSK (1 << 15) #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) @@ -174,6 +174,7 @@ struct mxc_nand_devtype_data { int spare_len; int eccbytes; int eccsize; + int ppb_shift; }; struct mxc_nand_host { @@ -1021,7 +1022,9 @@ static void preset_v3(struct mtd_info *mtd) } if (mtd->writesize) { - config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); + config2 |= NFC_V3_CONFIG2_PPB( + ffs(mtd->erasesize / mtd->writesize) - 6, + host->devtype_data->ppb_shift); host->eccsize = get_eccsize(mtd); if (host->eccsize == 8) config2 |= NFC_V3_CONFIG2_ECC_MODE_8; @@ -1234,7 +1237,7 @@ static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { .eccsize = 0, }; -/* v3: i.MX51, i.MX53 */ +/* v3.2a: i.MX51 */ static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { .preset = preset_v3, .send_cmd = send_cmd_v3, @@ -1258,6 +1261,34 @@ static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { .spare_len = 64, .eccbytes = 0, .eccsize = 0, + .ppb_shift = 7, +}; + +/* v3.2b: i.MX53 */ +static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { + .preset = preset_v3, + .send_cmd = send_cmd_v3, + .send_addr = send_addr_v3, + .send_page = send_page_v3, + .send_read_id = send_read_id_v3, + .get_dev_status = get_dev_status_v3, + .check_int = check_int_v3, + .irq_control = irq_control_v3, + .get_ecc_status = get_ecc_status_v3, + .ecclayout_512 = &nandv2_hw_eccoob_smallpage, + .ecclayout_2k = &nandv2_hw_eccoob_largepage, + .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ + .select_chip = mxc_nand_select_chip_v1_v3, + .correct_data = mxc_nand_correct_data_v2_v3, + .irqpending_quirk = 0, + .needs_ip = 1, + .regs_offset = 0, + .spare0_offset = 0x1000, + .axi_offset = 0x1e00, + .spare_len = 64, + .eccbytes = 0, + .eccsize = 0, + .ppb_shift = 8, }; #ifdef CONFIG_OF_MTD @@ -1274,6 +1305,9 @@ static const struct of_device_id mxcnd_dt_ids[] = { }, { .compatible = "fsl,imx51-nand", .data = &imx51_nand_devtype_data, + }, { + .compatible = "fsl,imx53-nand", + .data = &imx53_nand_devtype_data, }, { /* sentinel */ } }; @@ -1327,8 +1361,10 @@ static int __init mxcnd_probe_pdata(struct mxc_nand_host *host) host->devtype_data = &imx27_nand_devtype_data; } else if (nfc_is_v21()) { host->devtype_data = &imx25_nand_devtype_data; - } else if (nfc_is_v3_2()) { + } else if (nfc_is_v3_2a()) { host->devtype_data = &imx51_nand_devtype_data; + } else if (nfc_is_v3_2b()) { + host->devtype_data = &imx53_nand_devtype_data; } else BUG(); -- cgit v1.2.3 From 7bb9c75436212813b38700c34df4bbb6eb82debe Mon Sep 17 00:00:00 2001 From: Shmulik Ladkani Date: Sun, 10 Jun 2012 13:58:12 +0300 Subject: mtd: nand: Use the mirror BBT descriptor when reading its version The code responsible for reading the version of the mirror bbt was incorrectly using the descriptor of the main bbt. Pass the mirror bbt descriptor to 'scan_read_raw' when reading the version of the mirror bbt. Signed-off-by: Shmulik Ladkani Acked-by: Sebastian Andrzej Siewior Cc: stable@vger.kernel.org [v2.6.37+] Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 30d1319ff065..c126469b0645 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -390,7 +390,7 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the mirror version, if available */ if (md && (md->options & NAND_BBT_VERSION)) { scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift, - mtd->writesize, td); + mtd->writesize, md); md->version[0] = buf[bbt_get_ver_offs(mtd, md)]; pr_info("Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); -- cgit v1.2.3 From 3dfe41a4c705223c66373968327407e11c2fb1a1 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Mon, 25 Jun 2012 18:07:43 +0800 Subject: mtd: at91: extract hw ecc initialization to one function This patch moves hw ecc initialization code to one function. Signed-off-by: Hong Xu Signed-off-by: Josh Wu Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/atmel_nand.c | 127 ++++++++++++++++++++++-------------------- 1 file changed, 66 insertions(+), 61 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 97ac6712bb19..7a41a04beb87 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -527,6 +527,66 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host, } #endif +static int __init atmel_hw_nand_init_params(struct platform_device *pdev, + struct atmel_nand_host *host) +{ + struct mtd_info *mtd = &host->mtd; + struct nand_chip *nand_chip = &host->nand_chip; + struct resource *regs; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!regs) { + dev_err(host->dev, + "Can't get I/O resource regs, use software ECC\n"); + nand_chip->ecc.mode = NAND_ECC_SOFT; + return 0; + } + + host->ecc = ioremap(regs->start, resource_size(regs)); + if (host->ecc == NULL) { + dev_err(host->dev, "ioremap failed\n"); + return -EIO; + } + + /* ECC is calculated for the whole page (1 step) */ + nand_chip->ecc.size = mtd->writesize; + + /* set ECC page size and oob layout */ + switch (mtd->writesize) { + case 512: + nand_chip->ecc.layout = &atmel_oobinfo_small; + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); + break; + case 1024: + nand_chip->ecc.layout = &atmel_oobinfo_large; + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); + break; + case 2048: + nand_chip->ecc.layout = &atmel_oobinfo_large; + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); + break; + case 4096: + nand_chip->ecc.layout = &atmel_oobinfo_large; + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); + break; + default: + /* page size not handled by HW ECC */ + /* switching back to soft ECC */ + nand_chip->ecc.mode = NAND_ECC_SOFT; + return 0; + } + + /* set up for HW ECC */ + nand_chip->ecc.calculate = atmel_nand_calculate; + nand_chip->ecc.correct = atmel_nand_correct; + nand_chip->ecc.hwctl = atmel_nand_hwctl; + nand_chip->ecc.read_page = atmel_nand_read_page; + nand_chip->ecc.bytes = 4; + nand_chip->ecc.strength = 1; + + return 0; +} + /* * Probe for the NAND device. */ @@ -535,7 +595,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev) struct atmel_nand_host *host; struct mtd_info *mtd; struct nand_chip *nand_chip; - struct resource *regs; struct resource *mem; struct mtd_part_parser_data ppdata = {}; int res; @@ -587,29 +646,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev) nand_chip->dev_ready = atmel_nand_device_ready; nand_chip->ecc.mode = host->board.ecc_mode; - - regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!regs && nand_chip->ecc.mode == NAND_ECC_HW) { - printk(KERN_ERR "atmel_nand: can't get I/O resource " - "regs\nFalling back on software ECC\n"); - nand_chip->ecc.mode = NAND_ECC_SOFT; - } - - if (nand_chip->ecc.mode == NAND_ECC_HW) { - host->ecc = ioremap(regs->start, resource_size(regs)); - if (host->ecc == NULL) { - printk(KERN_ERR "atmel_nand: ioremap failed\n"); - res = -EIO; - goto err_ecc_ioremap; - } - nand_chip->ecc.calculate = atmel_nand_calculate; - nand_chip->ecc.correct = atmel_nand_correct; - nand_chip->ecc.hwctl = atmel_nand_hwctl; - nand_chip->ecc.read_page = atmel_nand_read_page; - nand_chip->ecc.bytes = 4; - nand_chip->ecc.strength = 1; - } - nand_chip->chip_delay = 20; /* 20us command delay time */ if (host->board.bus_width_16) /* 16-bit bus width */ @@ -661,40 +697,9 @@ static int __init atmel_nand_probe(struct platform_device *pdev) } if (nand_chip->ecc.mode == NAND_ECC_HW) { - /* ECC is calculated for the whole page (1 step) */ - nand_chip->ecc.size = mtd->writesize; - - /* set ECC page size and oob layout */ - switch (mtd->writesize) { - case 512: - nand_chip->ecc.layout = &atmel_oobinfo_small; - ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); - break; - case 1024: - nand_chip->ecc.layout = &atmel_oobinfo_large; - ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); - break; - case 2048: - nand_chip->ecc.layout = &atmel_oobinfo_large; - ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); - break; - case 4096: - nand_chip->ecc.layout = &atmel_oobinfo_large; - ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); - break; - default: - /* page size not handled by HW ECC */ - /* switching back to soft ECC */ - nand_chip->ecc.mode = NAND_ECC_SOFT; - nand_chip->ecc.calculate = NULL; - nand_chip->ecc.correct = NULL; - nand_chip->ecc.hwctl = NULL; - nand_chip->ecc.read_page = NULL; - nand_chip->ecc.postpad = 0; - nand_chip->ecc.prepad = 0; - nand_chip->ecc.bytes = 0; - break; - } + res = atmel_hw_nand_init_params(pdev, host); + if (res != 0) + goto err_hw_ecc; } /* second phase scan */ @@ -711,15 +716,15 @@ static int __init atmel_nand_probe(struct platform_device *pdev) return res; err_scan_tail: + if (host->ecc) + iounmap(host->ecc); +err_hw_ecc: err_scan_ident: err_no_card: atmel_nand_disable(host); platform_set_drvdata(pdev, NULL); if (host->dma_chan) dma_release_channel(host->dma_chan); - if (host->ecc) - iounmap(host->ecc); -err_ecc_ioremap: iounmap(host->io_base); err_nand_ioremap: kfree(host); -- cgit v1.2.3 From fdbad98dff8007f2b8bee6698b5d25ebba0471c9 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Mon, 25 Jun 2012 18:07:45 +0800 Subject: mtd: nand: teach write_page and write_page_raw return an error code There is an implemention of hardware ECC write page function which may return an error indication. For instance, using Atmel HW PMECC to write one page into a nand flash, the hardware engine will compute the BCH ecc code for this page. so we need read a the status register to theck whether the ecc code is generated. But we cannot assume the status register always can be ready, for example, incorrect hardware configuration or hardware issue, in such case we need write_page() to return a error code. Since the definition of 'write_page' function in struct nand_ecc_ctrl is 'void'. So this patch will: 1. add return 'int' value for 'write_page' function. 2. to be consitent, add return 'int' value for 'write_page_raw' fuctions too. 3. add code to test the return value, and if negative, indicate an error happend when write page with ECC. 4. fix the compile warning in all impacted nand flash driver. Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. Signed-off-by: Josh Wu Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/bcm_umi_bch.c | 6 ++++-- drivers/mtd/nand/bf5xx_nand.c | 6 ++++-- drivers/mtd/nand/cafe_nand.c | 11 ++++++++--- drivers/mtd/nand/denali.c | 12 +++++++----- drivers/mtd/nand/docg4.c | 8 +++++--- drivers/mtd/nand/fsl_elbc_nand.c | 4 +++- drivers/mtd/nand/fsl_ifc_nand.c | 4 +++- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 6 ++++-- drivers/mtd/nand/nand_base.c | 27 +++++++++++++++++++-------- drivers/mtd/nand/pxa3xx_nand.c | 4 +++- drivers/mtd/nand/sh_flctl.c | 3 ++- 11 files changed, 62 insertions(+), 29 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c index 5914bb32e001..c8799a001833 100644 --- a/drivers/mtd/nand/bcm_umi_bch.c +++ b/drivers/mtd/nand/bcm_umi_bch.c @@ -23,7 +23,7 @@ /* ---- Private Function Prototypes -------------------------------------- */ static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page); -static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, +static int bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required); /* ---- Private Variables ------------------------------------------------ */ @@ -194,7 +194,7 @@ static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd, * @oob_required: must write chip->oob_poi to OOB * ***************************************************************************/ -static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, +static int bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { int sectorIdx = 0; @@ -214,4 +214,6 @@ static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, } bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c index 3f1c18599cbd..ab0caa74eb43 100644 --- a/drivers/mtd/nand/bf5xx_nand.c +++ b/drivers/mtd/nand/bf5xx_nand.c @@ -566,11 +566,13 @@ static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip return 0; } -static void bf5xx_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) +static int bf5xx_nand_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, int oob_required) { bf5xx_nand_write_buf(mtd, buf, mtd->writesize); bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } /* diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c index ac0d967ee3fd..08248a0a167e 100644 --- a/drivers/mtd/nand/cafe_nand.c +++ b/drivers/mtd/nand/cafe_nand.c @@ -520,7 +520,7 @@ static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { }; -static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd, +static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { @@ -531,6 +531,8 @@ static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd, /* Set up ECC autogeneration */ cafe->ctl2 |= (1<<30); + + return 0; } static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, @@ -542,9 +544,12 @@ static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); if (unlikely(raw)) - chip->ecc.write_page_raw(mtd, chip, buf, oob_required); + status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); else - chip->ecc.write_page(mtd, chip, buf, oob_required); + status = chip->ecc.write_page(mtd, chip, buf, oob_required); + + if (status < 0) + return status; /* * Cached progamming disabled for now, Not sure if its worth the diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 0650aafa0dd2..e706a237170f 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1028,7 +1028,7 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op) /* writes a page. user specifies type, and this function handles the * configuration details. */ -static void write_page(struct mtd_info *mtd, struct nand_chip *chip, +static int write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, bool raw_xfer) { struct denali_nand_info *denali = mtd_to_denali(mtd); @@ -1078,6 +1078,8 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, denali_enable_dma(denali, false); dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); + + return 0; } /* NAND core entry points */ @@ -1086,24 +1088,24 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, * writing a page with ECC or without is similar, all the work is done * by write_page above. * */ -static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, +static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { /* for regular page writes, we let HW handle all the ECC * data written to the device. */ - write_page(mtd, chip, buf, false); + return write_page(mtd, chip, buf, false); } /* This is the callback that the NAND core calls to write a page without ECC. * raw access is similar to ECC page writes, so all the work is done in the * write_page() function above. */ -static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, +static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { /* for raw page writes, we want to disable ECC and simply write whatever data is in the buffer. */ - write_page(mtd, chip, buf, true); + return write_page(mtd, chip, buf, true); } static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c index a225e49a5623..0f2ffd7b6c82 100644 --- a/drivers/mtd/nand/docg4.c +++ b/drivers/mtd/nand/docg4.c @@ -898,7 +898,7 @@ static void docg4_erase_block(struct mtd_info *mtd, int page) write_nop(docptr); } -static void write_page(struct mtd_info *mtd, struct nand_chip *nand, +static int write_page(struct mtd_info *mtd, struct nand_chip *nand, const uint8_t *buf, bool use_ecc) { struct docg4_priv *doc = nand->priv; @@ -950,15 +950,17 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *nand, write_nop(docptr); writew(0, docptr + DOC_DATAEND); write_nop(docptr); + + return 0; } -static void docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand, +static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand, const uint8_t *buf, int oob_required) { return write_page(mtd, nand, buf, false); } -static void docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand, +static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand, const uint8_t *buf, int oob_required) { return write_page(mtd, nand, buf, true); diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 22bb5e6ddaca..8143873d17a5 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -766,11 +766,13 @@ static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip, /* ECC will be calculated automatically, and errors will be detected in * waitfunc. */ -static void fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip, +static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { fsl_elbc_write_buf(mtd, buf, mtd->writesize); fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index c5d7f382759d..1f71b545062a 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -721,11 +721,13 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, /* ECC will be calculated automatically, and errors will be detected in * waitfunc. */ -static void fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, +static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { fsl_ifc_write_buf(mtd, buf, mtd->writesize); fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } static int fsl_ifc_chip_init_tail(struct mtd_info *mtd) diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 6574c6f51b8b..d6fa8f4779ce 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -930,7 +930,7 @@ exit_nfc: return ret; } -static void gpmi_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, +static int gpmi_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { struct gpmi_nand_data *this = chip->priv; @@ -972,7 +972,7 @@ static void gpmi_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, &payload_virt, &payload_phys); if (ret) { pr_err("Inadequate payload DMA buffer\n"); - return; + return 0; } ret = send_page_prepare(this, @@ -1002,6 +1002,8 @@ exit_auxiliary: nfc_geo->payload_size, payload_virt, payload_phys); } + + return 0; } /* diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 0a8724e657d7..98ba46ecd5d8 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1911,12 +1911,14 @@ out: * * Not for syndrome calculating ECC controllers, which use a special oob layout. */ -static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, +static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { chip->write_buf(mtd, buf, mtd->writesize); if (oob_required) chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } /** @@ -1928,7 +1930,7 @@ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, * * We need a special oob layout and handling even when ECC isn't checked. */ -static void nand_write_page_raw_syndrome(struct mtd_info *mtd, +static int nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { @@ -1958,6 +1960,8 @@ static void nand_write_page_raw_syndrome(struct mtd_info *mtd, size = mtd->oobsize - (oob - chip->oob_poi); if (size) chip->write_buf(mtd, oob, size); + + return 0; } /** * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function @@ -1966,7 +1970,7 @@ static void nand_write_page_raw_syndrome(struct mtd_info *mtd, * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB */ -static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, +static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { int i, eccsize = chip->ecc.size; @@ -1983,7 +1987,7 @@ static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, for (i = 0; i < chip->ecc.total; i++) chip->oob_poi[eccpos[i]] = ecc_calc[i]; - chip->ecc.write_page_raw(mtd, chip, buf, 1); + return chip->ecc.write_page_raw(mtd, chip, buf, 1); } /** @@ -1993,7 +1997,7 @@ static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB */ -static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, +static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { int i, eccsize = chip->ecc.size; @@ -2013,6 +2017,8 @@ static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, chip->oob_poi[eccpos[i]] = ecc_calc[i]; chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } /** @@ -2025,7 +2031,7 @@ static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * The hw generator calculates the error syndrome automatically. Therefore we * need a special oob layout and handling. */ -static void nand_write_page_syndrome(struct mtd_info *mtd, +static int nand_write_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { @@ -2059,6 +2065,8 @@ static void nand_write_page_syndrome(struct mtd_info *mtd, i = mtd->oobsize - (oob - chip->oob_poi); if (i) chip->write_buf(mtd, oob, i); + + return 0; } /** @@ -2080,9 +2088,12 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); if (unlikely(raw)) - chip->ecc.write_page_raw(mtd, chip, buf, oob_required); + status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); else - chip->ecc.write_page(mtd, chip, buf, oob_required); + status = chip->ecc.write_page(mtd, chip, buf, oob_required); + + if (status < 0) + return status; /* * Cached progamming disabled for now. Not sure if it's worth the diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index afc4681f44d7..e8a1ae97a952 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -681,11 +681,13 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, info->state = STATE_IDLE; } -static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, +static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { chip->write_buf(mtd, buf, mtd->writesize); chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; } static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 2eb15418c227..ed03ed2355de 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -399,11 +399,12 @@ static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, return 0; } -static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, +static int flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { chip->write_buf(mtd, buf, mtd->writesize); chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + return 0; } static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) -- cgit v1.2.3 From 2944a44da09e46b6db2fd2c3334f242b09e05c43 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 7 Jun 2012 12:22:15 +0200 Subject: mtd: add LPC32xx SLC NAND driver This patch adds support for the SLC NAND controller inside the LPC32xx SoC. [dwmw2: 21st century pedantry] Signed-off-by: Roland Stigge Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 11 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_slc.c | 1065 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1077 insertions(+) create mode 100644 drivers/mtd/nand/lpc32xx_slc.c (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 31bb7e5b504a..b28b57ed51bc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -454,6 +454,17 @@ config MTD_NAND_PXA3xx This enables the driver for the NAND flash device found on PXA3xx processors +config MTD_NAND_SLC_LPC32XX + tristate "NXP LPC32xx SLC Controller" + depends on ARCH_LPC32XX + help + Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell + chips) NAND controller. This is the default for the PHYTEC 3250 + reference board which contains a NAND256R3A2CZA6 chip. + + Please check the actual NAND chip connected and its support + by the SLC NAND controller. + config MTD_NAND_CM_X270 tristate "Support for NAND Flash on CM-X270 modules" depends on MACH_ARMCORE diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index d4b4d8739bd8..d29a893608e7 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o +obj-$(CONFIG_MTD_NAND_SLC_LPC32XX) += lpc32xx_slc.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c new file mode 100644 index 000000000000..1d837b92ac79 --- /dev/null +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -0,0 +1,1065 @@ +/* + * NXP LPC32XX NAND SLC driver + * + * Authors: + * Kevin Wells + * Roland Stigge + * + * Copyright © 2011 NXP Semiconductors + * Copyright © 2012 Roland Stigge + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPC32XX_MODNAME "lpc32xx-nand" + +/********************************************************************** +* SLC NAND controller register offsets +**********************************************************************/ + +#define SLC_DATA(x) (x + 0x000) +#define SLC_ADDR(x) (x + 0x004) +#define SLC_CMD(x) (x + 0x008) +#define SLC_STOP(x) (x + 0x00C) +#define SLC_CTRL(x) (x + 0x010) +#define SLC_CFG(x) (x + 0x014) +#define SLC_STAT(x) (x + 0x018) +#define SLC_INT_STAT(x) (x + 0x01C) +#define SLC_IEN(x) (x + 0x020) +#define SLC_ISR(x) (x + 0x024) +#define SLC_ICR(x) (x + 0x028) +#define SLC_TAC(x) (x + 0x02C) +#define SLC_TC(x) (x + 0x030) +#define SLC_ECC(x) (x + 0x034) +#define SLC_DMA_DATA(x) (x + 0x038) + +/********************************************************************** +* slc_ctrl register definitions +**********************************************************************/ +#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */ +#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ +#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ + +/********************************************************************** +* slc_cfg register definitions +**********************************************************************/ +#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */ +#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ +#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ +#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ +#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ +#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */ + +/********************************************************************** +* slc_stat register definitions +**********************************************************************/ +#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ +#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */ +#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */ + +/********************************************************************** +* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions +**********************************************************************/ +#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */ +#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */ + +/********************************************************************** +* slc_tac register definitions +**********************************************************************/ +/* Clock setting for RDY write sample wait time in 2*n clocks */ +#define SLCTAC_WDR(n) (((n) & 0xF) << 28) +/* Write pulse width in clock cycles, 1 to 16 clocks */ +#define SLCTAC_WWIDTH(n) (((n) & 0xF) << 24) +/* Write hold time of control and data signals, 1 to 16 clocks */ +#define SLCTAC_WHOLD(n) (((n) & 0xF) << 20) +/* Write setup time of control and data signals, 1 to 16 clocks */ +#define SLCTAC_WSETUP(n) (((n) & 0xF) << 16) +/* Clock setting for RDY read sample wait time in 2*n clocks */ +#define SLCTAC_RDR(n) (((n) & 0xF) << 12) +/* Read pulse width in clock cycles, 1 to 16 clocks */ +#define SLCTAC_RWIDTH(n) (((n) & 0xF) << 8) +/* Read hold time of control and data signals, 1 to 16 clocks */ +#define SLCTAC_RHOLD(n) (((n) & 0xF) << 4) +/* Read setup time of control and data signals, 1 to 16 clocks */ +#define SLCTAC_RSETUP(n) (((n) & 0xF) << 0) + +/********************************************************************** +* slc_ecc register definitions +**********************************************************************/ +/* ECC line party fetch macro */ +#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF) +#define SLCECC_TO_COLPAR(n) ((n) & 0x3F) + +/* + * DMA requires storage space for the DMA local buffer and the hardware ECC + * storage area. The DMA local buffer is only used if DMA mapping fails + * during runtime. + */ +#define LPC32XX_DMA_DATA_SIZE 4096 +#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4) + +/* Number of bytes used for ECC stored in NAND per 256 bytes */ +#define LPC32XX_SLC_DEV_ECC_BYTES 3 + +/* + * If the NAND base clock frequency can't be fetched, this frequency will be + * used instead as the base. This rate is used to setup the timing registers + * used for NAND accesses. + */ +#define LPC32XX_DEF_BUS_RATE 133250000 + +/* Milliseconds for DMA FIFO timeout (unlikely anyway) */ +#define LPC32XX_DMA_TIMEOUT 100 + +/* + * NAND ECC Layout for small page NAND devices + * Note: For large and huge page devices, the default layouts are used + */ +static struct nand_ecclayout lpc32xx_nand_oob_16 = { + .eccbytes = 6, + .eccpos = {10, 11, 12, 13, 14, 15}, + .oobfree = { + { .offset = 0, .length = 4 }, + { .offset = 6, .length = 4 }, + }, +}; + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +/* + * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 + * Note: Large page devices used the default layout + */ +static struct nand_bbt_descr bbt_smallpage_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_smallpage_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/* + * NAND platform configuration structure + */ +struct lpc32xx_nand_cfg_slc { + uint32_t wdr_clks; + uint32_t wwidth; + uint32_t whold; + uint32_t wsetup; + uint32_t rdr_clks; + uint32_t rwidth; + uint32_t rhold; + uint32_t rsetup; + bool use_bbt; + unsigned wp_gpio; + struct mtd_partition *parts; + unsigned num_parts; +}; + +struct lpc32xx_nand_host { + struct nand_chip nand_chip; + struct clk *clk; + struct mtd_info mtd; + void __iomem *io_base; + struct lpc32xx_nand_cfg_slc *ncfg; + + struct completion comp; + struct dma_chan *dma_chan; + uint32_t dma_buf_len; + struct dma_slave_config dma_slave_config; + struct scatterlist sgl; + + /* + * DMA and CPU addresses of ECC work area and data buffer + */ + uint32_t *ecc_buf; + uint8_t *data_buf; + dma_addr_t io_base_dma; +}; + +static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) +{ + uint32_t clkrate, tmp; + + /* Reset SLC controller */ + writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); + udelay(1000); + + /* Basic setup */ + writel(0, SLC_CFG(host->io_base)); + writel(0, SLC_IEN(host->io_base)); + writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN), + SLC_ICR(host->io_base)); + + /* Get base clock for SLC block */ + clkrate = clk_get_rate(host->clk); + if (clkrate == 0) + clkrate = LPC32XX_DEF_BUS_RATE; + + /* Compute clock setup values */ + tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | + SLCTAC_WWIDTH(1 + (clkrate / host->ncfg->wwidth)) | + SLCTAC_WHOLD(1 + (clkrate / host->ncfg->whold)) | + SLCTAC_WSETUP(1 + (clkrate / host->ncfg->wsetup)) | + SLCTAC_RDR(host->ncfg->rdr_clks) | + SLCTAC_RWIDTH(1 + (clkrate / host->ncfg->rwidth)) | + SLCTAC_RHOLD(1 + (clkrate / host->ncfg->rhold)) | + SLCTAC_RSETUP(1 + (clkrate / host->ncfg->rsetup)); + writel(tmp, SLC_TAC(host->io_base)); +} + +/* + * Hardware specific access to control lines + */ +static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + uint32_t tmp; + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + + /* Does CE state need to be changed? */ + tmp = readl(SLC_CFG(host->io_base)); + if (ctrl & NAND_NCE) + tmp |= SLCCFG_CE_LOW; + else + tmp &= ~SLCCFG_CE_LOW; + writel(tmp, SLC_CFG(host->io_base)); + + if (cmd != NAND_CMD_NONE) { + if (ctrl & NAND_CLE) + writel(cmd, SLC_CMD(host->io_base)); + else + writel(cmd, SLC_ADDR(host->io_base)); + } +} + +/* + * Read the Device Ready pin + */ +static int lpc32xx_nand_device_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + int rdy = 0; + + if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) + rdy = 1; + + return rdy; +} + +/* + * Enable NAND write protect + */ +static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) +{ + gpio_set_value(host->ncfg->wp_gpio, 0); +} + +/* + * Disable NAND write protect + */ +static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) +{ + gpio_set_value(host->ncfg->wp_gpio, 1); +} + +/* + * Prepares SLC for transfers with H/W ECC enabled + */ +static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode) +{ + /* Hardware ECC is enabled automatically in hardware as needed */ +} + +/* + * Calculates the ECC for the data + */ +static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd, + const unsigned char *buf, + unsigned char *code) +{ + /* + * ECC is calculated automatically in hardware during syndrome read + * and write operations, so it doesn't need to be calculated here. + */ + return 0; +} + +/* + * Read a single byte from NAND device + */ +static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + + return (uint8_t)readl(SLC_DATA(host->io_base)); +} + +/* + * Simple device read without ECC + */ +static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + + /* Direct device read with no ECC */ + while (len-- > 0) + *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); +} + +/* + * Simple device write without ECC + */ +static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + + /* Direct device write with no ECC */ + while (len-- > 0) + writel((uint32_t)*buf++, SLC_DATA(host->io_base)); +} + +/* + * Verify data in buffer to data on device + */ +static int lpc32xx_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + int i; + + /* DATA register must be read as 32 bits or it will fail */ + for (i = 0; i < len; i++) { + if (buf[i] != (uint8_t)readl(SLC_DATA(host->io_base))) + return -EFAULT; + } + + return 0; +} + +/* + * Read the OOB data from the device without ECC using FIFO method + */ +static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} + +/* + * Write the OOB data to the device without ECC using FIFO method + */ +static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + int status; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + + /* Send command to program the OOB data */ + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + + status = chip->waitfunc(mtd, chip); + + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +/* + * Fills in the ECC fields in the OOB buffer with the hardware generated ECC + */ +static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) +{ + int i; + + for (i = 0; i < (count * 3); i += 3) { + uint32_t ce = ecc[i / 3]; + ce = ~(ce << 2) & 0xFFFFFF; + spare[i + 2] = (uint8_t)(ce & 0xFF); + ce >>= 8; + spare[i + 1] = (uint8_t)(ce & 0xFF); + ce >>= 8; + spare[i] = (uint8_t)(ce & 0xFF); + } +} + +static void lpc32xx_dma_complete_func(void *completion) +{ + complete(completion); +} + +static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, + void *mem, int len, enum dma_transfer_direction dir) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + struct dma_async_tx_descriptor *desc; + int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; + int res; + + host->dma_slave_config.direction = dir; + host->dma_slave_config.src_addr = dma; + host->dma_slave_config.dst_addr = dma; + host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + host->dma_slave_config.src_maxburst = 4; + host->dma_slave_config.dst_maxburst = 4; + /* DMA controller does flow control: */ + host->dma_slave_config.device_fc = false; + if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { + dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); + return -ENXIO; + } + + sg_init_one(&host->sgl, mem, len); + + res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, + DMA_BIDIRECTIONAL); + if (res != 1) { + dev_err(mtd->dev.parent, "Failed to map sg list\n"); + return -ENXIO; + } + desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, + flags); + if (!desc) { + dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); + goto out1; + } + + init_completion(&host->comp); + desc->callback = lpc32xx_dma_complete_func; + desc->callback_param = &host->comp; + + dmaengine_submit(desc); + dma_async_issue_pending(host->dma_chan); + + wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); + + dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, + DMA_BIDIRECTIONAL); + + return 0; +out1: + dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, + DMA_BIDIRECTIONAL); + return -ENXIO; +} + +/* + * DMA read/write transfers with ECC support + */ +static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, + int read) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + int i, status = 0; + unsigned long timeout; + int res; + enum dma_transfer_direction dir = + read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; + uint8_t *dma_buf; + bool dma_mapped; + + if ((void *)buf <= high_memory) { + dma_buf = buf; + dma_mapped = true; + } else { + dma_buf = host->data_buf; + dma_mapped = false; + if (!read) + memcpy(host->data_buf, buf, mtd->writesize); + } + + if (read) { + writel(readl(SLC_CFG(host->io_base)) | + SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | + SLCCFG_DMA_BURST, SLC_CFG(host->io_base)); + } else { + writel((readl(SLC_CFG(host->io_base)) | + SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) & + ~SLCCFG_DMA_DIR, + SLC_CFG(host->io_base)); + } + + /* Clear initial ECC */ + writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base)); + + /* Transfer size is data area only */ + writel(mtd->writesize, SLC_TC(host->io_base)); + + /* Start transfer in the NAND controller */ + writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START, + SLC_CTRL(host->io_base)); + + for (i = 0; i < chip->ecc.steps; i++) { + /* Data */ + res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma), + dma_buf + i * chip->ecc.size, + mtd->writesize / chip->ecc.steps, dir); + if (res) + return res; + + /* Always _read_ ECC */ + if (i == chip->ecc.steps - 1) + break; + if (!read) /* ECC availability delayed on write */ + udelay(10); + res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma), + &host->ecc_buf[i], 4, DMA_DEV_TO_MEM); + if (res) + return res; + } + + /* + * According to NXP, the DMA can be finished here, but the NAND + * controller may still have buffered data. After porting to using the + * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty) + * appears to be always true, according to tests. Keeping the check for + * safety reasons for now. + */ + if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) { + dev_warn(mtd->dev.parent, "FIFO not empty!\n"); + timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT); + while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) && + time_before(jiffies, timeout)) + cpu_relax(); + if (!time_before(jiffies, timeout)) { + dev_err(mtd->dev.parent, "FIFO held data too long\n"); + status = -EIO; + } + } + + /* Read last calculated ECC value */ + if (!read) + udelay(10); + host->ecc_buf[chip->ecc.steps - 1] = + readl(SLC_ECC(host->io_base)); + + /* Flush DMA */ + dmaengine_terminate_all(host->dma_chan); + + if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO || + readl(SLC_TC(host->io_base))) { + /* Something is left in the FIFO, something is wrong */ + dev_err(mtd->dev.parent, "DMA FIFO failure\n"); + status = -EIO; + } + + /* Stop DMA & HW ECC */ + writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START, + SLC_CTRL(host->io_base)); + writel(readl(SLC_CFG(host->io_base)) & + ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | + SLCCFG_DMA_BURST), SLC_CFG(host->io_base)); + + if (!dma_mapped && read) + memcpy(buf, host->data_buf, mtd->writesize); + + return status; +} + +/* + * Read the data and OOB data from the device, use ECC correction with the + * data, disable ECC for the OOB data + */ +static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +{ + struct lpc32xx_nand_host *host = chip->priv; + int stat, i, status; + uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE]; + + /* Issue read command */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + /* Read data and oob, calculate ECC */ + status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); + + /* Get OOB data */ + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + /* Convert to stored ECC format */ + lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); + + /* Pointer to ECC data retrieved from NAND spare area */ + oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0]; + + for (i = 0; i < chip->ecc.steps; i++) { + stat = chip->ecc.correct(mtd, buf, oobecc, + &tmpecc[i * chip->ecc.bytes]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + buf += chip->ecc.size; + oobecc += chip->ecc.bytes; + } + + return status; +} + +/* + * Read the data and OOB data from the device, no ECC correction with the + * data or OOB data + */ +static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, int oob_required, + int page) +{ + /* Issue read command */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + /* Raw reads can just use the FIFO interface */ + chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} + +/* + * Write the data and OOB data to the device, use ECC with the data, + * disable ECC for the OOB data + */ +static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + struct lpc32xx_nand_host *host = chip->priv; + uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0]; + int error; + + /* Write data, calculate ECC on outbound data */ + error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0); + if (error) + return error; + + /* + * The calculated ECC needs some manual work done to it before + * committing it to NAND. Process the calculated ECC and place + * the resultant values directly into the OOB buffer. */ + lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); + + /* Write ECC data to device */ + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + return 0; +} + +/* + * Write the data and OOB data to the device, no ECC correction with the + * data or OOB data + */ +static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, + int oob_required) +{ + /* Raw writes can just use the FIFO interface */ + chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps); + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + return 0; +} + +static bool lpc32xx_dma_filter(struct dma_chan *chan, void *param) +{ + struct pl08x_dma_chan *ch = + container_of(chan, struct pl08x_dma_chan, chan); + + /* In LPC32xx's PL080 DMA wiring, the SLC NAND DMA signal is #1 */ + if (ch->cd->min_signal == 1) + return true; + return false; +} + +static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) +{ + struct mtd_info *mtd = &host->mtd; + dma_cap_mask_t mask; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + host->dma_chan = dma_request_channel(mask, lpc32xx_dma_filter, NULL); + if (!host->dma_chan) { + dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); + return -EBUSY; + } + + return 0; +} + +#ifdef CONFIG_OF +static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) +{ + struct lpc32xx_nand_cfg_slc *pdata; + struct device_node *np = dev->of_node; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(dev, "could not allocate memory for platform data\n"); + return NULL; + } + + of_property_read_u32(np, "nxp,wdr-clks", &pdata->wdr_clks); + of_property_read_u32(np, "nxp,wwidth", &pdata->wwidth); + of_property_read_u32(np, "nxp,whold", &pdata->whold); + of_property_read_u32(np, "nxp,wsetup", &pdata->wsetup); + of_property_read_u32(np, "nxp,rdr-clks", &pdata->rdr_clks); + of_property_read_u32(np, "nxp,rwidth", &pdata->rwidth); + of_property_read_u32(np, "nxp,rhold", &pdata->rhold); + of_property_read_u32(np, "nxp,rsetup", &pdata->rsetup); + + if (!pdata->wdr_clks || !pdata->wwidth || !pdata->whold || + !pdata->wsetup || !pdata->rdr_clks || !pdata->rwidth || + !pdata->rhold || !pdata->rsetup) { + dev_err(dev, "chip parameters not specified correctly\n"); + return NULL; + } + + pdata->use_bbt = of_get_nand_on_flash_bbt(np); + pdata->wp_gpio = of_get_named_gpio_flags(np, "gpios", 0, NULL); + + return pdata; +} +#else +static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) +{ + return NULL; +} +#endif + +/* + * Probe for NAND controller + */ +static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) +{ + struct lpc32xx_nand_host *host; + struct mtd_info *mtd; + struct nand_chip *chip; + struct resource *rc; + struct mtd_part_parser_data ppdata = {}; + int res; + + rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (rc == NULL) { + dev_err(&pdev->dev, "No memory resource found for device\n"); + return -EBUSY; + } + + /* Allocate memory for the device structure (and zero it) */ + host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); + if (!host) { + dev_err(&pdev->dev, "failed to allocate device structure\n"); + return -ENOMEM; + } + host->io_base_dma = rc->start; + + host->io_base = devm_request_and_ioremap(&pdev->dev, rc); + if (host->io_base == NULL) { + dev_err(&pdev->dev, "ioremap failed\n"); + return -ENOMEM; + } + + if (pdev->dev.of_node) + host->ncfg = lpc32xx_parse_dt(&pdev->dev); + else + host->ncfg = pdev->dev.platform_data; + if (!host->ncfg) { + dev_err(&pdev->dev, "Missing platform data\n"); + return -ENOENT; + } + if (gpio_request(host->ncfg->wp_gpio, "NAND WP")) { + dev_err(&pdev->dev, "GPIO not available\n"); + return -EBUSY; + } + lpc32xx_wp_disable(host); + + mtd = &host->mtd; + chip = &host->nand_chip; + chip->priv = host; + mtd->priv = chip; + mtd->owner = THIS_MODULE; + mtd->dev.parent = &pdev->dev; + + /* Get NAND clock */ + host->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(host->clk)) { + dev_err(&pdev->dev, "Clock failure\n"); + res = -ENOENT; + goto err_exit1; + } + clk_enable(host->clk); + + /* Set NAND IO addresses and command/ready functions */ + chip->IO_ADDR_R = SLC_DATA(host->io_base); + chip->IO_ADDR_W = SLC_DATA(host->io_base); + chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; + chip->dev_ready = lpc32xx_nand_device_ready; + chip->chip_delay = 20; /* 20us command delay time */ + + /* Init NAND controller */ + lpc32xx_nand_setup(host); + + platform_set_drvdata(pdev, host); + + /* NAND callbacks for LPC32xx SLC hardware */ + chip->ecc.mode = NAND_ECC_HW_SYNDROME; + chip->read_byte = lpc32xx_nand_read_byte; + chip->read_buf = lpc32xx_nand_read_buf; + chip->write_buf = lpc32xx_nand_write_buf; + chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; + chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; + chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; + chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; + chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; + chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; + chip->ecc.calculate = lpc32xx_nand_ecc_calculate; + chip->ecc.correct = nand_correct_data; + chip->ecc.strength = 1; + chip->ecc.hwctl = lpc32xx_nand_ecc_enable; + chip->verify_buf = lpc32xx_verify_buf; + + /* bitflip_threshold's default is defined as ecc_strength anyway. + * Unfortunately, it is set only later at add_mtd_device(). Meanwhile + * being 0, it causes bad block table scanning errors in + * nand_scan_tail(), so preparing it here already. */ + mtd->bitflip_threshold = chip->ecc.strength; + + /* + * Allocate a large enough buffer for a single huge page plus + * extra space for the spare area and ECC storage area + */ + host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE; + host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, + GFP_KERNEL); + if (host->data_buf == NULL) { + dev_err(&pdev->dev, "Error allocating memory\n"); + res = -ENOMEM; + goto err_exit2; + } + + res = lpc32xx_nand_dma_setup(host); + if (res) { + res = -EIO; + goto err_exit2; + } + + /* Find NAND device */ + if (nand_scan_ident(mtd, 1, NULL)) { + res = -ENXIO; + goto err_exit3; + } + + /* OOB and ECC CPU and DMA work areas */ + host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); + + /* + * Small page FLASH has a unique OOB layout, but large and huge + * page FLASH use the standard layout. Small page FLASH uses a + * custom BBT marker layout. + */ + if (mtd->writesize <= 512) + chip->ecc.layout = &lpc32xx_nand_oob_16; + + /* These sizes remain the same regardless of page size */ + chip->ecc.size = 256; + chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; + chip->ecc.prepad = chip->ecc.postpad = 0; + + /* Avoid extra scan if using BBT, setup BBT support */ + if (host->ncfg->use_bbt) { + chip->options |= NAND_SKIP_BBTSCAN; + chip->bbt_options |= NAND_BBT_USE_FLASH; + + /* + * Use a custom BBT marker setup for small page FLASH that + * won't interfere with the ECC layout. Large and huge page + * FLASH use the standard layout. + */ + if (mtd->writesize <= 512) { + chip->bbt_td = &bbt_smallpage_main_descr; + chip->bbt_md = &bbt_smallpage_mirror_descr; + } + } + + /* + * Fills out all the uninitialized function pointers with the defaults + */ + if (nand_scan_tail(mtd)) { + res = -ENXIO; + goto err_exit3; + } + + /* Standard layout in FLASH for bad block tables */ + if (host->ncfg->use_bbt) { + if (nand_default_bbt(mtd) < 0) + dev_err(&pdev->dev, + "Error initializing default bad block tables\n"); + } + + mtd->name = "nxp_lpc3220_slc"; + ppdata.of_node = pdev->dev.of_node; + res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts, + host->ncfg->num_parts); + if (!res) + return res; + + nand_release(mtd); + +err_exit3: + dma_release_channel(host->dma_chan); +err_exit2: + clk_disable(host->clk); + clk_put(host->clk); + platform_set_drvdata(pdev, NULL); +err_exit1: + lpc32xx_wp_enable(host); + gpio_free(host->ncfg->wp_gpio); + + return res; +} + +/* + * Remove NAND device. + */ +static int __devexit lpc32xx_nand_remove(struct platform_device *pdev) +{ + uint32_t tmp; + struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); + struct mtd_info *mtd = &host->mtd; + + nand_release(mtd); + dma_release_channel(host->dma_chan); + + /* Force CE high */ + tmp = readl(SLC_CTRL(host->io_base)); + tmp &= ~SLCCFG_CE_LOW; + writel(tmp, SLC_CTRL(host->io_base)); + + clk_disable(host->clk); + clk_put(host->clk); + platform_set_drvdata(pdev, NULL); + lpc32xx_wp_enable(host); + gpio_free(host->ncfg->wp_gpio); + + return 0; +} + +#ifdef CONFIG_PM +static int lpc32xx_nand_resume(struct platform_device *pdev) +{ + struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); + + /* Re-enable NAND clock */ + clk_enable(host->clk); + + /* Fresh init of NAND controller */ + lpc32xx_nand_setup(host); + + /* Disable write protect */ + lpc32xx_wp_disable(host); + + return 0; +} + +static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) +{ + uint32_t tmp; + struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); + + /* Force CE high */ + tmp = readl(SLC_CTRL(host->io_base)); + tmp &= ~SLCCFG_CE_LOW; + writel(tmp, SLC_CTRL(host->io_base)); + + /* Enable write protect for safety */ + lpc32xx_wp_enable(host); + + /* Disable clock */ + clk_disable(host->clk); + + return 0; +} + +#else +#define lpc32xx_nand_resume NULL +#define lpc32xx_nand_suspend NULL +#endif + +#if defined(CONFIG_OF) +static const struct of_device_id lpc32xx_nand_match[] = { + { .compatible = "nxp,lpc3220-slc" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); +#endif + +static struct platform_driver lpc32xx_nand_driver = { + .probe = lpc32xx_nand_probe, + .remove = __devexit_p(lpc32xx_nand_remove), + .resume = lpc32xx_nand_resume, + .suspend = lpc32xx_nand_suspend, + .driver = { + .name = LPC32XX_MODNAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(lpc32xx_nand_match), + }, +}; + +module_platform_driver(lpc32xx_nand_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Kevin Wells "); +MODULE_AUTHOR("Roland Stigge "); +MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller"); -- cgit v1.2.3 From 9d9a8811622e36611e8eeb2401e4e9805d4727f3 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 20 Jun 2012 16:14:02 -0700 Subject: mtd: nand: change "AMD" manuf. ID to "AMD/Spansion" This manufacturer ID is used under the name Spansion. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index e04c675bf609..e3aa2748a6e7 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -174,7 +174,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix"}, {NAND_MFR_MICRON, "Micron"}, - {NAND_MFR_AMD, "AMD"}, + {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, {0x0, "Unknown"} -- cgit v1.2.3 From 947c9adb4280f495ff4810f52728f7e0cd3f5554 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Fri, 22 Jun 2012 15:29:28 +0200 Subject: mtd: nand: remove stale config options The commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c removed the use of CONFIG_MTD_NAND_ATMEL_ECC_NONE and CONFIG_MTD_NAND_ATMEL_ECC_HW but the Kconfig file was forgotten. This patch remove those inoperative options. Signed-off-by: Richard Genoud Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 40 ---------------------------------------- 1 file changed, 40 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index b28b57ed51bc..de6997832dad 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -406,46 +406,6 @@ config MTD_NAND_ATMEL help Enables support for NAND Flash / Smart Media Card interface on Atmel AT91 and AVR32 processors. -choice - prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32" - depends on MTD_NAND_ATMEL - -config MTD_NAND_ATMEL_ECC_HW - bool "Hardware ECC" - depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32 - help - Use hardware ECC instead of software ECC when the chip - supports it. - - The hardware ECC controller is capable of single bit error - correction and 2-bit random detection per page. - - NB : hardware and software ECC schemes are incompatible. - If you switch from one to another, you'll have to erase your - mtd partition. - - If unsure, say Y - -config MTD_NAND_ATMEL_ECC_SOFT - bool "Software ECC" - help - Use software ECC. - - NB : hardware and software ECC schemes are incompatible. - If you switch from one to another, you'll have to erase your - mtd partition. - -config MTD_NAND_ATMEL_ECC_NONE - bool "No ECC (testing only, DANGEROUS)" - depends on DEBUG_KERNEL - help - No ECC will be used. - It's not a good idea and it should be reserved for testing - purpose only. - - If unsure, say N - -endchoice config MTD_NAND_PXA3xx tristate "Support for NAND flash devices on PXA3xx" -- cgit v1.2.3 From 9fd6b37a08d49c5f9b108509fde8d618f74fb7ad Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Jun 2012 16:35:40 -0700 Subject: mtd: nand: rename "no_bbt" descriptors to "no_oob" These descriptors are for BBT's that don't use OOB; the "no_bbt" name doesn't really make sense. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index c126469b0645..dff24fa44cd2 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -1274,7 +1274,7 @@ static struct nand_bbt_descr bbt_mirror_descr = { .pattern = mirror_pattern }; -static struct nand_bbt_descr bbt_main_no_bbt_descr = { +static struct nand_bbt_descr bbt_main_no_oob_descr = { .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP | NAND_BBT_NO_OOB, @@ -1284,7 +1284,7 @@ static struct nand_bbt_descr bbt_main_no_bbt_descr = { .pattern = bbt_pattern }; -static struct nand_bbt_descr bbt_mirror_no_bbt_descr = { +static struct nand_bbt_descr bbt_mirror_no_oob_descr = { .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP | NAND_BBT_NO_OOB, @@ -1355,8 +1355,8 @@ int nand_default_bbt(struct mtd_info *mtd) /* Use the default pattern descriptors */ if (!this->bbt_td) { if (this->bbt_options & NAND_BBT_NO_OOB) { - this->bbt_td = &bbt_main_no_bbt_descr; - this->bbt_md = &bbt_mirror_no_bbt_descr; + this->bbt_td = &bbt_main_no_oob_descr; + this->bbt_md = &bbt_mirror_no_oob_descr; } else { this->bbt_td = &bbt_main_descr; this->bbt_md = &bbt_mirror_descr; -- cgit v1.2.3 From 718894ad94626b72403c21fab5ccdd982147e4c6 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Jun 2012 16:35:43 -0700 Subject: mtd: nand_bbt: refactor check_pattern_no_oob() This function only returns 0 or -1, so make that clear. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index dff24fa44cd2..3df8d92c5e08 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -71,12 +71,9 @@ static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) { - int ret; - - ret = memcmp(buf, td->pattern, td->len); - if (!ret) - return ret; - return -1; + if (memcmp(buf, td->pattern, td->len)) + return -1; + return 0; } /** -- cgit v1.2.3 From a41b51a1f7c15a1b00f30a3ad2d0373ad51b883d Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Fri, 29 Jun 2012 17:47:54 +0800 Subject: mtd: at91: add dt parameters for Atmel PMECC Add DT support for PMECC parameters. Signed-off-by: Hong Xu Signed-off-by: Josh Wu Acked-by: Nicolas Ferre Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/atmel_nand.c | 52 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 7a41a04beb87..b97ad9f78d39 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -93,6 +93,11 @@ struct atmel_nand_host { struct completion comp; struct dma_chan *dma_chan; + + bool has_pmecc; + u8 pmecc_corr_cap; + u16 pmecc_sector_size; + u32 pmecc_lookup_table_offset; }; static int cpu_has_dma(void) @@ -481,7 +486,8 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) static int __devinit atmel_of_init_port(struct atmel_nand_host *host, struct device_node *np) { - u32 val; + u32 val, table_offset; + u32 offset[2]; int ecc_mode; struct atmel_nand_data *board = &host->board; enum of_gpio_flags flags; @@ -517,6 +523,50 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host, board->enable_pin = of_get_gpio(np, 1); board->det_pin = of_get_gpio(np, 2); + host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc"); + + if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc) + return 0; /* Not using PMECC */ + + /* use PMECC, get correction capability, sector size and lookup + * table offset. + */ + if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) { + dev_err(host->dev, "Cannot decide PMECC Capability\n"); + return -EINVAL; + } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) && + (val != 24)) { + dev_err(host->dev, + "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n", + val); + return -EINVAL; + } + host->pmecc_corr_cap = (u8)val; + + if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) { + dev_err(host->dev, "Cannot decide PMECC Sector Size\n"); + return -EINVAL; + } else if ((val != 512) && (val != 1024)) { + dev_err(host->dev, + "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n", + val); + return -EINVAL; + } + host->pmecc_sector_size = (u16)val; + + if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset", + offset, 2) != 0) { + dev_err(host->dev, "Cannot get PMECC lookup table offset\n"); + return -EINVAL; + } + table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1]; + + if (!table_offset) { + dev_err(host->dev, "Invalid PMECC lookup table offset\n"); + return -EINVAL; + } + host->pmecc_lookup_table_offset = table_offset; + return 0; } #else -- cgit v1.2.3 From 1c7b874d33b463f7150b1ab4617f000af9b327fd Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Fri, 29 Jun 2012 17:47:55 +0800 Subject: mtd: at91: atmel_nand: add Programmable Multibit ECC controller support The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller can be used to support both SLC and MLC NAND Flash devices. It supports to generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. To use PMECC in this driver, the user needs to set the address and size of PMECC, PMECC error location controllers and ROM. And also needs to pass the correction capability, the sector size and ROM lookup table offsets via dt. This driver has been tested on AT91SAM9X5-EK and AT91SAM9N12-EK with JFFS2, YAFFS2, UBIFS and mtd-utils. Signed-off-by: Hong Xu Signed-off-by: Josh Wu Tested-by: Richard Genoud Acked-by: Nicolas Ferre Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/atmel_nand.c | 757 +++++++++++++++++++++++++++++++++++++- drivers/mtd/nand/atmel_nand_ecc.h | 114 +++++- 2 files changed, 864 insertions(+), 7 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index b97ad9f78d39..647275524e09 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1,20 +1,22 @@ /* - * Copyright (C) 2003 Rick Bronson + * Copyright © 2003 Rick Bronson * * Derived from drivers/mtd/nand/autcpu12.c - * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) + * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de) * * Derived from drivers/mtd/spia.c - * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) + * Copyright © 2000 Steven J. Hill (sjhill@cotw.com) * * * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 - * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007 * * Derived from Das U-Boot source code * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) - * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas * + * Add Programmable Multibit ECC support for various AT91 SoC + * © Copyright 2012 ATMEL, Hong Xu * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -98,8 +100,31 @@ struct atmel_nand_host { u8 pmecc_corr_cap; u16 pmecc_sector_size; u32 pmecc_lookup_table_offset; + + int pmecc_bytes_per_sector; + int pmecc_sector_number; + int pmecc_degree; /* Degree of remainders */ + int pmecc_cw_len; /* Length of codeword */ + + void __iomem *pmerrloc_base; + void __iomem *pmecc_rom_base; + + /* lookup table for alpha_to and index_of */ + void __iomem *pmecc_alpha_to; + void __iomem *pmecc_index_of; + + /* data for pmecc computation */ + int16_t *pmecc_partial_syn; + int16_t *pmecc_si; + int16_t *pmecc_smu; /* Sigma table */ + int16_t *pmecc_lmu; /* polynomal order */ + int *pmecc_mu; + int *pmecc_dmu; + int *pmecc_delta; }; +static struct nand_ecclayout atmel_pmecc_oobinfo; + static int cpu_has_dma(void) { return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); @@ -292,6 +317,703 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) atmel_write_buf8(mtd, buf, len); } +/* + * Return number of ecc bytes per sector according to sector size and + * correction capability + * + * Following table shows what at91 PMECC supported: + * Correction Capability Sector_512_bytes Sector_1024_bytes + * ===================== ================ ================= + * 2-bits 4-bytes 4-bytes + * 4-bits 7-bytes 7-bytes + * 8-bits 13-bytes 14-bytes + * 12-bits 20-bytes 21-bytes + * 24-bits 39-bytes 42-bytes + */ +static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size) +{ + int m = 12 + sector_size / 512; + return (m * cap + 7) / 8; +} + +static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout, + int oobsize, int ecc_len) +{ + int i; + + layout->eccbytes = ecc_len; + + /* ECC will occupy the last ecc_len bytes continuously */ + for (i = 0; i < ecc_len; i++) + layout->eccpos[i] = oobsize - ecc_len + i; + + layout->oobfree[0].offset = 2; + layout->oobfree[0].length = + oobsize - ecc_len - layout->oobfree[0].offset; +} + +static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host) +{ + int table_size; + + table_size = host->pmecc_sector_size == 512 ? + PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024; + + return host->pmecc_rom_base + host->pmecc_lookup_table_offset + + table_size * sizeof(int16_t); +} + +static void pmecc_data_free(struct atmel_nand_host *host) +{ + kfree(host->pmecc_partial_syn); + kfree(host->pmecc_si); + kfree(host->pmecc_lmu); + kfree(host->pmecc_smu); + kfree(host->pmecc_mu); + kfree(host->pmecc_dmu); + kfree(host->pmecc_delta); +} + +static int __devinit pmecc_data_alloc(struct atmel_nand_host *host) +{ + const int cap = host->pmecc_corr_cap; + + host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t), + GFP_KERNEL); + host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL); + host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL); + host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t), + GFP_KERNEL); + host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); + host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); + host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); + + if (host->pmecc_partial_syn && + host->pmecc_si && + host->pmecc_lmu && + host->pmecc_smu && + host->pmecc_mu && + host->pmecc_dmu && + host->pmecc_delta) + return 0; + + /* error happened */ + pmecc_data_free(host); + return -ENOMEM; +} + +static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + int i; + uint32_t value; + + /* Fill odd syndromes */ + for (i = 0; i < host->pmecc_corr_cap; i++) { + value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2); + if (i & 1) + value >>= 16; + value &= 0xffff; + host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value; + } +} + +static void pmecc_substitute(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + int16_t __iomem *alpha_to = host->pmecc_alpha_to; + int16_t __iomem *index_of = host->pmecc_index_of; + int16_t *partial_syn = host->pmecc_partial_syn; + const int cap = host->pmecc_corr_cap; + int16_t *si; + int i, j; + + /* si[] is a table that holds the current syndrome value, + * an element of that table belongs to the field + */ + si = host->pmecc_si; + + memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1)); + + /* Computation 2t syndromes based on S(x) */ + /* Odd syndromes */ + for (i = 1; i < 2 * cap; i += 2) { + for (j = 0; j < host->pmecc_degree; j++) { + if (partial_syn[i] & ((unsigned short)0x1 << j)) + si[i] = readw_relaxed(alpha_to + i * j) ^ si[i]; + } + } + /* Even syndrome = (Odd syndrome) ** 2 */ + for (i = 2, j = 1; j <= cap; i = ++j << 1) { + if (si[j] == 0) { + si[i] = 0; + } else { + int16_t tmp; + + tmp = readw_relaxed(index_of + si[j]); + tmp = (tmp * 2) % host->pmecc_cw_len; + si[i] = readw_relaxed(alpha_to + tmp); + } + } + + return; +} + +static void pmecc_get_sigma(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + + int16_t *lmu = host->pmecc_lmu; + int16_t *si = host->pmecc_si; + int *mu = host->pmecc_mu; + int *dmu = host->pmecc_dmu; /* Discrepancy */ + int *delta = host->pmecc_delta; /* Delta order */ + int cw_len = host->pmecc_cw_len; + const int16_t cap = host->pmecc_corr_cap; + const int num = 2 * cap + 1; + int16_t __iomem *index_of = host->pmecc_index_of; + int16_t __iomem *alpha_to = host->pmecc_alpha_to; + int i, j, k; + uint32_t dmu_0_count, tmp; + int16_t *smu = host->pmecc_smu; + + /* index of largest delta */ + int ro; + int largest; + int diff; + + dmu_0_count = 0; + + /* First Row */ + + /* Mu */ + mu[0] = -1; + + memset(smu, 0, sizeof(int16_t) * num); + smu[0] = 1; + + /* discrepancy set to 1 */ + dmu[0] = 1; + /* polynom order set to 0 */ + lmu[0] = 0; + delta[0] = (mu[0] * 2 - lmu[0]) >> 1; + + /* Second Row */ + + /* Mu */ + mu[1] = 0; + /* Sigma(x) set to 1 */ + memset(&smu[num], 0, sizeof(int16_t) * num); + smu[num] = 1; + + /* discrepancy set to S1 */ + dmu[1] = si[1]; + + /* polynom order set to 0 */ + lmu[1] = 0; + + delta[1] = (mu[1] * 2 - lmu[1]) >> 1; + + /* Init the Sigma(x) last row */ + memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num); + + for (i = 1; i <= cap; i++) { + mu[i + 1] = i << 1; + /* Begin Computing Sigma (Mu+1) and L(mu) */ + /* check if discrepancy is set to 0 */ + if (dmu[i] == 0) { + dmu_0_count++; + + tmp = ((cap - (lmu[i] >> 1) - 1) / 2); + if ((cap - (lmu[i] >> 1) - 1) & 0x1) + tmp += 2; + else + tmp += 1; + + if (dmu_0_count == tmp) { + for (j = 0; j <= (lmu[i] >> 1) + 1; j++) + smu[(cap + 1) * num + j] = + smu[i * num + j]; + + lmu[cap + 1] = lmu[i]; + return; + } + + /* copy polynom */ + for (j = 0; j <= lmu[i] >> 1; j++) + smu[(i + 1) * num + j] = smu[i * num + j]; + + /* copy previous polynom order to the next */ + lmu[i + 1] = lmu[i]; + } else { + ro = 0; + largest = -1; + /* find largest delta with dmu != 0 */ + for (j = 0; j < i; j++) { + if ((dmu[j]) && (delta[j] > largest)) { + largest = delta[j]; + ro = j; + } + } + + /* compute difference */ + diff = (mu[i] - mu[ro]); + + /* Compute degree of the new smu polynomial */ + if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff)) + lmu[i + 1] = lmu[i]; + else + lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2; + + /* Init smu[i+1] with 0 */ + for (k = 0; k < num; k++) + smu[(i + 1) * num + k] = 0; + + /* Compute smu[i+1] */ + for (k = 0; k <= lmu[ro] >> 1; k++) { + int16_t a, b, c; + + if (!(smu[ro * num + k] && dmu[i])) + continue; + a = readw_relaxed(index_of + dmu[i]); + b = readw_relaxed(index_of + dmu[ro]); + c = readw_relaxed(index_of + smu[ro * num + k]); + tmp = a + (cw_len - b) + c; + a = readw_relaxed(alpha_to + tmp % cw_len); + smu[(i + 1) * num + (k + diff)] = a; + } + + for (k = 0; k <= lmu[i] >> 1; k++) + smu[(i + 1) * num + k] ^= smu[i * num + k]; + } + + /* End Computing Sigma (Mu+1) and L(mu) */ + /* In either case compute delta */ + delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1; + + /* Do not compute discrepancy for the last iteration */ + if (i >= cap) + continue; + + for (k = 0; k <= (lmu[i + 1] >> 1); k++) { + tmp = 2 * (i - 1); + if (k == 0) { + dmu[i + 1] = si[tmp + 3]; + } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) { + int16_t a, b, c; + a = readw_relaxed(index_of + + smu[(i + 1) * num + k]); + b = si[2 * (i - 1) + 3 - k]; + c = readw_relaxed(index_of + b); + tmp = a + c; + tmp %= cw_len; + dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^ + dmu[i + 1]; + } + } + } + + return; +} + +static int pmecc_err_location(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + unsigned long end_time; + const int cap = host->pmecc_corr_cap; + const int num = 2 * cap + 1; + int sector_size = host->pmecc_sector_size; + int err_nbr = 0; /* number of error */ + int roots_nbr; /* number of roots */ + int i; + uint32_t val; + int16_t *smu = host->pmecc_smu; + + pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE); + + for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) { + pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i, + smu[(cap + 1) * num + i]); + err_nbr++; + } + + val = (err_nbr - 1) << 16; + if (sector_size == 1024) + val |= 1; + + pmerrloc_writel(host->pmerrloc_base, ELCFG, val); + pmerrloc_writel(host->pmerrloc_base, ELEN, + sector_size * 8 + host->pmecc_degree * cap); + + end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); + while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR) + & PMERRLOC_CALC_DONE)) { + if (unlikely(time_after(jiffies, end_time))) { + dev_err(host->dev, "PMECC: Timeout to calculate error location.\n"); + return -1; + } + cpu_relax(); + } + + roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR) + & PMERRLOC_ERR_NUM_MASK) >> 8; + /* Number of roots == degree of smu hence <= cap */ + if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1) + return err_nbr - 1; + + /* Number of roots does not match the degree of smu + * unable to correct error */ + return -1; +} + +static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, + int sector_num, int extra_bytes, int err_nbr) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + int i = 0; + int byte_pos, bit_pos, sector_size, pos; + uint32_t tmp; + uint8_t err_byte; + + sector_size = host->pmecc_sector_size; + + while (err_nbr) { + tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1; + byte_pos = tmp / 8; + bit_pos = tmp % 8; + + if (byte_pos >= (sector_size + extra_bytes)) + BUG(); /* should never happen */ + + if (byte_pos < sector_size) { + err_byte = *(buf + byte_pos); + *(buf + byte_pos) ^= (1 << bit_pos); + + pos = sector_num * host->pmecc_sector_size + byte_pos; + dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", + pos, bit_pos, err_byte, *(buf + byte_pos)); + } else { + /* Bit flip in OOB area */ + tmp = sector_num * host->pmecc_bytes_per_sector + + (byte_pos - sector_size); + err_byte = ecc[tmp]; + ecc[tmp] ^= (1 << bit_pos); + + pos = tmp + nand_chip->ecc.layout->eccpos[0]; + dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", + pos, bit_pos, err_byte, ecc[tmp]); + } + + i++; + err_nbr--; + } + + return; +} + +static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, + u8 *ecc) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + int i, err_nbr, eccbytes; + uint8_t *buf_pos; + + eccbytes = nand_chip->ecc.bytes; + for (i = 0; i < eccbytes; i++) + if (ecc[i] != 0xff) + goto normal_check; + /* Erased page, return OK */ + return 0; + +normal_check: + for (i = 0; i < host->pmecc_sector_number; i++) { + err_nbr = 0; + if (pmecc_stat & 0x1) { + buf_pos = buf + i * host->pmecc_sector_size; + + pmecc_gen_syndrome(mtd, i); + pmecc_substitute(mtd); + pmecc_get_sigma(mtd); + + err_nbr = pmecc_err_location(mtd); + if (err_nbr == -1) { + dev_err(host->dev, "PMECC: Too many errors\n"); + mtd->ecc_stats.failed++; + return -EIO; + } else { + pmecc_correct_data(mtd, buf_pos, ecc, i, + host->pmecc_bytes_per_sector, err_nbr); + mtd->ecc_stats.corrected += err_nbr; + } + } + pmecc_stat >>= 1; + } + + return 0; +} + +static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int oob_required, int page) +{ + struct atmel_nand_host *host = chip->priv; + int eccsize = chip->ecc.size; + uint8_t *oob = chip->oob_poi; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint32_t stat; + unsigned long end_time; + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); + pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) + & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE); + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); + + chip->read_buf(mtd, buf, eccsize); + chip->read_buf(mtd, oob, mtd->oobsize); + + end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); + while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { + if (unlikely(time_after(jiffies, end_time))) { + dev_err(host->dev, "PMECC: Timeout to get error status.\n"); + return -EIO; + } + cpu_relax(); + } + + stat = pmecc_readl_relaxed(host->ecc, ISR); + if (stat != 0) + if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0) + return -EIO; + + return 0; +} + +static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, int oob_required) +{ + struct atmel_nand_host *host = chip->priv; + uint32_t *eccpos = chip->ecc.layout->eccpos; + int i, j; + unsigned long end_time; + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); + + pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) | + PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE); + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); + + chip->write_buf(mtd, (u8 *)buf, mtd->writesize); + + end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); + while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { + if (unlikely(time_after(jiffies, end_time))) { + dev_err(host->dev, "PMECC: Timeout to get ECC value.\n"); + return -EIO; + } + cpu_relax(); + } + + for (i = 0; i < host->pmecc_sector_number; i++) { + for (j = 0; j < host->pmecc_bytes_per_sector; j++) { + int pos; + + pos = i * host->pmecc_bytes_per_sector + j; + chip->oob_poi[eccpos[pos]] = + pmecc_readb_ecc_relaxed(host->ecc, i, j); + } + } + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} + +static void atmel_pmecc_core_init(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + uint32_t val = 0; + struct nand_ecclayout *ecc_layout; + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); + + switch (host->pmecc_corr_cap) { + case 2: + val = PMECC_CFG_BCH_ERR2; + break; + case 4: + val = PMECC_CFG_BCH_ERR4; + break; + case 8: + val = PMECC_CFG_BCH_ERR8; + break; + case 12: + val = PMECC_CFG_BCH_ERR12; + break; + case 24: + val = PMECC_CFG_BCH_ERR24; + break; + } + + if (host->pmecc_sector_size == 512) + val |= PMECC_CFG_SECTOR512; + else if (host->pmecc_sector_size == 1024) + val |= PMECC_CFG_SECTOR1024; + + switch (host->pmecc_sector_number) { + case 1: + val |= PMECC_CFG_PAGE_1SECTOR; + break; + case 2: + val |= PMECC_CFG_PAGE_2SECTORS; + break; + case 4: + val |= PMECC_CFG_PAGE_4SECTORS; + break; + case 8: + val |= PMECC_CFG_PAGE_8SECTORS; + break; + } + + val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE + | PMECC_CFG_AUTO_DISABLE); + pmecc_writel(host->ecc, CFG, val); + + ecc_layout = nand_chip->ecc.layout; + pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1); + pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]); + pmecc_writel(host->ecc, EADDR, + ecc_layout->eccpos[ecc_layout->eccbytes - 1]); + /* See datasheet about PMECC Clock Control Register */ + pmecc_writel(host->ecc, CLK, 2); + pmecc_writel(host->ecc, IDR, 0xff); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); +} + +static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, + struct atmel_nand_host *host) +{ + struct mtd_info *mtd = &host->mtd; + struct nand_chip *nand_chip = &host->nand_chip; + struct resource *regs, *regs_pmerr, *regs_rom; + int cap, sector_size, err_no; + + cap = host->pmecc_corr_cap; + sector_size = host->pmecc_sector_size; + dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n", + cap, sector_size); + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!regs) { + dev_warn(host->dev, + "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n"); + nand_chip->ecc.mode = NAND_ECC_SOFT; + return 0; + } + + host->ecc = ioremap(regs->start, resource_size(regs)); + if (host->ecc == NULL) { + dev_err(host->dev, "ioremap failed\n"); + err_no = -EIO; + goto err_pmecc_ioremap; + } + + regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2); + regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); + if (regs_pmerr && regs_rom) { + host->pmerrloc_base = ioremap(regs_pmerr->start, + resource_size(regs_pmerr)); + host->pmecc_rom_base = ioremap(regs_rom->start, + resource_size(regs_rom)); + } + + if (!host->pmerrloc_base || !host->pmecc_rom_base) { + dev_err(host->dev, + "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n"); + err_no = -EIO; + goto err_pmloc_ioremap; + } + + /* ECC is calculated for the whole page (1 step) */ + nand_chip->ecc.size = mtd->writesize; + + /* set ECC page size and oob layout */ + switch (mtd->writesize) { + case 2048: + host->pmecc_degree = PMECC_GF_DIMENSION_13; + host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; + host->pmecc_sector_number = mtd->writesize / sector_size; + host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes( + cap, sector_size); + host->pmecc_alpha_to = pmecc_get_alpha_to(host); + host->pmecc_index_of = host->pmecc_rom_base + + host->pmecc_lookup_table_offset; + + nand_chip->ecc.steps = 1; + nand_chip->ecc.strength = cap; + nand_chip->ecc.bytes = host->pmecc_bytes_per_sector * + host->pmecc_sector_number; + if (nand_chip->ecc.bytes > mtd->oobsize - 2) { + dev_err(host->dev, "No room for ECC bytes\n"); + err_no = -EINVAL; + goto err_no_ecc_room; + } + pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, + mtd->oobsize, + nand_chip->ecc.bytes); + nand_chip->ecc.layout = &atmel_pmecc_oobinfo; + break; + case 512: + case 1024: + case 4096: + /* TODO */ + dev_warn(host->dev, + "Unsupported page size for PMECC, use Software ECC\n"); + default: + /* page size not handled by HW ECC */ + /* switching back to soft ECC */ + nand_chip->ecc.mode = NAND_ECC_SOFT; + return 0; + } + + /* Allocate data for PMECC computation */ + err_no = pmecc_data_alloc(host); + if (err_no) { + dev_err(host->dev, + "Cannot allocate memory for PMECC computation!\n"); + goto err_pmecc_data_alloc; + } + + nand_chip->ecc.read_page = atmel_nand_pmecc_read_page; + nand_chip->ecc.write_page = atmel_nand_pmecc_write_page; + + atmel_pmecc_core_init(mtd); + + return 0; + +err_pmecc_data_alloc: +err_no_ecc_room: +err_pmloc_ioremap: + iounmap(host->ecc); + if (host->pmerrloc_base) + iounmap(host->pmerrloc_base); + if (host->pmecc_rom_base) + iounmap(host->pmecc_rom_base); +err_pmecc_ioremap: + return err_no; +} + /* * Calculate HW ECC * @@ -747,7 +1469,11 @@ static int __init atmel_nand_probe(struct platform_device *pdev) } if (nand_chip->ecc.mode == NAND_ECC_HW) { - res = atmel_hw_nand_init_params(pdev, host); + if (host->has_pmecc) + res = atmel_pmecc_nand_init_params(pdev, host); + else + res = atmel_hw_nand_init_params(pdev, host); + if (res != 0) goto err_hw_ecc; } @@ -766,8 +1492,16 @@ static int __init atmel_nand_probe(struct platform_device *pdev) return res; err_scan_tail: + if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) { + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); + pmecc_data_free(host); + } if (host->ecc) iounmap(host->ecc); + if (host->pmerrloc_base) + iounmap(host->pmerrloc_base); + if (host->pmecc_rom_base) + iounmap(host->pmecc_rom_base); err_hw_ecc: err_scan_ident: err_no_card: @@ -793,8 +1527,19 @@ static int __exit atmel_nand_remove(struct platform_device *pdev) atmel_nand_disable(host); + if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) { + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); + pmerrloc_writel(host->pmerrloc_base, ELDIS, + PMERRLOC_DISABLE); + pmecc_data_free(host); + } + if (host->ecc) iounmap(host->ecc); + if (host->pmecc_rom_base) + iounmap(host->pmecc_rom_base); + if (host->pmerrloc_base) + iounmap(host->pmerrloc_base); if (host->dma_chan) dma_release_channel(host->dma_chan); diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index 578c776e1356..8a1e9a686759 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -3,7 +3,7 @@ * Based on AT91SAM9260 datasheet revision B. * * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2007 - 2012 Atmel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -36,4 +36,116 @@ #define ATMEL_ECC_NPR 0x10 /* NParity register */ #define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */ +/* PMECC Register Definitions */ +#define ATMEL_PMECC_CFG 0x000 /* Configuration Register */ +#define PMECC_CFG_BCH_ERR2 (0 << 0) +#define PMECC_CFG_BCH_ERR4 (1 << 0) +#define PMECC_CFG_BCH_ERR8 (2 << 0) +#define PMECC_CFG_BCH_ERR12 (3 << 0) +#define PMECC_CFG_BCH_ERR24 (4 << 0) + +#define PMECC_CFG_SECTOR512 (0 << 4) +#define PMECC_CFG_SECTOR1024 (1 << 4) + +#define PMECC_CFG_PAGE_1SECTOR (0 << 8) +#define PMECC_CFG_PAGE_2SECTORS (1 << 8) +#define PMECC_CFG_PAGE_4SECTORS (2 << 8) +#define PMECC_CFG_PAGE_8SECTORS (3 << 8) + +#define PMECC_CFG_READ_OP (0 << 12) +#define PMECC_CFG_WRITE_OP (1 << 12) + +#define PMECC_CFG_SPARE_ENABLE (1 << 16) +#define PMECC_CFG_SPARE_DISABLE (0 << 16) + +#define PMECC_CFG_AUTO_ENABLE (1 << 20) +#define PMECC_CFG_AUTO_DISABLE (0 << 20) + +#define ATMEL_PMECC_SAREA 0x004 /* Spare area size */ +#define ATMEL_PMECC_SADDR 0x008 /* PMECC starting address */ +#define ATMEL_PMECC_EADDR 0x00c /* PMECC ending address */ +#define ATMEL_PMECC_CLK 0x010 /* PMECC clock control */ +#define PMECC_CLK_133MHZ (2 << 0) + +#define ATMEL_PMECC_CTRL 0x014 /* PMECC control register */ +#define PMECC_CTRL_RST (1 << 0) +#define PMECC_CTRL_DATA (1 << 1) +#define PMECC_CTRL_USER (1 << 2) +#define PMECC_CTRL_ENABLE (1 << 4) +#define PMECC_CTRL_DISABLE (1 << 5) + +#define ATMEL_PMECC_SR 0x018 /* PMECC status register */ +#define PMECC_SR_BUSY (1 << 0) +#define PMECC_SR_ENABLE (1 << 4) + +#define ATMEL_PMECC_IER 0x01c /* PMECC interrupt enable */ +#define PMECC_IER_ENABLE (1 << 0) +#define ATMEL_PMECC_IDR 0x020 /* PMECC interrupt disable */ +#define PMECC_IER_DISABLE (1 << 0) +#define ATMEL_PMECC_IMR 0x024 /* PMECC interrupt mask */ +#define PMECC_IER_MASK (1 << 0) +#define ATMEL_PMECC_ISR 0x028 /* PMECC interrupt status */ +#define ATMEL_PMECC_ECCx 0x040 /* PMECC ECC x */ +#define ATMEL_PMECC_REMx 0x240 /* PMECC REM x */ + +/* PMERRLOC Register Definitions */ +#define ATMEL_PMERRLOC_ELCFG 0x000 /* Error location config */ +#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0) +#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0) +#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16) + +#define ATMEL_PMERRLOC_ELPRIM 0x004 /* Error location primitive */ +#define ATMEL_PMERRLOC_ELEN 0x008 /* Error location enable */ +#define ATMEL_PMERRLOC_ELDIS 0x00c /* Error location disable */ +#define PMERRLOC_DISABLE (1 << 0) + +#define ATMEL_PMERRLOC_ELSR 0x010 /* Error location status */ +#define PMERRLOC_ELSR_BUSY (1 << 0) +#define ATMEL_PMERRLOC_ELIER 0x014 /* Error location int enable */ +#define ATMEL_PMERRLOC_ELIDR 0x018 /* Error location int disable */ +#define ATMEL_PMERRLOC_ELIMR 0x01c /* Error location int mask */ +#define ATMEL_PMERRLOC_ELISR 0x020 /* Error location int status */ +#define PMERRLOC_ERR_NUM_MASK (0x1f << 8) +#define PMERRLOC_CALC_DONE (1 << 0) +#define ATMEL_PMERRLOC_SIGMAx 0x028 /* Error location SIGMA x */ +#define ATMEL_PMERRLOC_ELx 0x08c /* Error location x */ + +/* Register access macros for PMECC */ +#define pmecc_readl_relaxed(addr, reg) \ + readl_relaxed((addr) + ATMEL_PMECC_##reg) + +#define pmecc_writel(addr, reg, value) \ + writel((value), (addr) + ATMEL_PMECC_##reg) + +#define pmecc_readb_ecc_relaxed(addr, sector, n) \ + readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n)) + +#define pmecc_readl_rem_relaxed(addr, sector, n) \ + readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4)) + +#define pmerrloc_readl_relaxed(addr, reg) \ + readl_relaxed((addr) + ATMEL_PMERRLOC_##reg) + +#define pmerrloc_writel(addr, reg, value) \ + writel((value), (addr) + ATMEL_PMERRLOC_##reg) + +#define pmerrloc_writel_sigma_relaxed(addr, n, value) \ + writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4)) + +#define pmerrloc_readl_sigma_relaxed(addr, n) \ + readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4)) + +#define pmerrloc_readl_el_relaxed(addr, n) \ + readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4)) + +/* Galois field dimension */ +#define PMECC_GF_DIMENSION_13 13 +#define PMECC_GF_DIMENSION_14 14 + +#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000 +#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000 + +/* Time out value for reading PMECC status register */ +#define PMECC_MAX_TIMEOUT_MS 100 + #endif -- cgit v1.2.3 From df63fe7657d75424f58b41ac079ed8bc4b4676fb Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Wed, 27 Jun 2012 17:51:13 +0200 Subject: mtd: lpc32xx_slc: Make wp gpio optional This patch supports missing wp gpio. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge Signed-off-by: Artem Bityutskiy --- drivers/mtd/nand/lpc32xx_slc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 1d837b92ac79..1577a9b0d0c2 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -192,7 +192,7 @@ struct lpc32xx_nand_cfg_slc { uint32_t rhold; uint32_t rsetup; bool use_bbt; - unsigned wp_gpio; + int wp_gpio; struct mtd_partition *parts; unsigned num_parts; }; @@ -295,7 +295,8 @@ static int lpc32xx_nand_device_ready(struct mtd_info *mtd) */ static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) { - gpio_set_value(host->ncfg->wp_gpio, 0); + if (gpio_is_valid(host->ncfg->wp_gpio)) + gpio_set_value(host->ncfg->wp_gpio, 0); } /* @@ -303,7 +304,8 @@ static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) */ static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) { - gpio_set_value(host->ncfg->wp_gpio, 1); + if (gpio_is_valid(host->ncfg->wp_gpio)) + gpio_set_value(host->ncfg->wp_gpio, 1); } /* @@ -819,7 +821,8 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Missing platform data\n"); return -ENOENT; } - if (gpio_request(host->ncfg->wp_gpio, "NAND WP")) { + if (gpio_is_valid(host->ncfg->wp_gpio) && + gpio_request(host->ncfg->wp_gpio, "NAND WP")) { dev_err(&pdev->dev, "GPIO not available\n"); return -EBUSY; } -- cgit v1.2.3 From 21535ab39a74b5ec074e2d10b132e866472e86f9 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 27 Jun 2012 17:51:14 +0200 Subject: mtd: lpc32xx_slc: Use of_get_named_gpio() This patch makes the lpc32xx_slc driver use of_get_named_gpio() instead of of_get_named_gpio_flags() whose flags are discarded anyway. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_slc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 1577a9b0d0c2..116665015269 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -770,7 +770,7 @@ static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) } pdata->use_bbt = of_get_nand_on_flash_bbt(np); - pdata->wp_gpio = of_get_named_gpio_flags(np, "gpios", 0, NULL); + pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0); return pdata; } -- cgit v1.2.3 From d5842ab730d368ae2e8925dc00aec0ca132b72ab Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 27 Jun 2012 17:51:15 +0200 Subject: mtd: lpc32xx_slc: Make probe() return -EPROBE_DEFER if necessary Via of_get_named_gpio(), wp_gpio can become -EPROBE_DEFER which now makes probe() return -EPROBE_DEFER as well to wait until the gpio controller is probed before trying to probe lpc32xx_slc again. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_slc.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 116665015269..1719387dd008 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -821,6 +821,8 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Missing platform data\n"); return -ENOENT; } + if (host->ncfg->wp_gpio == -EPROBE_DEFER) + return -EPROBE_DEFER; if (gpio_is_valid(host->ncfg->wp_gpio) && gpio_request(host->ncfg->wp_gpio, "NAND WP")) { dev_err(&pdev->dev, "GPIO not available\n"); -- cgit v1.2.3 From 70f7cb78ec534301d13af1786b86f13fd96147eb Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sat, 30 Jun 2012 18:50:38 +0200 Subject: mtd: add LPC32xx MLC NAND driver This patch adds a driver for the MLC NAND controller of the LPC32xx SoC. [dwmw2: 21st century pedantry] Signed-off-by: Roland Stigge Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 11 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_mlc.c | 936 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 948 insertions(+) create mode 100644 drivers/mtd/nand/lpc32xx_mlc.c (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index de6997832dad..adee4681f98f 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -425,6 +425,17 @@ config MTD_NAND_SLC_LPC32XX Please check the actual NAND chip connected and its support by the SLC NAND controller. +config MTD_NAND_MLC_LPC32XX + tristate "NXP LPC32xx MLC Controller" + depends on ARCH_LPC32XX + help + Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND + controller. This is the default for the WORK92105 controller + board. + + Please check the actual NAND chip connected and its support + by the MLC NAND controller. + config MTD_NAND_CM_X270 tristate "Support for NAND Flash on CM-X270 modules" depends on MACH_ARMCORE diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index d29a893608e7..ddee81811b4a 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_MTD_NAND_SLC_LPC32XX) += lpc32xx_slc.o +obj-$(CONFIG_MTD_NAND_MLC_LPC32XX) += lpc32xx_mlc.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o diff --git a/drivers/mtd/nand/lpc32xx_mlc.c b/drivers/mtd/nand/lpc32xx_mlc.c new file mode 100644 index 000000000000..260b2c242491 --- /dev/null +++ b/drivers/mtd/nand/lpc32xx_mlc.c @@ -0,0 +1,936 @@ +/* + * Driver for NAND MLC Controller in LPC32xx + * + * Author: Roland Stigge + * + * Copyright © 2011 WORK Microwave GmbH + * Copyright © 2011, 2012 Roland Stigge + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * NAND Flash Controller Operation: + * - Read: Auto Decode + * - Write: Auto Encode + * - Tested Page Sizes: 2048, 4096 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "lpc32xx_mlc" + +/********************************************************************** +* MLC NAND controller register offsets +**********************************************************************/ + +#define MLC_BUFF(x) (x + 0x00000) +#define MLC_DATA(x) (x + 0x08000) +#define MLC_CMD(x) (x + 0x10000) +#define MLC_ADDR(x) (x + 0x10004) +#define MLC_ECC_ENC_REG(x) (x + 0x10008) +#define MLC_ECC_DEC_REG(x) (x + 0x1000C) +#define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010) +#define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014) +#define MLC_RPR(x) (x + 0x10018) +#define MLC_WPR(x) (x + 0x1001C) +#define MLC_RUBP(x) (x + 0x10020) +#define MLC_ROBP(x) (x + 0x10024) +#define MLC_SW_WP_ADD_LOW(x) (x + 0x10028) +#define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C) +#define MLC_ICR(x) (x + 0x10030) +#define MLC_TIME_REG(x) (x + 0x10034) +#define MLC_IRQ_MR(x) (x + 0x10038) +#define MLC_IRQ_SR(x) (x + 0x1003C) +#define MLC_LOCK_PR(x) (x + 0x10044) +#define MLC_ISR(x) (x + 0x10048) +#define MLC_CEH(x) (x + 0x1004C) + +/********************************************************************** +* MLC_CMD bit definitions +**********************************************************************/ +#define MLCCMD_RESET 0xFF + +/********************************************************************** +* MLC_ICR bit definitions +**********************************************************************/ +#define MLCICR_WPROT (1 << 3) +#define MLCICR_LARGEBLOCK (1 << 2) +#define MLCICR_LONGADDR (1 << 1) +#define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */ + +/********************************************************************** +* MLC_TIME_REG bit definitions +**********************************************************************/ +#define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24) +#define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19) +#define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16) +#define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12) +#define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8) +#define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4) +#define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0) + +/********************************************************************** +* MLC_IRQ_MR and MLC_IRQ_SR bit definitions +**********************************************************************/ +#define MLCIRQ_NAND_READY (1 << 5) +#define MLCIRQ_CONTROLLER_READY (1 << 4) +#define MLCIRQ_DECODE_FAILURE (1 << 3) +#define MLCIRQ_DECODE_ERROR (1 << 2) +#define MLCIRQ_ECC_READY (1 << 1) +#define MLCIRQ_WRPROT_FAULT (1 << 0) + +/********************************************************************** +* MLC_LOCK_PR bit definitions +**********************************************************************/ +#define MLCLOCKPR_MAGIC 0xA25E + +/********************************************************************** +* MLC_ISR bit definitions +**********************************************************************/ +#define MLCISR_DECODER_FAILURE (1 << 6) +#define MLCISR_ERRORS ((1 << 4) | (1 << 5)) +#define MLCISR_ERRORS_DETECTED (1 << 3) +#define MLCISR_ECC_READY (1 << 2) +#define MLCISR_CONTROLLER_READY (1 << 1) +#define MLCISR_NAND_READY (1 << 0) + +/********************************************************************** +* MLC_CEH bit definitions +**********************************************************************/ +#define MLCCEH_NORMAL (1 << 0) + +struct lpc32xx_nand_cfg_mlc { + uint32_t tcea_delay; + uint32_t busy_delay; + uint32_t nand_ta; + uint32_t rd_high; + uint32_t rd_low; + uint32_t wr_high; + uint32_t wr_low; + int wp_gpio; + struct mtd_partition *parts; + unsigned num_parts; +}; + +static struct nand_ecclayout lpc32xx_nand_oob = { + .eccbytes = 40, + .eccpos = { 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, + .oobfree = { + { .offset = 0, + .length = 6, }, + { .offset = 16, + .length = 6, }, + { .offset = 32, + .length = 6, }, + { .offset = 48, + .length = 6, }, + }, +}; + +static struct nand_bbt_descr lpc32xx_nand_bbt = { + .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | + NAND_BBT_WRITE, + .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = { + .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | + NAND_BBT_WRITE, + .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 }, +}; + +struct lpc32xx_nand_host { + struct nand_chip nand_chip; + struct clk *clk; + struct mtd_info mtd; + void __iomem *io_base; + int irq; + struct lpc32xx_nand_cfg_mlc *ncfg; + struct completion comp_nand; + struct completion comp_controller; + uint32_t llptr; + /* + * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer + */ + dma_addr_t oob_buf_phy; + /* + * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer + */ + uint8_t *oob_buf; + /* Physical address of DMA base address */ + dma_addr_t io_base_phy; + + struct completion comp_dma; + struct dma_chan *dma_chan; + struct dma_slave_config dma_slave_config; + struct scatterlist sgl; + uint8_t *dma_buf; + uint8_t *dummy_buf; + int mlcsubpages; /* number of 512bytes-subpages */ +}; + +/* + * Activate/Deactivate DMA Operation: + * + * Using the PL080 DMA Controller for transferring the 512 byte subpages + * instead of doing readl() / writel() in a loop slows it down significantly. + * Measurements via getnstimeofday() upon 512 byte subpage reads reveal: + * + * - readl() of 128 x 32 bits in a loop: ~20us + * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us + * - DMA read of 512 bytes (32 bit, no bursts): ~100us + * + * This applies to the transfer itself. In the DMA case: only the + * wait_for_completion() (DMA setup _not_ included). + * + * Note that the 512 bytes subpage transfer is done directly from/to a + * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a + * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND + * controller transferring data between its internal buffer to/from the NAND + * chip.) + * + * Therefore, using the PL080 DMA is disabled by default, for now. + * + */ +static int use_dma; + +static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) +{ + uint32_t clkrate, tmp; + + /* Reset MLC controller */ + writel(MLCCMD_RESET, MLC_CMD(host->io_base)); + udelay(1000); + + /* Get base clock for MLC block */ + clkrate = clk_get_rate(host->clk); + if (clkrate == 0) + clkrate = 104000000; + + /* Unlock MLC_ICR + * (among others, will be locked again automatically) */ + writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); + + /* Configure MLC Controller: Large Block, 5 Byte Address */ + tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR; + writel(tmp, MLC_ICR(host->io_base)); + + /* Unlock MLC_TIME_REG + * (among others, will be locked again automatically) */ + writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); + + /* Compute clock setup values, see LPC and NAND manual */ + tmp = 0; + tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1); + tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1); + tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1); + tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1); + tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low); + tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1); + tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low); + writel(tmp, MLC_TIME_REG(host->io_base)); + + /* Enable IRQ for CONTROLLER_READY and NAND_READY */ + writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY, + MLC_IRQ_MR(host->io_base)); + + /* Normal nCE operation: nCE controlled by controller */ + writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); +} + +/* + * Hardware specific access to control lines + */ +static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *nand_chip = mtd->priv; + struct lpc32xx_nand_host *host = nand_chip->priv; + + if (cmd != NAND_CMD_NONE) { + if (ctrl & NAND_CLE) + writel(cmd, MLC_CMD(host->io_base)); + else + writel(cmd, MLC_ADDR(host->io_base)); + } +} + +/* + * Read Device Ready (NAND device _and_ controller ready) + */ +static int lpc32xx_nand_device_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct lpc32xx_nand_host *host = nand_chip->priv; + + if ((readb(MLC_ISR(host->io_base)) & + (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) == + (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) + return 1; + + return 0; +} + +static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host) +{ + uint8_t sr; + + /* Clear interrupt flag by reading status */ + sr = readb(MLC_IRQ_SR(host->io_base)); + if (sr & MLCIRQ_NAND_READY) + complete(&host->comp_nand); + if (sr & MLCIRQ_CONTROLLER_READY) + complete(&host->comp_controller); + + return IRQ_HANDLED; +} + +static int lpc32xx_waitfunc_nand(struct mtd_info *mtd, struct nand_chip *chip) +{ + struct lpc32xx_nand_host *host = chip->priv; + + if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY) + goto exit; + + wait_for_completion(&host->comp_nand); + + while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) { + /* Seems to be delayed sometimes by controller */ + dev_dbg(&mtd->dev, "Warning: NAND not ready.\n"); + cpu_relax(); + } + +exit: + return NAND_STATUS_READY; +} + +static int lpc32xx_waitfunc_controller(struct mtd_info *mtd, + struct nand_chip *chip) +{ + struct lpc32xx_nand_host *host = chip->priv; + + if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY) + goto exit; + + wait_for_completion(&host->comp_controller); + + while (!(readb(MLC_ISR(host->io_base)) & + MLCISR_CONTROLLER_READY)) { + dev_dbg(&mtd->dev, "Warning: Controller not ready.\n"); + cpu_relax(); + } + +exit: + return NAND_STATUS_READY; +} + +static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) +{ + lpc32xx_waitfunc_nand(mtd, chip); + lpc32xx_waitfunc_controller(mtd, chip); + + return NAND_STATUS_READY; +} + +/* + * Enable NAND write protect + */ +static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) +{ + if (gpio_is_valid(host->ncfg->wp_gpio)) + gpio_set_value(host->ncfg->wp_gpio, 0); +} + +/* + * Disable NAND write protect + */ +static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) +{ + if (gpio_is_valid(host->ncfg->wp_gpio)) + gpio_set_value(host->ncfg->wp_gpio, 1); +} + +static void lpc32xx_dma_complete_func(void *completion) +{ + complete(completion); +} + +static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len, + enum dma_transfer_direction dir) +{ + struct nand_chip *chip = mtd->priv; + struct lpc32xx_nand_host *host = chip->priv; + struct dma_async_tx_descriptor *desc; + int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; + int res; + + sg_init_one(&host->sgl, mem, len); + + res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, + DMA_BIDIRECTIONAL); + if (res != 1) { + dev_err(mtd->dev.parent, "Failed to map sg list\n"); + return -ENXIO; + } + desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, + flags); + if (!desc) { + dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); + goto out1; + } + + init_completion(&host->comp_dma); + desc->callback = lpc32xx_dma_complete_func; + desc->callback_param = &host->comp_dma; + + dmaengine_submit(desc); + dma_async_issue_pending(host->dma_chan); + + wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000)); + + dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, + DMA_BIDIRECTIONAL); + return 0; +out1: + dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, + DMA_BIDIRECTIONAL); + return -ENXIO; +} + +static int lpc32xx_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + struct lpc32xx_nand_host *host = chip->priv; + int i, j; + uint8_t *oobbuf = chip->oob_poi; + uint32_t mlc_isr; + int res; + uint8_t *dma_buf; + bool dma_mapped; + + if ((void *)buf <= high_memory) { + dma_buf = buf; + dma_mapped = true; + } else { + dma_buf = host->dma_buf; + dma_mapped = false; + } + + /* Writing Command and Address */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + /* For all sub-pages */ + for (i = 0; i < host->mlcsubpages; i++) { + /* Start Auto Decode Command */ + writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base)); + + /* Wait for Controller Ready */ + lpc32xx_waitfunc_controller(mtd, chip); + + /* Check ECC Error status */ + mlc_isr = readl(MLC_ISR(host->io_base)); + if (mlc_isr & MLCISR_DECODER_FAILURE) { + mtd->ecc_stats.failed++; + dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__); + } else if (mlc_isr & MLCISR_ERRORS_DETECTED) { + mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1; + } + + /* Read 512 + 16 Bytes */ + if (use_dma) { + res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512, + DMA_DEV_TO_MEM); + if (res) + return res; + } else { + for (j = 0; j < (512 >> 2); j++) { + *((uint32_t *)(buf)) = + readl(MLC_BUFF(host->io_base)); + buf += 4; + } + } + for (j = 0; j < (16 >> 2); j++) { + *((uint32_t *)(oobbuf)) = + readl(MLC_BUFF(host->io_base)); + oobbuf += 4; + } + } + + if (use_dma && !dma_mapped) + memcpy(buf, dma_buf, mtd->writesize); + + return 0; +} + +static int lpc32xx_write_page_lowlevel(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + struct lpc32xx_nand_host *host = chip->priv; + const uint8_t *oobbuf = chip->oob_poi; + uint8_t *dma_buf = (uint8_t *)buf; + int res; + int i, j; + + if (use_dma && (void *)buf >= high_memory) { + dma_buf = host->dma_buf; + memcpy(dma_buf, buf, mtd->writesize); + } + + for (i = 0; i < host->mlcsubpages; i++) { + /* Start Encode */ + writeb(0x00, MLC_ECC_ENC_REG(host->io_base)); + + /* Write 512 + 6 Bytes to Buffer */ + if (use_dma) { + res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512, + DMA_MEM_TO_DEV); + if (res) + return res; + } else { + for (j = 0; j < (512 >> 2); j++) { + writel(*((uint32_t *)(buf)), + MLC_BUFF(host->io_base)); + buf += 4; + } + } + writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base)); + oobbuf += 4; + writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base)); + oobbuf += 12; + + /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ + writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base)); + + /* Wait for Controller Ready */ + lpc32xx_waitfunc_controller(mtd, chip); + } + return 0; +} + +static int lpc32xx_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required, int page, + int cached, int raw) +{ + int res; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + res = lpc32xx_write_page_lowlevel(mtd, chip, buf, oob_required); + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + lpc32xx_waitfunc(mtd, chip); + + return res; +} + +static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct lpc32xx_nand_host *host = chip->priv; + + /* Read whole page - necessary with MLC controller! */ + lpc32xx_read_page(mtd, chip, host->dummy_buf, 1, page); + + return 0; +} + +static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ + return 0; +} + +/* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */ +static void lpc32xx_ecc_enable(struct mtd_info *mtd, int mode) +{ + /* Always enabled! */ +} + +static bool lpc32xx_dma_filter(struct dma_chan *chan, void *param) +{ + struct pl08x_dma_chan *ch = + container_of(chan, struct pl08x_dma_chan, chan); + + /* In LPC32xx's PL080 DMA wiring, the MLC NAND DMA signal is #12 */ + if (ch->cd->min_signal == 12) + return true; + return false; +} + +static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) +{ + struct mtd_info *mtd = &host->mtd; + dma_cap_mask_t mask; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + host->dma_chan = dma_request_channel(mask, lpc32xx_dma_filter, NULL); + if (!host->dma_chan) { + dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); + return -EBUSY; + } + + /* + * Set direction to a sensible value even if the dmaengine driver + * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x + * driver criticizes it as "alien transfer direction". + */ + host->dma_slave_config.direction = DMA_DEV_TO_MEM; + host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + host->dma_slave_config.src_maxburst = 128; + host->dma_slave_config.dst_maxburst = 128; + /* DMA controller does flow control: */ + host->dma_slave_config.device_fc = false; + host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy); + host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy); + if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { + dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); + goto out1; + } + + return 0; +out1: + dma_release_channel(host->dma_chan); + return -ENXIO; +} + +#ifdef CONFIG_OF +static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) +{ + struct lpc32xx_nand_cfg_mlc *pdata; + struct device_node *np = dev->of_node; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(dev, "could not allocate memory for platform data\n"); + return NULL; + } + + of_property_read_u32(np, "nxp,tcea-delay", &pdata->tcea_delay); + of_property_read_u32(np, "nxp,busy-delay", &pdata->busy_delay); + of_property_read_u32(np, "nxp,nand-ta", &pdata->nand_ta); + of_property_read_u32(np, "nxp,rd-high", &pdata->rd_high); + of_property_read_u32(np, "nxp,rd-low", &pdata->rd_low); + of_property_read_u32(np, "nxp,wr-high", &pdata->wr_high); + of_property_read_u32(np, "nxp,wr-low", &pdata->wr_low); + + if (!pdata->tcea_delay || !pdata->busy_delay || !pdata->nand_ta || + !pdata->rd_high || !pdata->rd_low || !pdata->wr_high || + !pdata->wr_low) { + dev_err(dev, "chip parameters not specified correctly\n"); + return NULL; + } + + pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0); + + return pdata; +} +#else +static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) +{ + return NULL; +} +#endif + +/* + * Probe for NAND controller + */ +static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) +{ + struct lpc32xx_nand_host *host; + struct mtd_info *mtd; + struct nand_chip *nand_chip; + struct resource *rc; + int res; + struct mtd_part_parser_data ppdata = {}; + + /* Allocate memory for the device structure (and zero it) */ + host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); + if (!host) { + dev_err(&pdev->dev, "failed to allocate device structure.\n"); + return -ENOMEM; + } + + rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (rc == NULL) { + dev_err(&pdev->dev, "No memory resource found for device!\r\n"); + return -ENXIO; + } + + host->io_base = devm_request_and_ioremap(&pdev->dev, rc); + if (host->io_base == NULL) { + dev_err(&pdev->dev, "ioremap failed\n"); + return -EIO; + } + host->io_base_phy = rc->start; + + mtd = &host->mtd; + nand_chip = &host->nand_chip; + if (pdev->dev.of_node) + host->ncfg = lpc32xx_parse_dt(&pdev->dev); + else + host->ncfg = pdev->dev.platform_data; + if (!host->ncfg) { + dev_err(&pdev->dev, "Missing platform data\n"); + return -ENOENT; + } + if (host->ncfg->wp_gpio == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (gpio_is_valid(host->ncfg->wp_gpio) && + gpio_request(host->ncfg->wp_gpio, "NAND WP")) { + dev_err(&pdev->dev, "GPIO not available\n"); + return -EBUSY; + } + lpc32xx_wp_disable(host); + + nand_chip->priv = host; /* link the private data structures */ + mtd->priv = nand_chip; + mtd->owner = THIS_MODULE; + mtd->dev.parent = &pdev->dev; + + /* Get NAND clock */ + host->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(host->clk)) { + dev_err(&pdev->dev, "Clock initialization failure\n"); + res = -ENOENT; + goto err_exit1; + } + clk_enable(host->clk); + + nand_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; + nand_chip->dev_ready = lpc32xx_nand_device_ready; + nand_chip->chip_delay = 25; /* us */ + nand_chip->IO_ADDR_R = MLC_DATA(host->io_base); + nand_chip->IO_ADDR_W = MLC_DATA(host->io_base); + + /* Init NAND controller */ + lpc32xx_nand_setup(host); + + platform_set_drvdata(pdev, host); + + /* Initialize function pointers */ + nand_chip->ecc.hwctl = lpc32xx_ecc_enable; + nand_chip->ecc.read_page_raw = lpc32xx_read_page; + nand_chip->ecc.read_page = lpc32xx_read_page; + nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; + nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel; + nand_chip->ecc.write_oob = lpc32xx_write_oob; + nand_chip->ecc.read_oob = lpc32xx_read_oob; + nand_chip->ecc.strength = 4; + nand_chip->write_page = lpc32xx_write_page; + nand_chip->waitfunc = lpc32xx_waitfunc; + + nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; + nand_chip->bbt_td = &lpc32xx_nand_bbt; + nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror; + + /* bitflip_threshold's default is defined as ecc_strength anyway. + * Unfortunately, it is set only later at add_mtd_device(). Meanwhile + * being 0, it causes bad block table scanning errors in + * nand_scan_tail(), so preparing it here. */ + mtd->bitflip_threshold = nand_chip->ecc.strength; + + if (use_dma) { + res = lpc32xx_dma_setup(host); + if (res) { + res = -EIO; + goto err_exit2; + } + } + + /* + * Scan to find existance of the device and + * Get the type of NAND device SMALL block or LARGE block + */ + if (nand_scan_ident(mtd, 1, NULL)) { + res = -ENXIO; + goto err_exit3; + } + + host->dma_buf = devm_kzalloc(&pdev->dev, mtd->writesize, GFP_KERNEL); + if (!host->dma_buf) { + dev_err(&pdev->dev, "Error allocating dma_buf memory\n"); + res = -ENOMEM; + goto err_exit3; + } + + host->dummy_buf = devm_kzalloc(&pdev->dev, mtd->writesize, GFP_KERNEL); + if (!host->dummy_buf) { + dev_err(&pdev->dev, "Error allocating dummy_buf memory\n"); + res = -ENOMEM; + goto err_exit3; + } + + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.size = mtd->writesize; + nand_chip->ecc.layout = &lpc32xx_nand_oob; + host->mlcsubpages = mtd->writesize / 512; + + /* initially clear interrupt status */ + readb(MLC_IRQ_SR(host->io_base)); + + init_completion(&host->comp_nand); + init_completion(&host->comp_controller); + + host->irq = platform_get_irq(pdev, 0); + if ((host->irq < 0) || (host->irq >= NR_IRQS)) { + dev_err(&pdev->dev, "failed to get platform irq\n"); + res = -EINVAL; + goto err_exit3; + } + + if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq, + IRQF_TRIGGER_HIGH, DRV_NAME, host)) { + dev_err(&pdev->dev, "Error requesting NAND IRQ\n"); + res = -ENXIO; + goto err_exit3; + } + + /* + * Fills out all the uninitialized function pointers with the defaults + * And scans for a bad block table if appropriate. + */ + if (nand_scan_tail(mtd)) { + res = -ENXIO; + goto err_exit4; + } + + mtd->name = DRV_NAME; + + ppdata.of_node = pdev->dev.of_node; + res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts, + host->ncfg->num_parts); + if (!res) + return res; + + nand_release(mtd); + +err_exit4: + free_irq(host->irq, host); +err_exit3: + if (use_dma) + dma_release_channel(host->dma_chan); +err_exit2: + clk_disable(host->clk); + clk_put(host->clk); + platform_set_drvdata(pdev, NULL); +err_exit1: + lpc32xx_wp_enable(host); + gpio_free(host->ncfg->wp_gpio); + + return res; +} + +/* + * Remove NAND device + */ +static int __devexit lpc32xx_nand_remove(struct platform_device *pdev) +{ + struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); + struct mtd_info *mtd = &host->mtd; + + nand_release(mtd); + free_irq(host->irq, host); + if (use_dma) + dma_release_channel(host->dma_chan); + + clk_disable(host->clk); + clk_put(host->clk); + platform_set_drvdata(pdev, NULL); + + lpc32xx_wp_enable(host); + gpio_free(host->ncfg->wp_gpio); + + return 0; +} + +#ifdef CONFIG_PM +static int lpc32xx_nand_resume(struct platform_device *pdev) +{ + struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); + + /* Re-enable NAND clock */ + clk_enable(host->clk); + + /* Fresh init of NAND controller */ + lpc32xx_nand_setup(host); + + /* Disable write protect */ + lpc32xx_wp_disable(host); + + return 0; +} + +static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) +{ + struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); + + /* Enable write protect for safety */ + lpc32xx_wp_enable(host); + + /* Disable clock */ + clk_disable(host->clk); + return 0; +} + +#else +#define lpc32xx_nand_resume NULL +#define lpc32xx_nand_suspend NULL +#endif + +#if defined(CONFIG_OF) +static const struct of_device_id lpc32xx_nand_match[] = { + { .compatible = "nxp,lpc3220-mlc" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); +#endif + +static struct platform_driver lpc32xx_nand_driver = { + .probe = lpc32xx_nand_probe, + .remove = __devexit_p(lpc32xx_nand_remove), + .resume = lpc32xx_nand_resume, + .suspend = lpc32xx_nand_suspend, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(lpc32xx_nand_match), + }, +}; + +module_platform_driver(lpc32xx_nand_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Roland Stigge "); +MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller"); -- cgit v1.2.3 From 314a15664e028e6bcafc03495cc492645d9df4df Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 12 Jul 2012 14:22:56 +0200 Subject: mtd: lpc32xx_slc: Adjust to pl08x DMA interface changes This patch adjusts the LPC32xx SLC NAND driver to the new pl08x DMA interface, fixing the compile error resulting from changed pl08x structures. Signed-off-by: Roland Stigge Acked-By: Alexandre Pereira da Silva Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_slc.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 1719387dd008..c8c1d06b35ab 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -714,17 +714,6 @@ static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd, return 0; } -static bool lpc32xx_dma_filter(struct dma_chan *chan, void *param) -{ - struct pl08x_dma_chan *ch = - container_of(chan, struct pl08x_dma_chan, chan); - - /* In LPC32xx's PL080 DMA wiring, the SLC NAND DMA signal is #1 */ - if (ch->cd->min_signal == 1) - return true; - return false; -} - static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) { struct mtd_info *mtd = &host->mtd; @@ -732,7 +721,7 @@ static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - host->dma_chan = dma_request_channel(mask, lpc32xx_dma_filter, NULL); + host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-slc"); if (!host->dma_chan) { dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); return -EBUSY; -- cgit v1.2.3 From 79f9df7c0027742ae7c913367b6d88dec242fa63 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 12 Jul 2012 14:22:57 +0200 Subject: mtd: lpc32xx_mlc: Adjust to pl08x DMA interface changes This patch adjusts the LPC32xx MLC NAND driver to the new pl08x DMA interface, fixing the compile error resulting from changed pl08x structures. Signed-off-by: Roland Stigge Acked-By: Alexandre Pereira da Silva Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_mlc.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_mlc.c b/drivers/mtd/nand/lpc32xx_mlc.c index 260b2c242491..1cf35932a4d5 100644 --- a/drivers/mtd/nand/lpc32xx_mlc.c +++ b/drivers/mtd/nand/lpc32xx_mlc.c @@ -576,17 +576,6 @@ static void lpc32xx_ecc_enable(struct mtd_info *mtd, int mode) /* Always enabled! */ } -static bool lpc32xx_dma_filter(struct dma_chan *chan, void *param) -{ - struct pl08x_dma_chan *ch = - container_of(chan, struct pl08x_dma_chan, chan); - - /* In LPC32xx's PL080 DMA wiring, the MLC NAND DMA signal is #12 */ - if (ch->cd->min_signal == 12) - return true; - return false; -} - static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) { struct mtd_info *mtd = &host->mtd; @@ -594,7 +583,7 @@ static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - host->dma_chan = dma_request_channel(mask, lpc32xx_dma_filter, NULL); + host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-mlc"); if (!host->dma_chan) { dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); return -EBUSY; -- cgit v1.2.3 From 4d363b5518dd6298b39653919828eb7d9061488c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 2 Jul 2012 19:00:19 -0300 Subject: mtd: mxc_nand: Select the driver via ARCH_MXC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With device tree support in place, we should not use IMX_HAVE_PLATFORM_MXC_NAND as a dependency for selecting the mxc_nand driver. Use ARCH_MXC symbol instead, so that the driver can be even selected when a single device-tree machine is selected. Signed-off-by: Fabio Estevam Acked-by: Uwe Kleine-König Acked-by: Sascha Hauer Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index adee4681f98f..f4e81a7742b8 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -532,7 +532,7 @@ config MTD_NAND_MPC5121_NFC config MTD_NAND_MXC tristate "MXC NAND support" - depends on IMX_HAVE_PLATFORM_MXC_NAND + depends on ARCH_MXC help This enables the driver for the NAND flash controller on the MXC processors. -- cgit v1.2.3 From 11041ae65abfeaea959060ad17d167732f604ecf Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 3 Jul 2012 16:44:14 +0800 Subject: mtd: use MTD_OPS_PLACE_OOB macro consistently Use the MTD_OPS_PLACE_OOB to replace the hard code "0". Make the code more readable. Signed-off-by: Huang Shijie Acked-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 98ba46ecd5d8..ead301a455ee 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1625,7 +1625,7 @@ static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, ops.len = len; ops.datbuf = buf; ops.oobbuf = NULL; - ops.mode = 0; + ops.mode = MTD_OPS_PLACE_OOB; ret = nand_do_read_ops(mtd, from, &ops); *retlen = ops.retlen; nand_release_device(mtd); @@ -2331,7 +2331,7 @@ static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, ops.len = len; ops.datbuf = (uint8_t *)buf; ops.oobbuf = NULL; - ops.mode = 0; + ops.mode = MTD_OPS_PLACE_OOB; ret = nand_do_write_ops(mtd, to, &ops); @@ -2360,7 +2360,7 @@ static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, ops.len = len; ops.datbuf = (uint8_t *)buf; ops.oobbuf = NULL; - ops.mode = 0; + ops.mode = MTD_OPS_PLACE_OOB; ret = nand_do_write_ops(mtd, to, &ops); *retlen = ops.retlen; nand_release_device(mtd); -- cgit v1.2.3 From 44ed0ffdbc0e7ce2bd8954b79626df45d679d189 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 3 Jul 2012 16:44:15 +0800 Subject: mtd: fix typo in comment fix the comment for nand_bbt.c Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 3df8d92c5e08..2d1d2fa9dfc5 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -22,7 +22,7 @@ * BBT on flash. If a BBT is found then the contents are read and the memory * based BBT is created. If a mirrored BBT is selected then the mirror is * searched too and the versions are compared. If the mirror has a greater - * version number than the mirror BBT is used to build the memory based BBT. + * version number, then the mirror BBT is used to build the memory based BBT. * If the tables are not versioned, then we "or" the bad block information. * If one of the BBTs is out of date or does not exist it is (re)created. * If no BBT exists at all then the device is scanned for factory marked -- cgit v1.2.3 From c50c69402ac24641da38c146796c199387b97f8d Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 3 Jul 2012 16:24:32 +0800 Subject: mtd: gpmi: add on-flash BBT support for gpmi nand add the on flash bbt support for gpmi nand driver. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index d6fa8f4779ce..5d9796acc49a 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "gpmi-nand.h" /* add our owner bbt descriptor */ @@ -1502,6 +1503,8 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this) chip->ecc.size = 1; chip->ecc.strength = 8; chip->ecc.layout = &gpmi_hw_ecclayout; + if (of_get_nand_on_flash_bbt(this->dev->of_node)) + chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */ this->bch_geometry.payload_size = 1024; -- cgit v1.2.3 From e0dd89c56edc9274c513dbd2ba6dc8229aeeaa44 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 3 Jul 2012 16:24:33 +0800 Subject: mtd: gpmi: update the bitflip_threshold The origin code misses to update the bitflip_threshold when we have already get the right ecc_strength. The patch fixes it. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 5d9796acc49a..9da9ee88a824 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -1442,6 +1442,7 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data *this) /* Adjust the ECC strength according to the chip. */ this->nand.ecc.strength = this->bch_geometry.ecc_strength; this->mtd.ecc_strength = this->bch_geometry.ecc_strength; + this->mtd.bitflip_threshold = this->bch_geometry.ecc_strength; /* NAND boot init, depends on the gpmi_set_geometry(). */ return nand_boot_init(this); -- cgit v1.2.3 From d76236f30f1280f9345bb266a161e3ba60518c83 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Thu, 5 Jul 2012 12:41:01 +0200 Subject: mtd: sh_flctl: Use memcpy() instead of using a loop Elements have been copied "manually" in a loop. Better use memcpy(). Signed-off-by: Bastian Hecht Reviewed-by: Simon Horman Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index ed03ed2355de..1343315b37ba 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -746,10 +747,9 @@ static void flctl_select_chip(struct mtd_info *mtd, int chipnr) static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { struct sh_flctl *flctl = mtd_to_flctl(mtd); - int i, index = flctl->index; + int index = flctl->index; - for (i = 0; i < len; i++) - flctl->done_buff[index + i] = buf[i]; + memcpy(&flctl->done_buff[index], buf, len); flctl->index += len; } @@ -778,10 +778,11 @@ static uint16_t flctl_read_word(struct mtd_info *mtd) static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { - int i; + struct sh_flctl *flctl = mtd_to_flctl(mtd); + int index = flctl->index; - for (i = 0; i < len; i++) - buf[i] = flctl_read_byte(mtd); + memcpy(buf, &flctl->done_buff[index], len); + flctl->index += len; } static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -- cgit v1.2.3 From 894824f9731a805b70b553220ae58e5475ff6ff1 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Thu, 5 Jul 2012 12:41:02 +0200 Subject: mtd: sh_flctl: Only copy OOB data if it is required Check the new oob_required flag and only copy the OOB data to the internal buffer if needed. Signed-off-by: Bastian Hecht Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/sh_flctl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 1343315b37ba..4ff8ef526c02 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -396,7 +396,8 @@ static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { chip->read_buf(mtd, buf, mtd->writesize); - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + if (oob_required) + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); return 0; } -- cgit v1.2.3 From ff506172a30080963853dc0d259566c82fe8626c Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Mon, 2 Jul 2012 21:39:32 -0400 Subject: mtd: gpmi: change the code for clocks The gpmi nand driver may needs several clocks(MX6Q needs five clocks). In the old clock framework, all these clocks are chained together, all you need is to manipulate the first clock. But the kernel uses the common clk framework now, which forces us to get the clocks one by one. When we use them, we have to enable them one by one too. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 45 +++++++++++++++---- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 82 ++++++++++++++++++++++++++++++---- drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 3 +- 3 files changed, 112 insertions(+), 18 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index a1f43329ad43..6bb0998dcb40 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -124,12 +124,42 @@ error: return -ETIMEDOUT; } +static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v) +{ + struct clk *clk; + int ret; + int i; + + for (i = 0; i < GPMI_CLK_MAX; i++) { + clk = this->resources.clock[i]; + if (!clk) + break; + + if (v) { + ret = clk_prepare_enable(clk); + if (ret) + goto err_clk; + } else { + clk_disable_unprepare(clk); + } + } + return 0; + +err_clk: + for (; i > 0; i--) + clk_disable_unprepare(this->resources.clock[i - 1]); + return ret; +} + +#define gpmi_enable_clk(x) __gpmi_enable_clk(x, true) +#define gpmi_disable_clk(x) __gpmi_enable_clk(x, false) + int gpmi_init(struct gpmi_nand_data *this) { struct resources *r = &this->resources; int ret; - ret = clk_prepare_enable(r->clock); + ret = gpmi_enable_clk(this); if (ret) goto err_out; ret = gpmi_reset_block(r->gpmi_regs, false); @@ -149,7 +179,7 @@ int gpmi_init(struct gpmi_nand_data *this) /* Select BCH ECC. */ writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET); - clk_disable_unprepare(r->clock); + gpmi_disable_clk(this); return 0; err_out: return ret; @@ -205,7 +235,7 @@ int bch_set_geometry(struct gpmi_nand_data *this) ecc_strength = bch_geo->ecc_strength >> 1; page_size = bch_geo->page_size; - ret = clk_prepare_enable(r->clock); + ret = gpmi_enable_clk(this); if (ret) goto err_out; @@ -240,7 +270,7 @@ int bch_set_geometry(struct gpmi_nand_data *this) writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, r->bch_regs + HW_BCH_CTRL_SET); - clk_disable_unprepare(r->clock); + gpmi_disable_clk(this); return 0; err_out: return ret; @@ -716,7 +746,7 @@ void gpmi_begin(struct gpmi_nand_data *this) int ret; /* Enable the clock. */ - ret = clk_prepare_enable(r->clock); + ret = gpmi_enable_clk(this); if (ret) { pr_err("We failed in enable the clk\n"); goto err_out; @@ -727,7 +757,7 @@ void gpmi_begin(struct gpmi_nand_data *this) gpmi_regs + HW_GPMI_TIMING1); /* Get the timing information we need. */ - nfc->clock_frequency_in_hz = clk_get_rate(r->clock); + nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]); clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz; gpmi_nfc_compute_hardware_timing(this, &hw); @@ -784,8 +814,7 @@ err_out: void gpmi_end(struct gpmi_nand_data *this) { - struct resources *r = &this->resources; - clk_disable_unprepare(r->clock); + gpmi_disable_clk(this); } /* Clears a BCH interrupt. */ diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 9da9ee88a824..8c0d2f0a526f 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -465,9 +465,78 @@ acquire_err: return -EINVAL; } +static void gpmi_put_clks(struct gpmi_nand_data *this) +{ + struct resources *r = &this->resources; + struct clk *clk; + int i; + + for (i = 0; i < GPMI_CLK_MAX; i++) { + clk = r->clock[i]; + if (clk) { + clk_put(clk); + r->clock[i] = NULL; + } + } +} + +static char *extra_clks_for_mx6q[GPMI_CLK_MAX] = { + "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch", +}; + +static int __devinit gpmi_get_clks(struct gpmi_nand_data *this) +{ + struct resources *r = &this->resources; + char **extra_clks = NULL; + struct clk *clk; + int i; + + /* The main clock is stored in the first. */ + r->clock[0] = clk_get(this->dev, "gpmi_io"); + if (IS_ERR(r->clock[0])) + goto err_clock; + + /* Get extra clocks */ + if (GPMI_IS_MX6Q(this)) + extra_clks = extra_clks_for_mx6q; + if (!extra_clks) + return 0; + + for (i = 1; i < GPMI_CLK_MAX; i++) { + if (extra_clks[i - 1] == NULL) + break; + + clk = clk_get(this->dev, extra_clks[i - 1]); + if (IS_ERR(clk)) + goto err_clock; + + r->clock[i] = clk; + } + + if (GPMI_IS_MX6Q(this)) { + /* + * Set the default values for the clocks in mx6q: + * The main clock(enfc) : 22MHz + * The others : 44.5MHz + * + * These are just the default values. If you want to use + * the ONFI nand which is in the Synchronous Mode, you should + * change the clocks's frequencies as you need. + */ + clk_set_rate(r->clock[0], 22000000); + for (i = 1; i < GPMI_CLK_MAX && r->clock[i]; i++) + clk_set_rate(r->clock[i], 44500000); + } + return 0; + +err_clock: + dev_dbg(this->dev, "failed in finding the clocks.\n"); + gpmi_put_clks(this); + return -ENOMEM; +} + static int __devinit acquire_resources(struct gpmi_nand_data *this) { - struct resources *res = &this->resources; struct pinctrl *pinctrl; int ret; @@ -493,12 +562,9 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this) goto exit_pin; } - res->clock = clk_get(&this->pdev->dev, NULL); - if (IS_ERR(res->clock)) { - pr_err("can not get the clock\n"); - ret = -ENOENT; + ret = gpmi_get_clks(this); + if (ret) goto exit_clock; - } return 0; exit_clock: @@ -513,9 +579,7 @@ exit_regs: static void release_resources(struct gpmi_nand_data *this) { - struct resources *r = &this->resources; - - clk_put(r->clock); + gpmi_put_clks(this); release_register_block(this); release_bch_irq(this); release_dma_channels(this); diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index ce5daa160920..1547a60c1c6f 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -22,6 +22,7 @@ #include #include +#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */ struct resources { void *gpmi_regs; void *bch_regs; @@ -29,7 +30,7 @@ struct resources { unsigned int bch_high_interrupt; unsigned int dma_low_channel; unsigned int dma_high_channel; - struct clk *clock; + struct clk *clock[GPMI_CLK_MAX]; }; /** -- cgit v1.2.3 From 7b5a2d40978fbb046b99b4030ce2785b66a451a5 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Jun 2012 16:35:41 -0700 Subject: mtd: nand: remove unused 'int' return codes The return codes for read_abs_bbts() and search_read_bbts() are always non-zero, and so don't have much meaning. Just remove them. Signed-off-by: Brian Norris Reviewed-by: Shmulik Ladkani Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 2d1d2fa9dfc5..e23115be079e 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -370,8 +370,8 @@ static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td) * Read the bad block table(s) for all chips starting at a given page. We * assume that the bbt bits are in consecutive order. */ -static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, - struct nand_bbt_descr *td, struct nand_bbt_descr *md) +static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md) { struct nand_chip *this = mtd->priv; @@ -392,7 +392,6 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, pr_info("Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); } - return 1; } /* Scan a given block full */ @@ -623,7 +622,9 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr * * Search and read the bad block table(s). */ -static int search_read_bbts(struct mtd_info *mtd, uint8_t * buf, struct nand_bbt_descr *td, struct nand_bbt_descr *md) +static void search_read_bbts(struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, + struct nand_bbt_descr *md) { /* Search the primary table */ search_bbt(mtd, buf, td); @@ -631,9 +632,6 @@ static int search_read_bbts(struct mtd_info *mtd, uint8_t * buf, struct nand_bbt /* Search the mirror table */ if (md) search_bbt(mtd, buf, md); - - /* Force result check */ - return 1; } /** @@ -1159,14 +1157,13 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) /* Is the bbt at a given page? */ if (td->options & NAND_BBT_ABSPAGE) { - res = read_abs_bbts(mtd, buf, td, md); + read_abs_bbts(mtd, buf, td, md); } else { /* Search the bad block table using a pattern in oob */ - res = search_read_bbts(mtd, buf, td, md); + search_read_bbts(mtd, buf, td, md); } - if (res) - res = check_create(mtd, buf, bd); + res = check_create(mtd, buf, bd); /* Prevent the bbt regions from erasing / writing */ mark_bbt_region(mtd, td); -- cgit v1.2.3 From 491ed06f334955578f0c43d298c46ea1a7ea9e1b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Jun 2012 16:35:44 -0700 Subject: mtd: nand_bbt: use string library Some nand_bbt code can be shortened by using memcmp() and memchr_inv(). As an added bonus, there is a possible performance benefit. Borrowed some code from Akinobu Mita. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index e23115be079e..f5839f06cece 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -68,6 +68,7 @@ #include #include #include +#include static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) { @@ -89,19 +90,16 @@ static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) */ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) { - int i, end = 0; + int end = 0; uint8_t *p = buf; if (td->options & NAND_BBT_NO_OOB) return check_pattern_no_oob(buf, td); end = paglen + td->offs; - if (td->options & NAND_BBT_SCANEMPTY) { - for (i = 0; i < end; i++) { - if (p[i] != 0xff) - return -1; - } - } + if (td->options & NAND_BBT_SCANEMPTY) + if (memchr_inv(p, 0xff, end)) + return -1; p += end; /* Compare the pattern */ @@ -111,10 +109,8 @@ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_desc if (td->options & NAND_BBT_SCANEMPTY) { p += td->len; end += td->len; - for (i = end; i < len; i++) { - if (*p++ != 0xff) - return -1; - } + if (memchr_inv(p, 0xff, len - end)) + return -1; } return 0; } @@ -130,14 +126,9 @@ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_desc */ static int check_short_pattern(uint8_t *buf, struct nand_bbt_descr *td) { - int i; - uint8_t *p = buf; - /* Compare the pattern */ - for (i = 0; i < td->len; i++) { - if (p[td->offs + i] != td->pattern[i]) - return -1; - } + if (memcmp(buf + td->offs, td->pattern, td->len)) + return -1; return 0; } -- cgit v1.2.3 From a7e68834fc273930c17e3decaddc13acb87a7dce Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Jun 2012 16:35:45 -0700 Subject: mtd: nand: use ECC, if present, when scanning OOB scan_read_raw_oob() is used in only in places where the MTD_OPS_PLACE_OOB mode is preferable to MTD_OPS_RAW mode, so use MTD_OPS_PLACE_OOB instead. MTD_OPS_PLACE_OOB provides the same functionality with the potential[1] added bonus of error correction. This brings scan_block_full() in line with scan_block_fast() so that they both read bad block markers with MTD_OPS_PLACE_OOB. This can help in preventing 0xff markers (in good blocks) from being interpreted as bad block indicators in the presence of a single bitflip. Note that ECC error codes (EUCLEAN or EBADMSG) are already silently ignored in all users of scan_read_raw_oob(). [1] Few drivers perform proper error correction on OOB data. In those cases, the use of MTD_OPS_RAW vs. MTD_OPS_PLACE_OOB is not significant. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index f5839f06cece..0e928f3efaa4 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -289,14 +289,24 @@ static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, return mtd_read(mtd, offs, len, &retlen, buf); } -/* Scan read raw data from flash */ +/** + * scan_read_raw_oob - [GENERIC] Scan data+OOB region to buffer + * @mtd: MTD device structure + * @buf: temporary buffer + * @offs: offset at which to scan + * @len: length of data region to read + * + * Scan read data from data+OOB. May traverse multiple pages, interleaving + * page,OOB,page,OOB,... in buf. Completes transfer and returns the "strongest" + * ECC condition (error or bitflip). May quit on the first (non-ECC) error. + */ static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, size_t len) { struct mtd_oob_ops ops; - int res; + int res, ret = 0; - ops.mode = MTD_OPS_RAW; + ops.mode = MTD_OPS_PLACE_OOB; ops.ooboffs = 0; ops.ooblen = mtd->oobsize; @@ -306,15 +316,18 @@ static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, ops.oobbuf = buf + ops.len; res = mtd_read_oob(mtd, offs, &ops); - - if (res) - return res; + if (res) { + if (!mtd_is_bitflip_or_eccerr(res)) + return res; + else if (mtd_is_eccerr(res) || !ret) + ret = res; + } buf += mtd->oobsize + mtd->writesize; len -= mtd->writesize; offs += mtd->writesize; } - return 0; + return ret; } static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs, -- cgit v1.2.3 From af69dcd3862ed174cf67637f4142c9c895862436 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Jun 2012 16:35:42 -0700 Subject: mtd: nand: rename '_raw' BBT scan functions None of these scanning functions use MTD_OPS_RAW mode any more, so there's really nothing 'raw' about them. Rename them to (hopefully) make the code a little clearer. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 0e928f3efaa4..9a5402e320bf 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -276,7 +276,7 @@ static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc } /* BBT marker is in the first page, no OOB */ -static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, +static int scan_read_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, struct nand_bbt_descr *td) { size_t retlen; @@ -290,7 +290,7 @@ static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, } /** - * scan_read_raw_oob - [GENERIC] Scan data+OOB region to buffer + * scan_read_oob - [GENERIC] Scan data+OOB region to buffer * @mtd: MTD device structure * @buf: temporary buffer * @offs: offset at which to scan @@ -300,7 +300,7 @@ static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, * page,OOB,page,OOB,... in buf. Completes transfer and returns the "strongest" * ECC condition (error or bitflip). May quit on the first (non-ECC) error. */ -static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, +static int scan_read_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, size_t len) { struct mtd_oob_ops ops; @@ -330,13 +330,13 @@ static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, return ret; } -static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs, +static int scan_read(struct mtd_info *mtd, uint8_t *buf, loff_t offs, size_t len, struct nand_bbt_descr *td) { if (td->options & NAND_BBT_NO_OOB) - return scan_read_raw_data(mtd, buf, offs, td); + return scan_read_data(mtd, buf, offs, td); else - return scan_read_raw_oob(mtd, buf, offs, len); + return scan_read_oob(mtd, buf, offs, len); } /* Scan write data with oob to flash */ @@ -381,7 +381,7 @@ static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the primary version, if available */ if (td->options & NAND_BBT_VERSION) { - scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift, + scan_read(mtd, buf, (loff_t)td->pages[0] << this->page_shift, mtd->writesize, td); td->version[0] = buf[bbt_get_ver_offs(mtd, td)]; pr_info("Bad block table at page %d, version 0x%02X\n", @@ -390,7 +390,7 @@ static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the mirror version, if available */ if (md && (md->options & NAND_BBT_VERSION)) { - scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift, + scan_read(mtd, buf, (loff_t)md->pages[0] << this->page_shift, mtd->writesize, md); md->version[0] = buf[bbt_get_ver_offs(mtd, md)]; pr_info("Bad block table at page %d, version 0x%02X\n", @@ -405,7 +405,7 @@ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd, { int ret, j; - ret = scan_read_raw_oob(mtd, buf, offs, readlen); + ret = scan_read_oob(mtd, buf, offs, readlen); /* Ignore ECC errors when checking for BBM */ if (ret && !mtd_is_bitflip_or_eccerr(ret)) return ret; @@ -594,7 +594,7 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr loff_t offs = (loff_t)actblock << this->bbt_erase_shift; /* Read first page */ - scan_read_raw(mtd, buf, offs, mtd->writesize, td); + scan_read(mtd, buf, offs, mtd->writesize, td); if (!check_pattern(buf, scanlen, mtd->writesize, td)) { td->pages[i] = actblock << blocktopage; if (td->options & NAND_BBT_VERSION) { -- cgit v1.2.3 From de20c22d2bf41f970a6300a89dd550f12121c126 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 16 Aug 2012 15:15:34 +0200 Subject: mtd: lpc32xx_slc: Make driver independent of AMBA DMA engine driver This patch makes the SLC NAND driver independent of the single AMBA DMA engine driver by using the platform data provided dma_filter callback. Signed-off-by: Roland Stigge Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_slc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index c8c1d06b35ab..184035045208 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #define LPC32XX_MODNAME "lpc32xx-nand" @@ -199,6 +199,7 @@ struct lpc32xx_nand_cfg_slc { struct lpc32xx_nand_host { struct nand_chip nand_chip; + struct lpc32xx_slc_platform_data *pdata; struct clk *clk; struct mtd_info mtd; void __iomem *io_base; @@ -719,9 +720,15 @@ static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) struct mtd_info *mtd = &host->mtd; dma_cap_mask_t mask; + if (!host->pdata || !host->pdata->dma_filter) { + dev_err(mtd->dev.parent, "no DMA platform data\n"); + return -ENOENT; + } + dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-slc"); + host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, + "nand-slc"); if (!host->dma_chan) { dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); return -EBUSY; @@ -819,6 +826,8 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) } lpc32xx_wp_disable(host); + host->pdata = pdev->dev.platform_data; + mtd = &host->mtd; chip = &host->nand_chip; chip->priv = host; -- cgit v1.2.3 From 9c6f62a7ef230253a7dfc0547c431f07d8a64721 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 16 Aug 2012 15:15:35 +0200 Subject: mtd: lpc32xx_mlc: Make driver independent of AMBA DMA engine driver This patch makes the MLC NAND driver independent of the single AMBA DMA engine driver by using the platform data provided dma_filter callback. Signed-off-by: Roland Stigge Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_mlc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_mlc.c b/drivers/mtd/nand/lpc32xx_mlc.c index 1cf35932a4d5..5da31795b693 100644 --- a/drivers/mtd/nand/lpc32xx_mlc.c +++ b/drivers/mtd/nand/lpc32xx_mlc.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -171,6 +171,7 @@ static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = { struct lpc32xx_nand_host { struct nand_chip nand_chip; + struct lpc32xx_mlc_platform_data *pdata; struct clk *clk; struct mtd_info mtd; void __iomem *io_base; @@ -581,9 +582,15 @@ static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) struct mtd_info *mtd = &host->mtd; dma_cap_mask_t mask; + if (!host->pdata || !host->pdata->dma_filter) { + dev_err(mtd->dev.parent, "no DMA platform data\n"); + return -ENOENT; + } + dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-mlc"); + host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, + "nand-mlc"); if (!host->dma_chan) { dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); return -EBUSY; @@ -703,6 +710,8 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) } lpc32xx_wp_disable(host); + host->pdata = pdev->dev.platform_data; + nand_chip->priv = host; /* link the private data structures */ mtd->priv = nand_chip; mtd->owner = THIS_MODULE; -- cgit v1.2.3 From aa6d01fa435a6f701128829f8d9d04208fd53176 Mon Sep 17 00:00:00 2001 From: Mike Dunn Date: Wed, 11 Jul 2012 11:08:19 -0700 Subject: mtd: docg4: fix oob reads This patch does two closely related things: (1) Currently the ecc.read_page() method does not fill the nand->oob_poi buffer with the oob data, but instead reads oob into a local buffer. Fix this by filling the oob_poi buffer instead of a local buffer. The 'oob_required' argument is quietly ignored; the device must always read oob after the page data, and it is presumed that there's no harm in filling oob_poi, even when not explicitly requested. (2) Always read oob from the device in ecc.read_oob(), instead of copying it from a local buffer under some circumstances. Signed-off-by: Mike Dunn Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/docg4.c | 33 ++++++--------------------------- 1 file changed, 6 insertions(+), 27 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c index 0f2ffd7b6c82..793921e56f8e 100644 --- a/drivers/mtd/nand/docg4.c +++ b/drivers/mtd/nand/docg4.c @@ -378,9 +378,9 @@ static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page) * bit flips(s) are not reported in stats. */ - if (doc->oob_buf[15]) { + if (nand->oob_poi[15]) { int bit, numsetbits = 0; - unsigned long written_flag = doc->oob_buf[15]; + unsigned long written_flag = nand->oob_poi[15]; for_each_set_bit(bit, &written_flag, 8) numsetbits++; if (numsetbits > 4) { /* assume blank */ @@ -428,7 +428,7 @@ static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page) /* if error within oob area preceeding ecc bytes... */ if (errpos[i] > DOCG4_PAGE_SIZE * 8) change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8, - (unsigned long *)doc->oob_buf); + (unsigned long *)nand->oob_poi); else /* error in page data */ change_bit(errpos[i], (unsigned long *)buf); @@ -748,18 +748,12 @@ static int read_page(struct mtd_info *mtd, struct nand_chip *nand, docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */ - /* - * Diskonchips read oob immediately after a page read. Mtd - * infrastructure issues a separate command for reading oob after the - * page is read. So we save the oob bytes in a local buffer and just - * copy it if the next command reads oob from the same page. - */ - + /* this device always reads oob after page data */ /* first 14 oob bytes read from I/O reg */ - docg4_read_buf(mtd, doc->oob_buf, 14); + docg4_read_buf(mtd, nand->oob_poi, 14); /* last 2 read from another reg */ - buf16 = (uint16_t *)(doc->oob_buf + 14); + buf16 = (uint16_t *)(nand->oob_poi + 14); *buf16 = readw(docptr + DOCG4_MYSTERY_REG); write_nop(docptr); @@ -807,21 +801,6 @@ static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand, dev_dbg(doc->dev, "%s: page %x\n", __func__, page); - /* - * Oob bytes are read as part of a normal page read. If the previous - * nand command was a read of the page whose oob is now being read, just - * copy the oob bytes that we saved in a local buffer and avoid a - * separate oob read. - */ - if (doc->last_command.command == NAND_CMD_READ0 && - doc->last_command.page == page) { - memcpy(nand->oob_poi, doc->oob_buf, 16); - return 0; - } - - /* - * Separate read of oob data only. - */ docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page); writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0); -- cgit v1.2.3 From 28446acb1f8268cda4b2076f72519534f84d6a36 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 12 Jul 2012 10:31:08 +0200 Subject: mtd: atmel nand: fix gpio missing request without this the gpio will not be muxed as a gpio by the current custom pinmux or later by the pinctrl Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/atmel_nand.c | 65 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 63 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 647275524e09..914455783302 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1399,7 +1399,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev) if (pdev->dev.of_node) { res = atmel_of_init_port(host, pdev->dev.of_node); if (res) - goto err_nand_ioremap; + goto err_ecc_ioremap; } else { memcpy(&host->board, pdev->dev.platform_data, sizeof(struct atmel_nand_data)); @@ -1414,8 +1414,43 @@ static int __init atmel_nand_probe(struct platform_device *pdev) nand_chip->IO_ADDR_W = host->io_base; nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; - if (gpio_is_valid(host->board.rdy_pin)) + if (gpio_is_valid(host->board.rdy_pin)) { + res = gpio_request(host->board.rdy_pin, "nand_rdy"); + if (res < 0) { + dev_err(&pdev->dev, + "can't request rdy gpio %d\n", + host->board.rdy_pin); + goto err_ecc_ioremap; + } + + res = gpio_direction_input(host->board.rdy_pin); + if (res < 0) { + dev_err(&pdev->dev, + "can't request input direction rdy gpio %d\n", + host->board.rdy_pin); + goto err_ecc_ioremap; + } + nand_chip->dev_ready = atmel_nand_device_ready; + } + + if (gpio_is_valid(host->board.enable_pin)) { + res = gpio_request(host->board.enable_pin, "nand_enable"); + if (res < 0) { + dev_err(&pdev->dev, + "can't request enable gpio %d\n", + host->board.enable_pin); + goto err_ecc_ioremap; + } + + res = gpio_direction_output(host->board.enable_pin, 1); + if (res < 0) { + dev_err(&pdev->dev, + "can't request output direction enable gpio %d\n", + host->board.enable_pin); + goto err_ecc_ioremap; + } + } nand_chip->ecc.mode = host->board.ecc_mode; nand_chip->chip_delay = 20; /* 20us command delay time */ @@ -1430,6 +1465,22 @@ static int __init atmel_nand_probe(struct platform_device *pdev) atmel_nand_enable(host); if (gpio_is_valid(host->board.det_pin)) { + res = gpio_request(host->board.det_pin, "nand_det"); + if (res < 0) { + dev_err(&pdev->dev, + "can't request det gpio %d\n", + host->board.det_pin); + goto err_no_card; + } + + res = gpio_direction_input(host->board.det_pin); + if (res < 0) { + dev_err(&pdev->dev, + "can't request input direction det gpio %d\n", + host->board.det_pin); + goto err_no_card; + } + if (gpio_get_value(host->board.det_pin)) { printk(KERN_INFO "No SmartMedia card inserted.\n"); res = -ENXIO; @@ -1509,6 +1560,7 @@ err_no_card: platform_set_drvdata(pdev, NULL); if (host->dma_chan) dma_release_channel(host->dma_chan); +err_ecc_ioremap: iounmap(host->io_base); err_nand_ioremap: kfree(host); @@ -1534,6 +1586,15 @@ static int __exit atmel_nand_remove(struct platform_device *pdev) pmecc_data_free(host); } + if (gpio_is_valid(host->board.det_pin)) + gpio_free(host->board.det_pin); + + if (gpio_is_valid(host->board.enable_pin)) + gpio_free(host->board.enable_pin); + + if (gpio_is_valid(host->board.rdy_pin)) + gpio_free(host->board.rdy_pin); + if (host->ecc) iounmap(host->ecc); if (host->pmecc_rom_base) -- cgit v1.2.3 From bf7a01bf7987b63b121d572b240c132ec44129c4 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 13 Jul 2012 09:28:24 -0700 Subject: mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It silently masks off at least one flag that might be set by the driver (NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly others. Really, as long as driver writers exercise a small amount of care with NAND_* options, this mask is not necessary at all; it was only here to prevent certain options from accidentally being set by the driver. But the original thought turns out to be a bad idea occasionally. Thus, kill it. Note, this patch fixes some major gpmi-nand breakage. Signed-off-by: Brian Norris Tested-by: Huang Shijie Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ead301a455ee..996cc4836885 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2909,8 +2909,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, if (le16_to_cpu(p->features) & 1) *busw = NAND_BUSWIDTH_16; - chip->options &= ~NAND_CHIPOPTIONS_MSK; - pr_info("ONFI flash detected\n"); return 1; } @@ -3074,9 +3072,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, mtd->erasesize <<= ((id_data[3] & 0x03) << 1); } } - /* Get chip options, preserve non chip based options */ - chip->options &= ~NAND_CHIPOPTIONS_MSK; - chip->options |= type->options & NAND_CHIPOPTIONS_MSK; + /* Get chip options */ + chip->options |= type->options; /* * Check if chip is not a Samsung device. Do not clear the -- cgit v1.2.3 From 4cacbe226f39061f3e6730a08e3323e04a0de03f Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Thu, 19 Jul 2012 13:21:04 +0200 Subject: mtd: omap2: fix some typos in comments Signed-off-by: Peter Meerwald Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/omap2.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index ac4fd756eda3..1ede9fb43430 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -347,7 +347,7 @@ static void omap_nand_dma_callback(void *data) } /* - * omap_nand_dma_transfer: configer and start dma transfer + * omap_nand_dma_transfer: configure and start dma transfer * @mtd: MTD device structure * @addr: virtual address in RAM of source/destination * @len: number of data bytes to be transferred @@ -463,7 +463,7 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd, } /* - * omap_nand_irq - GMPC irq handler + * omap_nand_irq - GPMC irq handler * @this_irq: gpmc irq number * @dev: omap_nand_info structure pointer is passed here */ @@ -1205,8 +1205,8 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) /* * If RDY/BSY line is connected to OMAP then use the omap ready - * funcrtion and the generic nand_wait function which reads the status - * register after monitoring the RDY/BSY line.Otherwise use a standard + * function and the generic nand_wait function which reads the status + * register after monitoring the RDY/BSY line. Otherwise use a standard * chip delay which is slightly more than tR (AC Timing) of the NAND * device and read status register until you get a failure or success */ @@ -1287,7 +1287,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.verify_buf = omap_verify_buf; - /* selsect the ecc type */ + /* select the ecc type */ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) info->nand.ecc.mode = NAND_ECC_SOFT; else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || -- cgit v1.2.3 From 27c84fa5844039480daf7223d59c10ea1a173dc7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 25 Jul 2012 08:18:18 -0300 Subject: mtd: nand: Include IMX6 in the list of supported SoCs Include IMX6 in the list of supported SoCs. Signed-off-by: Fabio Estevam Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 588e98930aac..5708d3b28a98 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -464,7 +464,7 @@ config MTD_NAND_GPMI_NAND bool "GPMI NAND Flash Controller driver" depends on MTD_NAND && MXS_DMA help - Enables NAND Flash support for IMX23 or IMX28. + Enables NAND Flash support for IMX23, IMX28 or IMX6. The GPMI controller is very powerful, with the help of BCH module, it can do the hardware ECC. The GPMI supports several NAND flashs at the same time. The GPMI may conflicts with other -- cgit v1.2.3 From 056fcab51c8a9e7735f5441efaa82d9201ac4d8d Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 16 Jul 2012 16:02:22 +0530 Subject: mtd: s3c2410: Use module_platform_driver() This makes the code simpler by eliminating module_init() and module_exit(). Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 91121f33f743..8f9267fe29fd 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -1134,20 +1134,7 @@ static struct platform_driver s3c24xx_nand_driver = { }, }; -static int __init s3c2410_nand_init(void) -{ - printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); - - return platform_driver_register(&s3c24xx_nand_driver); -} - -static void __exit s3c2410_nand_exit(void) -{ - platform_driver_unregister(&s3c24xx_nand_driver); -} - -module_init(s3c2410_nand_init); -module_exit(s3c2410_nand_exit); +module_platform_driver(s3c24xx_nand_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Ben Dooks "); -- cgit v1.2.3 From 92aeb5d20c188fc7c28d7a5895a6b2f56038a2bd Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 16 Jul 2012 16:02:23 +0530 Subject: mtd: s3c2410: Use pr_* instead of printk Use pr_* instead of printk. Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 8f9267fe29fd..3021b174761f 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -21,6 +21,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#define pr_fmt(fmt) "nand-s3c2410: " fmt + #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG #define DEBUG #endif @@ -215,7 +217,8 @@ static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) pr_debug("result %d from %ld, %d\n", result, clk, wanted); if (result > max) { - printk("%d ns is too big for current clock rate %ld\n", wanted, clk); + pr_err("%d ns is too big for current clock rate %ld\n", + wanted, clk); return -1; } -- cgit v1.2.3 From d2a89be8e7cedbc7aba7f0265459e75e6627614c Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 16 Jul 2012 16:02:24 +0530 Subject: mtd: s3c2410: Use instead of Fixes the following checkpatch warning: WARNING: Use #include instead of Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 3021b174761f..f9bbf55f4b0f 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -45,8 +46,6 @@ #include #include -#include - #include #include -- cgit v1.2.3 From a68c5ec85685a8eb7a93a0577f91c5e0952df39e Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 16 Jul 2012 16:02:25 +0530 Subject: mtd: s3c2410: Do not initialise statics to 0 or NULL Fixes the following checkpatch errors: ERROR: do not initialise statics to 0 or NULL +static int hardware_ecc = 0; ERROR: do not initialise statics to 0 or NULL +static const int clock_stop = 0; Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 64 +++++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 37 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index f9bbf55f4b0f..38cecc9620e4 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -49,19 +49,6 @@ #include #include -#ifdef CONFIG_MTD_NAND_S3C2410_HWECC -static int hardware_ecc = 1; -#else -static int hardware_ecc = 0; -#endif - -#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP -static const int clock_stop = 1; -#else -static const int clock_stop = 0; -#endif - - /* new oob placement block for use with hardware ecc generation */ @@ -170,7 +157,11 @@ static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) static inline int allow_clk_suspend(struct s3c2410_nand_info *info) { - return clock_stop; +#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP + return 1; +#else + return 0; +#endif } /** @@ -821,32 +812,31 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, nmtd->mtd.owner = THIS_MODULE; nmtd->set = set; - if (hardware_ecc) { +#ifdef CONFIG_MTD_NAND_S3C2410_HWECC + chip->ecc.calculate = s3c2410_nand_calculate_ecc; + chip->ecc.correct = s3c2410_nand_correct_data; + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.strength = 1; + + switch (info->cpu_type) { + case TYPE_S3C2410: + chip->ecc.hwctl = s3c2410_nand_enable_hwecc; chip->ecc.calculate = s3c2410_nand_calculate_ecc; - chip->ecc.correct = s3c2410_nand_correct_data; - chip->ecc.mode = NAND_ECC_HW; - chip->ecc.strength = 1; - - switch (info->cpu_type) { - case TYPE_S3C2410: - chip->ecc.hwctl = s3c2410_nand_enable_hwecc; - chip->ecc.calculate = s3c2410_nand_calculate_ecc; - break; - - case TYPE_S3C2412: - chip->ecc.hwctl = s3c2412_nand_enable_hwecc; - chip->ecc.calculate = s3c2412_nand_calculate_ecc; - break; - - case TYPE_S3C2440: - chip->ecc.hwctl = s3c2440_nand_enable_hwecc; - chip->ecc.calculate = s3c2440_nand_calculate_ecc; - break; + break; - } - } else { - chip->ecc.mode = NAND_ECC_SOFT; + case TYPE_S3C2412: + chip->ecc.hwctl = s3c2412_nand_enable_hwecc; + chip->ecc.calculate = s3c2412_nand_calculate_ecc; + break; + + case TYPE_S3C2440: + chip->ecc.hwctl = s3c2440_nand_enable_hwecc; + chip->ecc.calculate = s3c2440_nand_calculate_ecc; + break; } +#else + chip->ecc.mode = NAND_ECC_SOFT; +#endif if (set->ecc_layout != NULL) chip->ecc.layout = set->ecc_layout; -- cgit v1.2.3 From 54cd0208c6be19d6944f40a083fe97dd56de3489 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 16 Jul 2012 16:02:26 +0530 Subject: mtd: s3c2410: Fix checkpatch warnings and errors related to whitespaces Fixes checkpatch warnings and errors related to whitespaces. Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 38cecc9620e4..e82c679abe48 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -218,7 +218,7 @@ static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) return result; } -#define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) +#define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) /* controller setup */ @@ -261,7 +261,8 @@ static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) } dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", - tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); + tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), + twrph1, to_ns(twrph1, clkrate)); switch (info->cpu_type) { case TYPE_S3C2410: @@ -318,13 +319,13 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) if (ret < 0) return ret; - switch (info->cpu_type) { - case TYPE_S3C2410: + switch (info->cpu_type) { + case TYPE_S3C2410: default: break; - case TYPE_S3C2440: - case TYPE_S3C2412: + case TYPE_S3C2440: + case TYPE_S3C2412: /* enable the controller and de-assert nFCE */ writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); @@ -803,7 +804,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, dev_info(info->device, "System booted from NAND\n"); break; - } + } chip->IO_ADDR_R = chip->IO_ADDR_W; @@ -913,7 +914,7 @@ static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, static int s3c24xx_nand_probe(struct platform_device *pdev) { struct s3c2410_platform_nand *plat = to_nand_plat(pdev); - enum s3c_cpu_type cpu_type; + enum s3c_cpu_type cpu_type; struct s3c2410_nand_info *info; struct s3c2410_nand_mtd *nmtd; struct s3c2410_nand_set *sets; -- cgit v1.2.3 From f938bc563b4ca04013d02961dd423be10eee418a Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 21 Aug 2012 10:21:15 +0530 Subject: mtd: s3c2410: Fix line over 80 characters warning Fixes the following checkpatch warnings: WARNING: line over 80 characters Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index e82c679abe48..e71f7a951bf0 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -540,7 +540,8 @@ static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) unsigned long ctrl; ctrl = readl(info->regs + S3C2440_NFCONT); - writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT); + writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, + info->regs + S3C2440_NFCONT); } static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) @@ -552,7 +553,8 @@ static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); } -static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); @@ -566,7 +568,8 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u return 0; } -static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); @@ -575,12 +578,14 @@ static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u ecc_code[1] = ecc >> 8; ecc_code[2] = ecc >> 16; - pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); + pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", + ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } -static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); @@ -619,13 +624,15 @@ static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } -static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) { struct nand_chip *this = mtd->priv; writesb(this->IO_ADDR_W, buf, len); } -static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); @@ -669,7 +676,8 @@ static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) CPUFREQ_TRANSITION_NOTIFIER); } -static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) +static inline void +s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) { cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); @@ -681,7 +689,8 @@ static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) return 0; } -static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) +static inline void +s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) { } #endif @@ -1004,7 +1013,8 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) nmtd = info->mtds; for (setno = 0; setno < nr_sets; setno++, nmtd++) { - pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); + pr_debug("initialising set %d (%p, info %p)\n", + setno, nmtd, info); s3c2410_nand_init_chip(info, nmtd, sets); -- cgit v1.2.3 From cdeadd712f52b16a9285386d61ee26fd14eb4085 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Jul 2012 09:22:24 +0200 Subject: mtd: nand: davinci: add OF support for davinci nand controller add OF support for the davinci nand controller. Signed-off-by: Heiko Schocher Acked-by: Sekhar Nori Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/davinci_nand.c | 72 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d94b03c207af..f386b3c55031 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -518,9 +519,75 @@ static struct nand_ecclayout hwecc4_2048 __initconst = { }, }; +#if defined(CONFIG_OF) +static const struct of_device_id davinci_nand_of_match[] = { + {.compatible = "ti,davinci-nand", }, + {}, +} +MODULE_DEVICE_TABLE(of, davinci_nand_of_match); + +static struct davinci_nand_pdata + *nand_davinci_get_pdata(struct platform_device *pdev) +{ + if (!pdev->dev.platform_data && pdev->dev.of_node) { + struct davinci_nand_pdata *pdata; + const char *mode; + u32 prop; + int len; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct davinci_nand_pdata), + GFP_KERNEL); + pdev->dev.platform_data = pdata; + if (!pdata) + return NULL; + if (!of_property_read_u32(pdev->dev.of_node, + "ti,davinci-chipselect", &prop)) + pdev->id = prop; + if (!of_property_read_u32(pdev->dev.of_node, + "ti,davinci-mask-ale", &prop)) + pdata->mask_ale = prop; + if (!of_property_read_u32(pdev->dev.of_node, + "ti,davinci-mask-cle", &prop)) + pdata->mask_cle = prop; + if (!of_property_read_u32(pdev->dev.of_node, + "ti,davinci-mask-chipsel", &prop)) + pdata->mask_chipsel = prop; + if (!of_property_read_string(pdev->dev.of_node, + "ti,davinci-ecc-mode", &mode)) { + if (!strncmp("none", mode, 4)) + pdata->ecc_mode = NAND_ECC_NONE; + if (!strncmp("soft", mode, 4)) + pdata->ecc_mode = NAND_ECC_SOFT; + if (!strncmp("hw", mode, 2)) + pdata->ecc_mode = NAND_ECC_HW; + } + if (!of_property_read_u32(pdev->dev.of_node, + "ti,davinci-ecc-bits", &prop)) + pdata->ecc_bits = prop; + if (!of_property_read_u32(pdev->dev.of_node, + "ti,davinci-nand-buswidth", &prop)) + if (prop == 16) + pdata->options |= NAND_BUSWIDTH_16; + if (of_find_property(pdev->dev.of_node, + "ti,davinci-nand-use-bbt", &len)) + pdata->bbt_options = NAND_BBT_USE_FLASH; + } + + return pdev->dev.platform_data; +} +#else +#define davinci_nand_of_match NULL +static struct davinci_nand_pdata + *nand_davinci_get_pdata(struct platform_device *pdev) +{ + return pdev->dev.platform_data; +} +#endif + static int __init nand_davinci_probe(struct platform_device *pdev) { - struct davinci_nand_pdata *pdata = pdev->dev.platform_data; + struct davinci_nand_pdata *pdata; struct davinci_nand_info *info; struct resource *res1; struct resource *res2; @@ -530,6 +597,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) uint32_t val; nand_ecc_modes_t ecc_mode; + pdata = nand_davinci_get_pdata(pdev); /* insist on board-specific configuration */ if (!pdata) return -ENODEV; @@ -816,6 +884,8 @@ static struct platform_driver nand_davinci_driver = { .remove = __exit_p(nand_davinci_remove), .driver = { .name = "davinci_nand", + .owner = THIS_MODULE, + .of_match_table = davinci_nand_of_match, }, }; MODULE_ALIAS("platform:davinci_nand"); -- cgit v1.2.3 From 513d57e1db53870cdc11e60df77c57c8b3897fdf Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 17 Jul 2012 14:14:02 +0800 Subject: mtd: gpmi: fix the compiler warnings Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 4 ++-- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 20 ++++++++------------ drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 4 ++-- 3 files changed, 12 insertions(+), 16 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 6bb0998dcb40..2289cf8dc35b 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -26,7 +26,7 @@ #include "gpmi-regs.h" #include "bch-regs.h" -struct timing_threshod timing_default_threshold = { +static struct timing_threshod timing_default_threshold = { .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> BP_GPMI_TIMING0_DATA_SETUP), .internal_data_setup_in_ns = 0, @@ -738,7 +738,7 @@ void gpmi_begin(struct gpmi_nand_data *this) { struct resources *r = &this->resources; struct timing_threshod *nfc = &timing_default_threshold; - unsigned char *gpmi_regs = r->gpmi_regs; + void __iomem *gpmi_regs = r->gpmi_regs; unsigned int clock_period_in_ns; uint32_t reg; unsigned int dll_wait_time_in_us; diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0a526f..c46be6c8b2c4 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -317,7 +317,7 @@ acquire_register_block(struct gpmi_nand_data *this, const char *res_name) struct platform_device *pdev = this->pdev; struct resources *res = &this->resources; struct resource *r; - void *p; + void __iomem *p; r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name); if (!r) { @@ -424,8 +424,8 @@ static int __devinit acquire_dma_channels(struct gpmi_nand_data *this) struct platform_device *pdev = this->pdev; struct resource *r_dma; struct device_node *dn; - int dma_channel; - unsigned int ret; + u32 dma_channel; + int ret; struct dma_chan *dma_chan; dma_cap_mask_t mask; @@ -732,12 +732,12 @@ static int gpmi_alloc_dma_buffer(struct gpmi_nand_data *this) struct device *dev = this->dev; /* [1] Allocate a command buffer. PAGE_SIZE is enough. */ - this->cmd_buffer = kzalloc(PAGE_SIZE, GFP_DMA); + this->cmd_buffer = kzalloc(PAGE_SIZE, GFP_DMA | GFP_KERNEL); if (this->cmd_buffer == NULL) goto error_alloc; /* [2] Allocate a read/write data buffer. PAGE_SIZE is enough. */ - this->data_buffer_dma = kzalloc(PAGE_SIZE, GFP_DMA); + this->data_buffer_dma = kzalloc(PAGE_SIZE, GFP_DMA | GFP_KERNEL); if (this->data_buffer_dma == NULL) goto error_alloc; @@ -1260,7 +1260,6 @@ static int mx23_check_transcription_stamp(struct gpmi_nand_data *this) unsigned int search_area_size_in_strides; unsigned int stride; unsigned int page; - loff_t byte; uint8_t *buffer = chip->buffers->databuf; int saved_chip_number; int found_an_ncb_fingerprint = false; @@ -1277,9 +1276,8 @@ static int mx23_check_transcription_stamp(struct gpmi_nand_data *this) dev_dbg(dev, "Scanning for an NCB fingerprint...\n"); for (stride = 0; stride < search_area_size_in_strides; stride++) { - /* Compute the page and byte addresses. */ + /* Compute the page addresses. */ page = stride * rom_geo->stride_size_in_pages; - byte = page * mtd->writesize; dev_dbg(dev, "Looking for a fingerprint in page 0x%x\n", page); @@ -1321,7 +1319,6 @@ static int mx23_write_transcription_stamp(struct gpmi_nand_data *this) unsigned int block; unsigned int stride; unsigned int page; - loff_t byte; uint8_t *buffer = chip->buffers->databuf; int saved_chip_number; int status; @@ -1370,9 +1367,8 @@ static int mx23_write_transcription_stamp(struct gpmi_nand_data *this) /* Loop through the first search area, writing NCB fingerprints. */ dev_dbg(dev, "Writing NCB fingerprints...\n"); for (stride = 0; stride < search_area_size_in_strides; stride++) { - /* Compute the page and byte addresses. */ + /* Compute the page addresses. */ page = stride * rom_geo->stride_size_in_pages; - byte = page * mtd->writesize; /* Write the first page of the current stride. */ dev_dbg(dev, "Writing an NCB fingerprint in page 0x%x\n", page); @@ -1527,7 +1523,7 @@ static int gpmi_scan_bbt(struct mtd_info *mtd) return nand_default_bbt(mtd); } -void gpmi_nfc_exit(struct gpmi_nand_data *this) +static void gpmi_nfc_exit(struct gpmi_nand_data *this) { nand_release(&this->mtd); gpmi_free_dma_buffer(this); diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1547a60c1c6f..1f6121782330 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -24,8 +24,8 @@ #define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */ struct resources { - void *gpmi_regs; - void *bch_regs; + void __iomem *gpmi_regs; + void __iomem *bch_regs; unsigned int bch_low_interrupt; unsigned int bch_high_interrupt; unsigned int dma_low_channel; -- cgit v1.2.3 From 13e859745cf8cf0e6602759b1ef2abcb9ced7991 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 2 Aug 2012 16:06:47 +0300 Subject: mtd: use %*ph[CN] to dump small buffers There is new format specified that helps to dump small buffers. It makes the code simpler and nicer. Signed-off-by: Andy Shevchenko Acked-by: Jiandong Zheng Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/bcm_umi_bch.c | 17 ++++------------- drivers/mtd/nand/s3c2410.c | 12 ++++-------- 2 files changed, 8 insertions(+), 21 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c index c8799a001833..ce39c8705d62 100644 --- a/drivers/mtd/nand/bcm_umi_bch.c +++ b/drivers/mtd/nand/bcm_umi_bch.c @@ -154,19 +154,10 @@ static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd, #if defined(NAND_BCM_UMI_DEBUG) printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n", __func__, sectorIdx); - printk(KERN_WARNING - "%s data %02x %02x %02x %02x " - "%02x %02x %02x %02x\n", - __func__, datap[0], datap[1], datap[2], datap[3], - datap[4], datap[5], datap[6], datap[7]); - printk(KERN_WARNING - "%s ecc %02x %02x %02x %02x " - "%02x %02x %02x %02x %02x %02x " - "%02x %02x %02x\n", - __func__, eccCalc[0], eccCalc[1], eccCalc[2], - eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6], - eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10], - eccCalc[11], eccCalc[12]); + printk(KERN_WARNING "%s data %*ph\n", + __func__, 8, datap); + printk(KERN_WARNING "%s ecc %*ph\n", + __func__, 13, eccCalc); BUG(); #endif mtd->ecc_stats.failed++; diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index e71f7a951bf0..8ae9399fb4c8 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -457,10 +457,8 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, diff1 = read_ecc[1] ^ calc_ecc[1]; diff2 = read_ecc[2] ^ calc_ecc[2]; - pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", - __func__, - read_ecc[0], read_ecc[1], read_ecc[2], - calc_ecc[0], calc_ecc[1], calc_ecc[2], + pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", + __func__, 3, read_ecc, 3, calc_ecc, diff0, diff1, diff2); if (diff0 == 0 && diff1 == 0 && diff2 == 0) @@ -562,8 +560,7 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); - pr_debug("%s: returning ecc %02x%02x%02x\n", __func__, - ecc_code[0], ecc_code[1], ecc_code[2]); + pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); return 0; } @@ -578,8 +575,7 @@ static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, ecc_code[1] = ecc >> 8; ecc_code[2] = ecc >> 16; - pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", - ecc_code[0], ecc_code[1], ecc_code[2]); + pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); return 0; } -- cgit v1.2.3 From 657f28f8811c92724db10d18bbbec70d540147d6 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 14 Aug 2012 22:38:45 -0400 Subject: mtd: kill MTD_NAND_VERIFY_WRITE Just as Artem suggested: "Both UBI and JFFS2 are able to read verify what they wrote already. There are also MTD tests which do this verification. So I think there is no reason to keep this in the NAND layer, let alone wasting RAM in the driver to support this feature. Besides, it does not work for sub-pages and many drivers have it broken. It hurts more than it provides benefits." So kill MTD_NAND_VERIFY_WRITE entirely. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 9 ------ drivers/mtd/nand/ams-delta.c | 13 --------- drivers/mtd/nand/au1550nd.c | 46 ----------------------------- drivers/mtd/nand/bcm_umi_nand.c | 22 -------------- drivers/mtd/nand/cafe_nand.c | 7 ----- drivers/mtd/nand/cmx270_nand.c | 13 --------- drivers/mtd/nand/diskonchip.c | 63 ---------------------------------------- drivers/mtd/nand/fsl_elbc_nand.c | 36 ----------------------- drivers/mtd/nand/fsl_ifc_nand.c | 41 -------------------------- drivers/mtd/nand/gpio.c | 39 ------------------------- drivers/mtd/nand/lpc32xx_slc.c | 19 ------------ drivers/mtd/nand/mpc5121_nfc.c | 22 -------------- drivers/mtd/nand/mxc_nand.c | 9 ------ drivers/mtd/nand/nand_base.c | 53 --------------------------------- drivers/mtd/nand/nandsim.c | 16 ---------- drivers/mtd/nand/ndfc.c | 13 --------- drivers/mtd/nand/nuc900_nand.c | 17 ----------- drivers/mtd/nand/omap2.c | 23 --------------- drivers/mtd/nand/pxa3xx_nand.c | 7 ----- drivers/mtd/nand/r852.c | 22 -------------- drivers/mtd/nand/sh_flctl.c | 11 ------- drivers/mtd/nand/socrates_nand.c | 19 ------------ drivers/mtd/nand/tmio_nand.c | 13 --------- drivers/mtd/nand/txx9ndfmc.c | 13 --------- 24 files changed, 546 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 5708d3b28a98..7101e8a03259 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -22,15 +22,6 @@ menuconfig MTD_NAND if MTD_NAND -config MTD_NAND_VERIFY_WRITE - bool "Verify NAND page writes" - help - This adds an extra check when data is written to the flash. The - NAND flash device internally checks only bits transitioning - from 1 to 0. There is a rare possibility that even though the - device thinks the write was successful, a bit could have been - flipped accidentally due to device wear or something else. - config MTD_NAND_BCH tristate select BCH diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c index 861ca8f7e47d..2d73f2393586 100644 --- a/drivers/mtd/nand/ams-delta.c +++ b/drivers/mtd/nand/ams-delta.c @@ -103,18 +103,6 @@ static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len) buf[i] = ams_delta_read_byte(mtd); } -static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf, - int len) -{ - int i; - - for (i=0; iread_byte = ams_delta_read_byte; this->write_buf = ams_delta_write_buf; this->read_buf = ams_delta_read_buf; - this->verify_buf = ams_delta_verify_buf; this->cmd_ctrl = ams_delta_hwcontrol; if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) { this->dev_ready = ams_delta_nand_ready; diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 9f609d2dcf62..5c47b200045a 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -140,28 +140,6 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } -/** - * au_verify_buf - Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * verify function for 8bit buswidth - */ -static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) { - if (buf[i] != readb(this->IO_ADDR_R)) - return -EFAULT; - au_sync(); - } - - return 0; -} - /** * au_write_buf16 - write buffer to chip * @mtd: MTD device structure @@ -205,29 +183,6 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) } } -/** - * au_verify_buf16 - Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * verify function for 16bit buswidth - */ -static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - u16 *p = (u16 *) buf; - len >>= 1; - - for (i = 0; i < len; i++) { - if (p[i] != readw(this->IO_ADDR_R)) - return -EFAULT; - au_sync(); - } - return 0; -} - /* Select the chip by setting nCE to low */ #define NAND_CTL_SETNCE 1 /* Deselect the chip by setting nCE to high */ @@ -516,7 +471,6 @@ static int __devinit au1550nd_probe(struct platform_device *pdev) this->read_word = au_read_word; this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf; this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf; - this->verify_buf = (pd->devwidth) ? au_verify_buf16 : au_verify_buf; ret = nand_scan(&ctx->info, 1); if (ret) { diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c index c855e7cd337b..3fcbcbc7b082 100644 --- a/drivers/mtd/nand/bcm_umi_nand.c +++ b/drivers/mtd/nand/bcm_umi_nand.c @@ -332,27 +332,6 @@ static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) #endif } -static uint8_t readbackbuf[NAND_MAX_PAGESIZE]; -static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, - int len) -{ - /* - * Try to readback page with ECC correction. This is necessary - * for MLC parts which may have permanently stuck bits. - */ - struct nand_chip *chip = mtd->priv; - int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0); - if (ret < 0) - return -EFAULT; - else { - if (memcmp(readbackbuf, buf, len) == 0) - return 0; - - return -EFAULT; - } - return 0; -} - static int __devinit bcm_umi_nand_probe(struct platform_device *pdev) { struct nand_chip *this; @@ -416,7 +395,6 @@ static int __devinit bcm_umi_nand_probe(struct platform_device *pdev) this->write_buf = bcm_umi_nand_write_buf; this->read_buf = bcm_umi_nand_read_buf; - this->verify_buf = bcm_umi_nand_verify_buf; this->cmd_ctrl = bcm_umi_nand_hwcontrol; this->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c index 08248a0a167e..2bb7170502c2 100644 --- a/drivers/mtd/nand/cafe_nand.c +++ b/drivers/mtd/nand/cafe_nand.c @@ -576,13 +576,6 @@ static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, status = chip->waitfunc(mtd, chip); } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - /* Send command to read back the data */ - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - - if (chip->verify_buf(mtd, buf, mtd->writesize)) - return -EIO; -#endif return 0; } diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c index 1024bfc05c86..39b2ef848811 100644 --- a/drivers/mtd/nand/cmx270_nand.c +++ b/drivers/mtd/nand/cmx270_nand.c @@ -76,18 +76,6 @@ static void cmx270_read_buf(struct mtd_info *mtd, u_char *buf, int len) *buf++ = readl(this->IO_ADDR_R) >> 16; } -static int cmx270_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i=0; iIO_ADDR_R) >> 16)) - return -EFAULT; - - return 0; -} - static inline void nand_cs_on(void) { gpio_set_value(GPIO_NAND_CS, 0); @@ -209,7 +197,6 @@ static int __init cmx270_init(void) this->read_byte = cmx270_read_byte; this->read_buf = cmx270_read_buf; this->write_buf = cmx270_write_buf; - this->verify_buf = cmx270_verify_buf; /* Scan to find existence of the device */ if (nand_scan (cmx270_nand_mtd, 1)) { diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c index e2ca067631cf..256eb30f6180 100644 --- a/drivers/mtd/nand/diskonchip.c +++ b/drivers/mtd/nand/diskonchip.c @@ -376,19 +376,6 @@ static void doc2000_readbuf_dword(struct mtd_info *mtd, u_char *buf, int len) } } -static int doc2000_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - for (i = 0; i < len; i++) - if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO)) - return -EFAULT; - return 0; -} - static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr) { struct nand_chip *this = mtd->priv; @@ -526,26 +513,6 @@ static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len) buf[i] = ReadDOC(docptr, LastDataRead); } -static int doc2001_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - /* Start read pipeline */ - ReadDOC(docptr, ReadPipeInit); - - for (i = 0; i < len - 1; i++) - if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { - ReadDOC(docptr, LastDataRead); - return i; - } - if (buf[i] != ReadDOC(docptr, LastDataRead)) - return i; - return 0; -} - static u_char doc2001plus_read_byte(struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; @@ -610,33 +577,6 @@ static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len) printk("\n"); } -static int doc2001plus_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("verifybuf of %d bytes: ", len); - - /* Start read pipeline */ - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - - for (i = 0; i < len - 2; i++) - if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { - ReadDOC(docptr, Mplus_LastDataRead); - ReadDOC(docptr, Mplus_LastDataRead); - return i; - } - if (buf[len - 2] != ReadDOC(docptr, Mplus_LastDataRead)) - return len - 2; - if (buf[len - 1] != ReadDOC(docptr, Mplus_LastDataRead)) - return len - 1; - return 0; -} - static void doc2001plus_select_chip(struct mtd_info *mtd, int chip) { struct nand_chip *this = mtd->priv; @@ -1432,7 +1372,6 @@ static inline int __init doc2000_init(struct mtd_info *mtd) this->read_byte = doc2000_read_byte; this->write_buf = doc2000_writebuf; this->read_buf = doc2000_readbuf; - this->verify_buf = doc2000_verifybuf; this->scan_bbt = nftl_scan_bbt; doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO; @@ -1449,7 +1388,6 @@ static inline int __init doc2001_init(struct mtd_info *mtd) this->read_byte = doc2001_read_byte; this->write_buf = doc2001_writebuf; this->read_buf = doc2001_readbuf; - this->verify_buf = doc2001_verifybuf; ReadDOC(doc->virtadr, ChipID); ReadDOC(doc->virtadr, ChipID); @@ -1480,7 +1418,6 @@ static inline int __init doc2001plus_init(struct mtd_info *mtd) this->read_byte = doc2001plus_read_byte; this->write_buf = doc2001plus_writebuf; this->read_buf = doc2001plus_readbuf; - this->verify_buf = doc2001plus_verifybuf; this->scan_bbt = inftl_scan_bbt; this->cmd_ctrl = NULL; this->select_chip = doc2001plus_select_chip; diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 8143873d17a5..cc1480a5e4c1 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -614,41 +614,6 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) len, avail); } -/* - * Verify buffer against the FCM Controller Data Buffer - */ -static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; - struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; - int i; - - if (len < 0) { - dev_err(priv->dev, "write_buf of %d bytes", len); - return -EINVAL; - } - - if ((unsigned int)len > - elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) { - dev_err(priv->dev, - "verify_buf beyond end of buffer " - "(%d requested, %u available)\n", - len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); - - elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes; - return -EINVAL; - } - - for (i = 0; i < len; i++) - if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i]) - != buf[i]) - break; - - elbc_fcm_ctrl->index += len; - return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO; -} - /* This function is called after Program and Erase Operations to * check for success or failure. */ @@ -798,7 +763,6 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) chip->read_byte = fsl_elbc_read_byte; chip->write_buf = fsl_elbc_write_buf; chip->read_buf = fsl_elbc_read_buf; - chip->verify_buf = fsl_elbc_verify_buf; chip->select_chip = fsl_elbc_select_chip; chip->cmdfunc = fsl_elbc_cmdfunc; chip->waitfunc = fsl_elbc_wait; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 1f71b545062a..e92d223e5e1a 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -626,46 +626,6 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) __func__, len, avail); } -/* - * Verify buffer against the IFC Controller Data Buffer - */ -static int fsl_ifc_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; - struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; - int i; - - if (len < 0) { - dev_err(priv->dev, "%s: write_buf of %d bytes", __func__, len); - return -EINVAL; - } - - if ((unsigned int)len > nctrl->read_bytes - nctrl->index) { - dev_err(priv->dev, - "%s: beyond end of buffer (%d requested, %u available)\n", - __func__, len, nctrl->read_bytes - nctrl->index); - - nctrl->index = nctrl->read_bytes; - return -EINVAL; - } - - for (i = 0; i < len; i++) - if (in_8(&nctrl->addr[nctrl->index + i]) != buf[i]) - break; - - nctrl->index += len; - - if (i != len) - return -EIO; - if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) - return -EIO; - - return 0; -} - /* * This function is called after Program and Erase Operations to * check for success or failure. @@ -796,7 +756,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) chip->write_buf = fsl_ifc_write_buf; chip->read_buf = fsl_ifc_read_buf; - chip->verify_buf = fsl_ifc_verify_buf; chip->select_chip = fsl_ifc_select_chip; chip->cmdfunc = fsl_ifc_cmdfunc; chip->waitfunc = fsl_ifc_wait; diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c index 27000a5f5f47..ce6a284c8277 100644 --- a/drivers/mtd/nand/gpio.c +++ b/drivers/mtd/nand/gpio.c @@ -100,23 +100,6 @@ static void gpio_nand_readbuf(struct mtd_info *mtd, u_char *buf, int len) readsb(this->IO_ADDR_R, buf, len); } -static int gpio_nand_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - unsigned char read, *p = (unsigned char *) buf; - int i, err = 0; - - for (i = 0; i < len; i++) { - read = readb(this->IO_ADDR_R); - if (read != p[i]) { - pr_debug("%s: err at %d (read %04x vs %04x)\n", - __func__, i, read, p[i]); - err = -EFAULT; - } - } - return err; -} - static void gpio_nand_writebuf16(struct mtd_info *mtd, const u_char *buf, int len) { @@ -148,26 +131,6 @@ static void gpio_nand_readbuf16(struct mtd_info *mtd, u_char *buf, int len) } } -static int gpio_nand_verifybuf16(struct mtd_info *mtd, const u_char *buf, - int len) -{ - struct nand_chip *this = mtd->priv; - unsigned short read, *p = (unsigned short *) buf; - int i, err = 0; - len >>= 1; - - for (i = 0; i < len; i++) { - read = readw(this->IO_ADDR_R); - if (read != p[i]) { - pr_debug("%s: err at %d (read %04x vs %04x)\n", - __func__, i, read, p[i]); - err = -EFAULT; - } - } - return err; -} - - static int gpio_nand_devready(struct mtd_info *mtd) { struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd); @@ -391,11 +354,9 @@ static int __devinit gpio_nand_probe(struct platform_device *dev) if (this->options & NAND_BUSWIDTH_16) { this->read_buf = gpio_nand_readbuf16; this->write_buf = gpio_nand_writebuf16; - this->verify_buf = gpio_nand_verifybuf16; } else { this->read_buf = gpio_nand_readbuf; this->write_buf = gpio_nand_writebuf; - this->verify_buf = gpio_nand_verifybuf; } /* set the mtd private data for the nand driver */ diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 184035045208..9326e5994b26 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -368,24 +368,6 @@ static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int writel((uint32_t)*buf++, SLC_DATA(host->io_base)); } -/* - * Verify data in buffer to data on device - */ -static int lpc32xx_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct lpc32xx_nand_host *host = chip->priv; - int i; - - /* DATA register must be read as 32 bits or it will fail */ - for (i = 0; i < len; i++) { - if (buf[i] != (uint8_t)readl(SLC_DATA(host->io_base))) - return -EFAULT; - } - - return 0; -} - /* * Read the OOB data from the device without ECC using FIFO method */ @@ -871,7 +853,6 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) chip->ecc.correct = nand_correct_data; chip->ecc.strength = 1; chip->ecc.hwctl = lpc32xx_nand_ecc_enable; - chip->verify_buf = lpc32xx_verify_buf; /* bitflip_threshold's default is defined as ecc_strength anyway. * Unfortunately, it is set only later at add_mtd_device(). Meanwhile diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index c259c24d7986..f776c8577b8c 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -506,27 +506,6 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd, mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1); } -/* Compare buffer with NAND flash */ -static int mpc5121_nfc_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - u_char tmp[256]; - uint bsize; - - while (len) { - bsize = min(len, 256); - mpc5121_nfc_read_buf(mtd, tmp, bsize); - - if (memcmp(buf, tmp, bsize)) - return 1; - - buf += bsize; - len -= bsize; - } - - return 0; -} - /* Read byte from NFC buffers */ static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd) { @@ -732,7 +711,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op) chip->read_word = mpc5121_nfc_read_word; chip->read_buf = mpc5121_nfc_read_buf; chip->write_buf = mpc5121_nfc_write_buf; - chip->verify_buf = mpc5121_nfc_verify_buf; chip->select_chip = mpc5121_nfc_select_chip; chip->bbt_options = NAND_BBT_USE_FLASH; chip->ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 3f94e1f13231..bfee9ebf9ab9 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -746,14 +746,6 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) host->buf_start += n; } -/* Used by the upper layer to verify the data in NAND Flash - * with the data in the buf. */ -static int mxc_nand_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - return -EFAULT; -} - /* This function is used by upper layer for select and * deselect of the NAND chip */ static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) @@ -1406,7 +1398,6 @@ static int __init mxcnd_probe(struct platform_device *pdev) this->read_word = mxc_nand_read_word; this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; - this->verify_buf = mxc_nand_verify_buf; host->clk = devm_clk_get(&pdev->dev, "nfc"); if (IS_ERR(host->clk)) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 996cc4836885..6a8e15d6b402 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -242,25 +242,6 @@ static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) buf[i] = readb(chip->IO_ADDR_R); } -/** - * nand_verify_buf - [DEFAULT] Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * Default verify function for 8bit buswidth. - */ -static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - - for (i = 0; i < len; i++) - if (buf[i] != readb(chip->IO_ADDR_R)) - return -EFAULT; - return 0; -} - /** * nand_write_buf16 - [DEFAULT] write buffer to chip * @mtd: MTD device structure @@ -300,28 +281,6 @@ static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) p[i] = readw(chip->IO_ADDR_R); } -/** - * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * Default verify function for 16bit buswidth. - */ -static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - u16 *p = (u16 *) buf; - len >>= 1; - - for (i = 0; i < len; i++) - if (p[i] != readw(chip->IO_ADDR_R)) - return -EFAULT; - - return 0; -} - /** * nand_block_bad - [DEFAULT] Read bad block marker from the chip * @mtd: MTD device structure @@ -2120,16 +2079,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, status = chip->waitfunc(mtd, chip); } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - /* Send command to read back the data */ - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - - if (chip->verify_buf(mtd, buf, mtd->writesize)) - return -EIO; - - /* Make sure the next page prog is preceded by a status read */ - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); -#endif return 0; } @@ -2804,8 +2753,6 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; if (!chip->read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; - if (!chip->verify_buf) - chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c index cf0cd3146817..21e64b5d352b 100644 --- a/drivers/mtd/nand/nandsim.c +++ b/drivers/mtd/nand/nandsim.c @@ -447,8 +447,6 @@ static unsigned int rptwear_cnt = 0; /* MTD structure for NAND controller */ static struct mtd_info *nsmtd; -static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE]; - /* * Allocate array of page pointers, create slab allocation for an array * and initialize the array by NULL pointers. @@ -2189,19 +2187,6 @@ static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) return; } -static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len); - - if (!memcmp(buf, &ns_verify_buf[0], len)) { - NS_DBG("verify_buf: the buffer is OK\n"); - return 0; - } else { - NS_DBG("verify_buf: the buffer is wrong\n"); - return -EFAULT; - } -} - /* * Module initialization function */ @@ -2236,7 +2221,6 @@ static int __init ns_init_module(void) chip->dev_ready = ns_device_ready; chip->write_buf = ns_nand_write_buf; chip->read_buf = ns_nand_read_buf; - chip->verify_buf = ns_nand_verify_buf; chip->read_word = ns_nand_read_word; chip->ecc.mode = NAND_ECC_SOFT; /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */ diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 2b6f632cf274..5fd3f010e3ae 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -140,18 +140,6 @@ static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); } -static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct ndfc_controller *ndfc = chip->priv; - uint32_t *p = (uint32_t *) buf; - - for(;len > 0; len -= 4) - if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA)) - return -EFAULT; - return 0; -} - /* * Initialize chip structure */ @@ -172,7 +160,6 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc, chip->controller = &ndfc->ndfc_control; chip->read_buf = ndfc_read_buf; chip->write_buf = ndfc_write_buf; - chip->verify_buf = ndfc_verify_buf; chip->ecc.correct = nand_correct_data; chip->ecc.hwctl = ndfc_enable_hwecc; chip->ecc.calculate = ndfc_calculate_ecc; diff --git a/drivers/mtd/nand/nuc900_nand.c b/drivers/mtd/nand/nuc900_nand.c index 8febe46e1105..94dc46bc118c 100644 --- a/drivers/mtd/nand/nuc900_nand.c +++ b/drivers/mtd/nand/nuc900_nand.c @@ -112,22 +112,6 @@ static void nuc900_nand_write_buf(struct mtd_info *mtd, write_data_reg(nand, buf[i]); } -static int nuc900_verify_buf(struct mtd_info *mtd, - const unsigned char *buf, int len) -{ - int i; - struct nuc900_nand *nand; - - nand = container_of(mtd, struct nuc900_nand, mtd); - - for (i = 0; i < len; i++) { - if (buf[i] != (unsigned char)read_data_reg(nand)) - return -EFAULT; - } - - return 0; -} - static int nuc900_check_rb(struct nuc900_nand *nand) { unsigned int val; @@ -292,7 +276,6 @@ static int __devinit nuc900_nand_probe(struct platform_device *pdev) chip->read_byte = nuc900_nand_read_byte; chip->write_buf = nuc900_nand_write_buf; chip->read_buf = nuc900_nand_read_buf; - chip->verify_buf = nuc900_verify_buf; chip->chip_delay = 50; chip->options = 0; chip->ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 1ede9fb43430..f47c422c7dfd 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -613,27 +613,6 @@ out_copy: omap_write_buf8(mtd, buf, len); } -/** - * omap_verify_buf - Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - */ -static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) -{ - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, - mtd); - u16 *p = (u16 *) buf; - - len >>= 1; - while (len--) { - if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R))) - return -EFAULT; - } - - return 0; -} - /** * gen_true_ecc - This function will generate true ECC value * @ecc_buf: buffer to store ecc code @@ -1285,8 +1264,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) goto out_release_mem_region; } - info->nand.verify_buf = omap_verify_buf; - /* select the ecc type */ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) info->nand.ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index e8a1ae97a952..5df91d554dac 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -771,12 +771,6 @@ static void pxa3xx_nand_write_buf(struct mtd_info *mtd, info->buf_start += real_len; } -static int pxa3xx_nand_verify_buf(struct mtd_info *mtd, - const uint8_t *buf, int len) -{ - return 0; -} - static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) { return; @@ -1069,7 +1063,6 @@ static int alloc_nand_resource(struct platform_device *pdev) chip->read_byte = pxa3xx_nand_read_byte; chip->read_buf = pxa3xx_nand_read_buf; chip->write_buf = pxa3xx_nand_write_buf; - chip->verify_buf = pxa3xx_nand_verify_buf; } spin_lock_init(&chip->controller->lock); diff --git a/drivers/mtd/nand/r852.c b/drivers/mtd/nand/r852.c index 8cb627751c9c..4495f8551fa0 100644 --- a/drivers/mtd/nand/r852.c +++ b/drivers/mtd/nand/r852.c @@ -309,27 +309,6 @@ static uint8_t r852_read_byte(struct mtd_info *mtd) return r852_read_reg(dev, R852_DATALINE); } - -/* - * Readback the buffer to verify it - */ -int r852_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - struct r852_device *dev = r852_get_dev(mtd); - - /* We can't be sure about anything here... */ - if (dev->card_unstable) - return -1; - - /* This will never happen, unless you wired up a nand chip - with > 512 bytes page size to the reader */ - if (len > SM_SECTOR_SIZE) - return 0; - - r852_read_buf(mtd, dev->tmp_buffer, len); - return memcmp(buf, dev->tmp_buffer, len); -} - /* * Control several chip lines & send commands */ @@ -882,7 +861,6 @@ int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) chip->read_byte = r852_read_byte; chip->read_buf = r852_read_buf; chip->write_buf = r852_write_buf; - chip->verify_buf = r852_verify_buf; /* ecc */ chip->ecc.mode = NAND_ECC_HW_SYNDROME; diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 4ff8ef526c02..4fbfe96e37a1 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -786,16 +786,6 @@ static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) flctl->index += len; } -static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - if (buf[i] != flctl_read_byte(mtd)) - return -EFAULT; - return 0; -} - static int flctl_chip_init_tail(struct mtd_info *mtd) { struct sh_flctl *flctl = mtd_to_flctl(mtd); @@ -929,7 +919,6 @@ static int __devinit flctl_probe(struct platform_device *pdev) nand->read_byte = flctl_read_byte; nand->write_buf = flctl_write_buf; nand->read_buf = flctl_read_buf; - nand->verify_buf = flctl_verify_buf; nand->select_chip = flctl_select_chip; nand->cmdfunc = flctl_cmdfunc; diff --git a/drivers/mtd/nand/socrates_nand.c b/drivers/mtd/nand/socrates_nand.c index e02b08bcf0c0..f3f28fafbf7a 100644 --- a/drivers/mtd/nand/socrates_nand.c +++ b/drivers/mtd/nand/socrates_nand.c @@ -98,24 +98,6 @@ static uint16_t socrates_nand_read_word(struct mtd_info *mtd) return word; } -/** - * socrates_nand_verify_buf - Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - */ -static int socrates_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, - int len) -{ - int i; - - for (i = 0; i < len; i++) { - if (buf[i] != socrates_nand_read_byte(mtd)) - return -EFAULT; - } - return 0; -} - /* * Hardware specific access to control-lines */ @@ -201,7 +183,6 @@ static int __devinit socrates_nand_probe(struct platform_device *ofdev) nand_chip->read_word = socrates_nand_read_word; nand_chip->write_buf = socrates_nand_write_buf; nand_chip->read_buf = socrates_nand_read_buf; - nand_chip->verify_buf = socrates_nand_verify_buf; nand_chip->dev_ready = socrates_nand_device_ready; nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ diff --git a/drivers/mtd/nand/tmio_nand.c b/drivers/mtd/nand/tmio_nand.c index 5aa518081c51..508e9e04b092 100644 --- a/drivers/mtd/nand/tmio_nand.c +++ b/drivers/mtd/nand/tmio_nand.c @@ -256,18 +256,6 @@ static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); } -static int -tmio_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct tmio_nand *tmio = mtd_to_tmio(mtd); - u16 *p = (u16 *) buf; - - for (len >>= 1; len; len--) - if (*(p++) != tmio_ioread16(tmio->fcr + FCR_DATA)) - return -EFAULT; - return 0; -} - static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct tmio_nand *tmio = mtd_to_tmio(mtd); @@ -424,7 +412,6 @@ static int tmio_probe(struct platform_device *dev) nand_chip->read_byte = tmio_nand_read_byte; nand_chip->write_buf = tmio_nand_write_buf; nand_chip->read_buf = tmio_nand_read_buf; - nand_chip->verify_buf = tmio_nand_verify_buf; /* set eccmode using hardware ECC */ nand_chip->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c index 26398dcf21cf..e3d7266e256f 100644 --- a/drivers/mtd/nand/txx9ndfmc.c +++ b/drivers/mtd/nand/txx9ndfmc.c @@ -131,18 +131,6 @@ static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) *buf++ = __raw_readl(ndfdtr); } -static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, - int len) -{ - struct platform_device *dev = mtd_to_platdev(mtd); - void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); - - while (len--) - if (*buf++ != (uint8_t)__raw_readl(ndfdtr)) - return -EFAULT; - return 0; -} - static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { @@ -346,7 +334,6 @@ static int __init txx9ndfmc_probe(struct platform_device *dev) chip->read_byte = txx9ndfmc_read_byte; chip->read_buf = txx9ndfmc_read_buf; chip->write_buf = txx9ndfmc_write_buf; - chip->verify_buf = txx9ndfmc_verify_buf; chip->cmd_ctrl = txx9ndfmc_cmd_ctrl; chip->dev_ready = txx9ndfmc_dev_ready; chip->ecc.calculate = txx9ndfmc_calculate_ecc; -- cgit v1.2.3 From da3888cb84065a03d30b5f729b405e573bd0d66e Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 22 Jul 2012 08:59:57 +0200 Subject: mtd: check for valid pdata inside plat_nand If plat_nand loads and the platform_data is not properly set it will segfault. Signed-off-by: John Crispin Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/plat_nand.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c index 1bcb52040422..a47ee68a0cfa 100644 --- a/drivers/mtd/nand/plat_nand.c +++ b/drivers/mtd/nand/plat_nand.c @@ -37,6 +37,11 @@ static int __devinit plat_nand_probe(struct platform_device *pdev) const char **part_types; int err = 0; + if (!pdata) { + dev_err(&pdev->dev, "platform_nand_data is missing\n"); + return -EINVAL; + } + if (pdata->chip.nr_chips < 1) { dev_err(&pdev->dev, "invalid number of chips specified\n"); return -EINVAL; -- cgit v1.2.3 From 99f2b107924c07bee0bae7151426495fb815ca6e Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 23 Aug 2012 20:28:32 +0200 Subject: mtd: lantiq: Add NAND support on Lantiq XWAY SoC. The driver uses plat_nand. As the platform_device is loaded from DT, we need to lookup the node and attach our xway specific "struct platform_nand_data" to it. Signed-off-by: John Crispin Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 8 ++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/xway_nand.c | 201 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/mtd/nand/xway_nand.c (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 7101e8a03259..ce5cf020cd76 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -580,4 +580,12 @@ config MTD_NAND_FSMC Enables support for NAND Flash chips on the ST Microelectronics Flexible Static Memory Controller (FSMC) +config MTD_NAND_XWAY + tristate "Support for NAND on Lantiq XWAY SoC" + depends on LANTIQ && SOC_TYPE_XWAY + select MTD_NAND_PLATFORM + help + Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached + to the External Bus Unit (EBU). + endif # MTD_NAND diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index ddee81811b4a..c4b0ab316bab 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ +obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o nand-objs := nand_base.o nand_bbt.o diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c new file mode 100644 index 000000000000..3f81dc8f214c --- /dev/null +++ b/drivers/mtd/nand/xway_nand.c @@ -0,0 +1,201 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright © 2012 John Crispin + */ + +#include +#include +#include + +#include + +/* nand registers */ +#define EBU_ADDSEL1 0x24 +#define EBU_NAND_CON 0xB0 +#define EBU_NAND_WAIT 0xB4 +#define EBU_NAND_ECC0 0xB8 +#define EBU_NAND_ECC_AC 0xBC + +/* nand commands */ +#define NAND_CMD_ALE (1 << 2) +#define NAND_CMD_CLE (1 << 3) +#define NAND_CMD_CS (1 << 4) +#define NAND_WRITE_CMD_RESET 0xff +#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) +#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) +#define NAND_WRITE_DATA (NAND_CMD_CS) +#define NAND_READ_DATA (NAND_CMD_CS) +#define NAND_WAIT_WR_C (1 << 3) +#define NAND_WAIT_RD (0x1) + +/* we need to tel the ebu which addr we mapped the nand to */ +#define ADDSEL1_MASK(x) (x << 4) +#define ADDSEL1_REGEN 1 + +/* we need to tell the EBU that we have nand attached and set it up properly */ +#define BUSCON1_SETUP (1 << 22) +#define BUSCON1_BCGEN_RES (0x3 << 12) +#define BUSCON1_WAITWRC2 (2 << 8) +#define BUSCON1_WAITRDC2 (2 << 6) +#define BUSCON1_HOLDC1 (1 << 4) +#define BUSCON1_RECOVC1 (1 << 2) +#define BUSCON1_CMULT4 1 + +#define NAND_CON_CE (1 << 20) +#define NAND_CON_OUT_CS1 (1 << 10) +#define NAND_CON_IN_CS1 (1 << 8) +#define NAND_CON_PRE_P (1 << 7) +#define NAND_CON_WP_P (1 << 6) +#define NAND_CON_SE_P (1 << 5) +#define NAND_CON_CS_P (1 << 4) +#define NAND_CON_CSMUX (1 << 1) +#define NAND_CON_NANDM 1 + +static void xway_reset_chip(struct nand_chip *chip) +{ + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; + unsigned long flags; + + nandaddr &= ~NAND_WRITE_ADDR; + nandaddr |= NAND_WRITE_CMD; + + /* finish with a reset */ + spin_lock_irqsave(&ebu_lock, flags); + writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void xway_select_chip(struct mtd_info *mtd, int chip) +{ + + switch (chip) { + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); + break; + case 0: + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; + default: + BUG(); + } +} + +static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + unsigned long flags; + + if (ctrl & NAND_CTRL_CHANGE) { + nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR); + if (ctrl & NAND_CLE) + nandaddr |= NAND_WRITE_CMD; + else + nandaddr |= NAND_WRITE_ADDR; + this->IO_ADDR_W = (void __iomem *) nandaddr; + } + + if (cmd != NAND_CMD_NONE) { + spin_lock_irqsave(&ebu_lock, flags); + writeb(cmd, this->IO_ADDR_W); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + spin_unlock_irqrestore(&ebu_lock, flags); + } +} + +static int xway_dev_ready(struct mtd_info *mtd) +{ + return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; +} + +static unsigned char xway_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; + unsigned long flags; + int ret; + + spin_lock_irqsave(&ebu_lock, flags); + ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA)); + spin_unlock_irqrestore(&ebu_lock, flags); + + return ret; +} + +static int xway_nand_probe(struct platform_device *pdev) +{ + struct nand_chip *this = platform_get_drvdata(pdev); + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + const __be32 *cs = of_get_property(pdev->dev.of_node, + "lantiq,cs", NULL); + u32 cs_flag = 0; + + /* load our CS from the DT. Either we find a valid 1 or default to 0 */ + if (cs && (*cs == 1)) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); + + ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 + | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 + | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); + + ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P + | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P + | cs_flag, EBU_NAND_CON); + + /* finish with a reset */ + xway_reset_chip(this); + + return 0; +} + +/* allow users to override the partition in DT using the cmdline */ +static const char *part_probes[] = { "cmdlinepart", "ofpart", NULL }; + +static struct platform_nand_data xway_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 30, + .part_probe_types = part_probes, + }, + .ctrl = { + .probe = xway_nand_probe, + .cmd_ctrl = xway_cmd_ctrl, + .dev_ready = xway_dev_ready, + .select_chip = xway_select_chip, + .read_byte = xway_read_byte, + } +}; + +/* + * Try to find the node inside the DT. If it is available attach out + * platform_nand_data + */ +static int __init xway_register_nand(void) +{ + struct device_node *node; + struct platform_device *pdev; + + node = of_find_compatible_node(NULL, NULL, "lantiq,nand-xway"); + if (!node) + return -ENOENT; + pdev = of_find_device_by_node(node); + if (!pdev) + return -EINVAL; + pdev->dev.platform_data = &xway_nand_data; + of_node_put(node); + return 0; +} + +subsys_initcall(xway_register_nand); -- cgit v1.2.3 From 6f32a3e2853da194bd541fa107645d71c4eaaef9 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 21 Aug 2012 14:24:09 +0530 Subject: mtd: s3c2410: Use devm_* functions devm_* functions are device managed functions and make cleanup code simpler and smaller. devm_kzalloc, devm_clk_get and devm_request_and_ioremap functions are used. Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 47 ++++++++++------------------------------------ 1 file changed, 10 insertions(+), 37 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 8ae9399fb4c8..90a630a6f0b9 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -97,9 +97,8 @@ enum s3c_nand_clk_state { * @mtds: An array of MTD instances on this controoler. * @platform: The platform data for this board. * @device: The platform device we bound to. - * @area: The IO area resource that came from request_mem_region(). * @clk: The clock resource for this controller. - * @regs: The area mapped for the hardware registers described by @area. + * @regs: The area mapped for the hardware registers. * @sel_reg: Pointer to the register controlling the NAND selection. * @sel_bit: The bit in @sel_reg to select the NAND chip. * @mtd_count: The number of MTDs created from this controller. @@ -116,7 +115,6 @@ struct s3c2410_nand_info { /* device info */ struct device *device; - struct resource *area; struct clk *clk; void __iomem *regs; void __iomem *sel_reg; @@ -716,29 +714,12 @@ static int s3c24xx_nand_remove(struct platform_device *pdev) pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); nand_release(&ptr->mtd); } - - kfree(info->mtds); } /* free the common resources */ - if (!IS_ERR(info->clk)) { + if (!IS_ERR(info->clk)) s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); - clk_put(info->clk); - } - - if (info->regs != NULL) { - iounmap(info->regs); - info->regs = NULL; - } - - if (info->area != NULL) { - release_resource(info->area); - kfree(info->area); - info->area = NULL; - } - - kfree(info); return 0; } @@ -933,7 +914,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) pr_debug("s3c2410_nand_probe(%p)\n", pdev); - info = kzalloc(sizeof(*info), GFP_KERNEL); + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); if (info == NULL) { dev_err(&pdev->dev, "no memory for flash info\n"); err = -ENOMEM; @@ -947,7 +928,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) /* get the clock source and enable it */ - info->clk = clk_get(&pdev->dev, "nand"); + info->clk = devm_clk_get(&pdev->dev, "nand"); if (IS_ERR(info->clk)) { dev_err(&pdev->dev, "failed to get clock\n"); err = -ENOENT; @@ -959,22 +940,14 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) /* allocate and map the resource */ /* currently we assume we have the one resource */ - res = pdev->resource; + res = pdev->resource; size = resource_size(res); - info->area = request_mem_region(res->start, size, pdev->name); - - if (info->area == NULL) { - dev_err(&pdev->dev, "cannot reserve register region\n"); - err = -ENOENT; - goto exit_error; - } - - info->device = &pdev->dev; - info->platform = plat; - info->regs = ioremap(res->start, size); - info->cpu_type = cpu_type; + info->device = &pdev->dev; + info->platform = plat; + info->cpu_type = cpu_type; + info->regs = devm_request_and_ioremap(&pdev->dev, res); if (info->regs == NULL) { dev_err(&pdev->dev, "cannot reserve register region\n"); err = -EIO; @@ -997,7 +970,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) /* allocate our information */ size = nr_sets * sizeof(*info->mtds); - info->mtds = kzalloc(size, GFP_KERNEL); + info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); if (info->mtds == NULL) { dev_err(&pdev->dev, "failed to allocate mtd storage\n"); err = -ENOMEM; -- cgit v1.2.3 From 19da4158d33053c6e91e95ee0663d625b2d32a77 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 21 Aug 2012 14:24:10 +0530 Subject: mtd: s3c2410: Fix compiler warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following warnings: ‘s3c2410_nand_correct_data’ defined but not used [-Wunused-function] ‘s3c2410_nand_enable_hwecc’ defined but not used [-Wunused-function] ‘s3c2412_nand_enable_hwecc’ defined but not used [-Wunused-function] ‘s3c2440_nand_enable_hwecc’ defined but not used [-Wunused-function] ‘s3c2410_nand_calculate_ecc’ defined but not used [-Wunused-function] ‘s3c2412_nand_calculate_ecc’ defined but not used [-Wunused-function] ‘s3c2440_nand_calculate_ecc’ defined but not used [-Wunused-function] The above functions are called only when CONFIG_MTD_NAND_S3C2410_HWECC is defined. Thus making them conditional. Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/s3c2410.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 90a630a6f0b9..792cee846221 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -442,6 +442,7 @@ static int s3c2412_nand_devready(struct mtd_info *mtd) /* ECC handling functions */ +#ifdef CONFIG_MTD_NAND_S3C2410_HWECC static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { @@ -592,6 +593,7 @@ static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, return 0; } +#endif /* over-ride the standard functions for a little more speed. We can * use read/write block to move the data buffers to/from the controller -- cgit v1.2.3 From eceb84b1886acb38e618f3dfb51cd4e53f2ddb97 Mon Sep 17 00:00:00 2001 From: Shmulik Ladkani Date: Mon, 20 Aug 2012 16:29:15 +0300 Subject: mtd: nand: rename create_bbt()'s 'len' variable to 'numpages' Rename 'len' variable of create_bbt/scan_block_fast/scan_block_full to 'numpages', since it really means number of pages to scan when searching for the BBM (and not the byte length of the scan). Signed-off-by: Shmulik Ladkani Reviewed-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 9a5402e320bf..24b0a4c3c39f 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -401,7 +401,7 @@ static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Scan a given block full */ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd, loff_t offs, uint8_t *buf, size_t readlen, - int scanlen, int len) + int scanlen, int numpages) { int ret, j; @@ -410,7 +410,7 @@ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd, if (ret && !mtd_is_bitflip_or_eccerr(ret)) return ret; - for (j = 0; j < len; j++, buf += scanlen) { + for (j = 0; j < numpages; j++, buf += scanlen) { if (check_pattern(buf, scanlen, mtd->writesize, bd)) return 1; } @@ -419,7 +419,7 @@ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd, /* Scan a given block partially */ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd, - loff_t offs, uint8_t *buf, int len) + loff_t offs, uint8_t *buf, int numpages) { struct mtd_oob_ops ops; int j, ret; @@ -430,7 +430,7 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd, ops.datbuf = NULL; ops.mode = MTD_OPS_PLACE_OOB; - for (j = 0; j < len; j++) { + for (j = 0; j < numpages; j++) { /* * Read the full oob until read_oob is fixed to handle single * byte reads for 16 bit buswidth. @@ -463,7 +463,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) { struct nand_chip *this = mtd->priv; - int i, numblocks, len, scanlen; + int i, numblocks, numpages, scanlen; int startblock; loff_t from; size_t readlen; @@ -471,11 +471,11 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, pr_info("Scanning device for bad blocks\n"); if (bd->options & NAND_BBT_SCANALLPAGES) - len = 1 << (this->bbt_erase_shift - this->page_shift); + numpages = 1 << (this->bbt_erase_shift - this->page_shift); else if (bd->options & NAND_BBT_SCAN2NDPAGE) - len = 2; + numpages = 2; else - len = 1; + numpages = 1; if (!(bd->options & NAND_BBT_SCANEMPTY)) { /* We need only read few bytes from the OOB area */ @@ -484,7 +484,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, } else { /* Full page content should be read */ scanlen = mtd->writesize + mtd->oobsize; - readlen = len * mtd->writesize; + readlen = numpages * mtd->writesize; } if (chip == -1) { @@ -508,7 +508,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, } if (this->bbt_options & NAND_BBT_SCANLASTPAGE) - from += mtd->erasesize - (mtd->writesize * len); + from += mtd->erasesize - (mtd->writesize * numpages); for (i = startblock; i < numblocks;) { int ret; @@ -517,9 +517,9 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, if (bd->options & NAND_BBT_SCANALLPAGES) ret = scan_block_full(mtd, bd, from, buf, readlen, - scanlen, len); + scanlen, numpages); else - ret = scan_block_fast(mtd, bd, from, buf, len); + ret = scan_block_fast(mtd, bd, from, buf, numpages); if (ret < 0) return ret; -- cgit v1.2.3 From d159c4e5fb7b755b9f254768293da7737790ac5b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 28 Jul 2012 19:29:25 -0300 Subject: mtd: nand: nand_bbt: export nand_update_bbt When building MTD_NAND_GPMI_NAND as module, the following error shows up: ERROR: "nand_update_bbt" [drivers/mtd/nand/gpmi-nand/gpmi_nand.ko] undefined! Export nand_update_bbt to fix it. Signed-off-by: Fabio Estevam Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 24b0a4c3c39f..2f744dd90740 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -4,7 +4,7 @@ * Overview: * Bad block table support for the NAND driver * - * Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de) + * Copyright © 2004 Thomas Gleixner (tglx@linutronix.de) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -1404,3 +1404,4 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) EXPORT_SYMBOL(nand_scan_bbt); EXPORT_SYMBOL(nand_default_bbt); +EXPORT_SYMBOL_GPL(nand_update_bbt); -- cgit v1.2.3 From e1f5b3f6a8370a053326077b413c61026e3f710a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 28 Jul 2012 19:29:24 -0300 Subject: mtd: allow MTD_NAND_GPMI_NAND to be built as module Allow MTD_NAND_GPMI_NAND to be built as module. Signed-off-by: Fabio Estevam Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index ce5cf020cd76..6010b500f93d 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -452,7 +452,7 @@ config MTD_NAND_NANDSIM MTD nand layer. config MTD_NAND_GPMI_NAND - bool "GPMI NAND Flash Controller driver" + tristate "GPMI NAND Flash Controller driver" depends on MTD_NAND && MXS_DMA help Enables NAND Flash support for IMX23, IMX28 or IMX6. -- cgit v1.2.3 From 10594f67870e86aac361d75ee1e84535a33e1214 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Fri, 24 Aug 2012 15:06:51 +0200 Subject: mtd: lpc32xx_slc: Cleanup after DT-only conversion The LPC32xx's DT-only conversion of the SLC NAND driver makes NAND config via platform_data obsolete. Dropped by this patch. Further, the driver really needs CONFIG_OF, which is already reflected by the dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping CONFIG_OF ifdefs. There is still platform_data necessary to supply the dma_filter callback for the dma engine. This is a completely different data structure than the old platform_data for NAND config, so renaming some old "pdata" variable to "ncfg" to prevent confusion with the new platform data. Signed-off-by: Roland Stigge Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_slc.c | 52 +++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 31 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index 9326e5994b26..32409c45d479 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -719,45 +719,38 @@ static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) return 0; } -#ifdef CONFIG_OF static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) { - struct lpc32xx_nand_cfg_slc *pdata; + struct lpc32xx_nand_cfg_slc *ncfg; struct device_node *np = dev->of_node; - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - dev_err(dev, "could not allocate memory for platform data\n"); + ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); + if (!ncfg) { + dev_err(dev, "could not allocate memory for NAND config\n"); return NULL; } - of_property_read_u32(np, "nxp,wdr-clks", &pdata->wdr_clks); - of_property_read_u32(np, "nxp,wwidth", &pdata->wwidth); - of_property_read_u32(np, "nxp,whold", &pdata->whold); - of_property_read_u32(np, "nxp,wsetup", &pdata->wsetup); - of_property_read_u32(np, "nxp,rdr-clks", &pdata->rdr_clks); - of_property_read_u32(np, "nxp,rwidth", &pdata->rwidth); - of_property_read_u32(np, "nxp,rhold", &pdata->rhold); - of_property_read_u32(np, "nxp,rsetup", &pdata->rsetup); - - if (!pdata->wdr_clks || !pdata->wwidth || !pdata->whold || - !pdata->wsetup || !pdata->rdr_clks || !pdata->rwidth || - !pdata->rhold || !pdata->rsetup) { + of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks); + of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth); + of_property_read_u32(np, "nxp,whold", &ncfg->whold); + of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup); + of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks); + of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth); + of_property_read_u32(np, "nxp,rhold", &ncfg->rhold); + of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup); + + if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold || + !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth || + !ncfg->rhold || !ncfg->rsetup) { dev_err(dev, "chip parameters not specified correctly\n"); return NULL; } - pdata->use_bbt = of_get_nand_on_flash_bbt(np); - pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0); + ncfg->use_bbt = of_get_nand_on_flash_bbt(np); + ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); - return pdata; -} -#else -static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) -{ - return NULL; + return ncfg; } -#endif /* * Probe for NAND controller @@ -793,10 +786,9 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) if (pdev->dev.of_node) host->ncfg = lpc32xx_parse_dt(&pdev->dev); - else - host->ncfg = pdev->dev.platform_data; if (!host->ncfg) { - dev_err(&pdev->dev, "Missing platform data\n"); + dev_err(&pdev->dev, + "Missing or bad NAND config from device tree\n"); return -ENOENT; } if (host->ncfg->wp_gpio == -EPROBE_DEFER) @@ -1021,13 +1013,11 @@ static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) #define lpc32xx_nand_suspend NULL #endif -#if defined(CONFIG_OF) static const struct of_device_id lpc32xx_nand_match[] = { { .compatible = "nxp,lpc3220-slc" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); -#endif static struct platform_driver lpc32xx_nand_driver = { .probe = lpc32xx_nand_probe, -- cgit v1.2.3 From 62beee20b1a53ba633badc4b57c68d815c9f3e66 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Fri, 24 Aug 2012 15:06:52 +0200 Subject: mtd: lpc32xx_mlc: Cleanup after DT-only conversion The LPC32xx's DT-only conversion of the MLC NAND driver makes NAND config via platform_data obsolete. Dropped by this patch. Further, the driver really needs CONFIG_OF, which is already reflected by the dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping CONFIG_OF ifdefs. There is still platform_data necessary to supply the dma_filter callback for the dma engine. This is a completely different data structure than the old platform_data for NAND config, so renaming some old "pdata" variable to "ncfg" to prevent confusion with the new platform data. Signed-off-by: Roland Stigge Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/lpc32xx_mlc.c | 46 +++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 28 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/lpc32xx_mlc.c b/drivers/mtd/nand/lpc32xx_mlc.c index 5da31795b693..c29b7ac1f6af 100644 --- a/drivers/mtd/nand/lpc32xx_mlc.c +++ b/drivers/mtd/nand/lpc32xx_mlc.c @@ -621,43 +621,36 @@ out1: return -ENXIO; } -#ifdef CONFIG_OF static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) { - struct lpc32xx_nand_cfg_mlc *pdata; + struct lpc32xx_nand_cfg_mlc *ncfg; struct device_node *np = dev->of_node; - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) { + ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); + if (!ncfg) { dev_err(dev, "could not allocate memory for platform data\n"); return NULL; } - of_property_read_u32(np, "nxp,tcea-delay", &pdata->tcea_delay); - of_property_read_u32(np, "nxp,busy-delay", &pdata->busy_delay); - of_property_read_u32(np, "nxp,nand-ta", &pdata->nand_ta); - of_property_read_u32(np, "nxp,rd-high", &pdata->rd_high); - of_property_read_u32(np, "nxp,rd-low", &pdata->rd_low); - of_property_read_u32(np, "nxp,wr-high", &pdata->wr_high); - of_property_read_u32(np, "nxp,wr-low", &pdata->wr_low); - - if (!pdata->tcea_delay || !pdata->busy_delay || !pdata->nand_ta || - !pdata->rd_high || !pdata->rd_low || !pdata->wr_high || - !pdata->wr_low) { + of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay); + of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay); + of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta); + of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high); + of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low); + of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high); + of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low); + + if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta || + !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high || + !ncfg->wr_low) { dev_err(dev, "chip parameters not specified correctly\n"); return NULL; } - pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0); + ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); - return pdata; + return ncfg; } -#else -static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) -{ - return NULL; -} -#endif /* * Probe for NAND controller @@ -695,10 +688,9 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev) nand_chip = &host->nand_chip; if (pdev->dev.of_node) host->ncfg = lpc32xx_parse_dt(&pdev->dev); - else - host->ncfg = pdev->dev.platform_data; if (!host->ncfg) { - dev_err(&pdev->dev, "Missing platform data\n"); + dev_err(&pdev->dev, + "Missing or bad NAND config from device tree\n"); return -ENOENT; } if (host->ncfg->wp_gpio == -EPROBE_DEFER) @@ -907,13 +899,11 @@ static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) #define lpc32xx_nand_suspend NULL #endif -#if defined(CONFIG_OF) static const struct of_device_id lpc32xx_nand_match[] = { { .compatible = "nxp,lpc3220-mlc" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); -#endif static struct platform_driver lpc32xx_nand_driver = { .probe = lpc32xx_nand_probe, -- cgit v1.2.3 From 32098f6af02754b357ce303afd1bd00a470f906c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 28 Aug 2012 01:35:28 +0200 Subject: mtd: orion_nand: remove include Commit abcda1dc ('arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option') currently pending in linux-next will make the ARCH_MVEBU platform select PLAT_ORION, which means that now all Orion drivers can be enabled on ARCH_MVEBU. This works fine for most drivers, except for orion_nand, because it includes , but mach-mvebu does not have a mach/hardware.h header (it is considered as a deprecated practice). It turns out that the include in orion_nand is not necessary: the driver builds perfectly fine without it, so we simply get rid of it. Signed-off-by: Thomas Petazzoni Tested-by: Andrew Lunn Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/orion_nand.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index fc5a868c436e..9ee436d30932 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -21,7 +21,6 @@ #include #include #include -#include #include static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -- cgit v1.2.3 From a5ff4f102937a3492bca4a9ff0c341d78813414c Mon Sep 17 00:00:00 2001 From: Jeff Westfahl Date: Mon, 13 Aug 2012 16:35:30 -0500 Subject: mtd: nand: Added a device flag for subpage read support Added a NAND device flag for subpage read support. Previously this was hard coded based on large page and soft ECC. Updated base NAND driver to use the new subpage read flag if the NAND is large page and soft ECC. Signed-off-by: Jeff Westfahl Reviewed-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6a8e15d6b402..88f671cb96c7 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1484,7 +1484,8 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, oob_required, page); - else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) + else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && + !oob) ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); else @@ -1501,7 +1502,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, /* Transfer not aligned data */ if (!aligned) { - if (!NAND_SUBPAGE_READ(chip) && !oob && + if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && !(mtd->ecc_stats.failed - stats.failed) && (ops->mode != MTD_OPS_RAW)) { chip->pagebuf = realpage; @@ -3415,6 +3416,10 @@ int nand_scan_tail(struct mtd_info *mtd) /* Invalidate the pagebuffer reference */ chip->pagebuf = -1; + /* Large page NAND with SOFT_ECC should support subpage reads */ + if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) + chip->options |= NAND_SUBPAGE_READ; + /* Fill in remaining MTD driver data */ mtd->type = MTD_NANDFLASH; mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : -- cgit v1.2.3 From 7d9b110269253b1d5858cfa57d68dfc7bf50dd77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 31 Aug 2012 13:35:41 +0200 Subject: mtd: omap2: fix omap_nand_remove segfault MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not kfree() the mtd_info; it is handled in the mtd subsystem and already freed by nand_release(). Instead kfree() the struct omap_nand_info allocated in omap_nand_probe which was not freed before. This patch fixes following error when unloading the omap2 module: ---8<--- ~ $ rmmod omap2 ------------[ cut here ]------------ kernel BUG at mm/slab.c:3126! Internal error: Oops - BUG: 0 [#1] PREEMPT ARM Modules linked in: omap2(-) CPU: 0 Not tainted (3.6.0-rc3-00230-g155e36d-dirty #3) PC is at cache_free_debugcheck+0x2d4/0x36c LR is at kfree+0xc8/0x2ac pc : [] lr : [] psr: 200d0193 sp : c521fe08 ip : c0e8ef90 fp : c521fe5c r10: bf0001fc r9 : c521e000 r8 : c0d99c8c r7 : c661ebc0 r6 : c065d5a4 r5 : c65c4060 r4 : c78005c0 r3 : 00000000 r2 : 00001000 r1 : c65c4000 r0 : 00000001 Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c5387d Table: 86694019 DAC: 00000015 Process rmmod (pid: 549, stack limit = 0xc521e2f0) Stack: (0xc521fe08 to 0xc5220000) fe00: c008a874 c00bf44c c515c6d0 200d0193 c65c4860 c515c240 fe20: c521fe3c c521fe30 c008a9c0 c008a854 c521fe5c c65c4860 c78005c0 bf0001fc fe40: c780ff40 a00d0113 c521e000 00000000 c521fe84 c521fe60 c0112efc c01122d8 fe60: c65c4860 c0673778 c06737ac 00000000 00070013 00000000 c521fe9c c521fe88 fe80: bf0001fc c0112e40 c0673778 bf001ca8 c521feac c521fea0 c02ca11c bf0001ac fea0: c521fec4 c521feb0 c02c82c4 c02ca100 c0673778 bf001ca8 c521fee4 c521fec8 fec0: c02c8dd8 c02c8250 00000000 bf001ca8 bf001ca8 c0804ee0 c521ff04 c521fee8 fee0: c02c804c c02c8d20 bf001924 00000000 bf001ca8 c521e000 c521ff1c c521ff08 ff00: c02c950c c02c7fbc bf001d48 00000000 c521ff2c c521ff20 c02ca3a4 c02c94b8 ff20: c521ff3c c521ff30 bf001938 c02ca394 c521ffa4 c521ff40 c009beb4 bf001930 ff40: c521ff6c 70616d6f b6fe0032 c0014f84 70616d6f b6fe0032 00000081 60070010 ff60: c521ff84 c521ff70 c008e1f4 c00bf328 0001a004 70616d6f c521ff94 0021ff88 ff80: c008e368 0001a004 70616d6f b6fe0032 00000081 c0015028 00000000 c521ffa8 ffa0: c0014dc0 c009bcd0 0001a004 70616d6f bec2ab38 00000880 bec2ab38 00000880 ffc0: 0001a004 70616d6f b6fe0032 00000081 00000319 00000000 b6fe1000 00000000 ffe0: bec2ab30 bec2ab20 00019f00 b6f539c0 60070010 bec2ab38 aaaaaaaa aaaaaaaa Backtrace: [] (cache_free_debugcheck+0x0/0x36c) from [] (kfree+0xc8/0x2ac) [] (kfree+0x0/0x2ac) from [] (omap_nand_remove+0x5c/0x64 [omap2]) [] (omap_nand_remove+0x0/0x64 [omap2]) from [] (platform_drv_remove+0x28/0x2c) r5:bf001ca8 r4:c0673778 [] (platform_drv_remove+0x0/0x2c) from [] (__device_release_driver+0x80/0xdc) [] (__device_release_driver+0x0/0xdc) from [] (driver_detach+0xc4/0xc8) r5:bf001ca8 r4:c0673778 [] (driver_detach+0x0/0xc8) from [] (bus_remove_driver+0x9c/0x104) r6:c0804ee0 r5:bf001ca8 r4:bf001ca8 r3:00000000 [] (bus_remove_driver+0x0/0x104) from [] (driver_unregister+0x60/0x80) r6:c521e000 r5:bf001ca8 r4:00000000 r3:bf001924 [] (driver_unregister+0x0/0x80) from [] (platform_driver_unregister+0x1c/0x20) r5:00000000 r4:bf001d48 [] (platform_driver_unregister+0x0/0x20) from [] (omap_nand_driver_exit+0x14/0x1c [omap2]) [] (omap_nand_driver_exit+0x0/0x1c [omap2]) from [] (sys_delete_module+0x1f0/0x2ec) [] (sys_delete_module+0x0/0x2ec) from [] (ret_fast_syscall+0x0/0x48) r8:c0015028 r7:00000081 r6:b6fe0032 r5:70616d6f r4:0001a004 Code: e1a00005 eb0d9172 e7f001f2 e7f001f2 (e7f001f2) ---[ end trace 6a30b24d8c0cc2ee ]--- Segmentation fault --->8--- This error was introduced in 67ce04bf2746f8a1f8c2a104b313d20c63f68378 which was the first commit of this driver. Signed-off-by: Andreas Bießmann Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/omap2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index f47c422c7dfd..e604a458c8a6 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1364,7 +1364,7 @@ static int omap_nand_remove(struct platform_device *pdev) /* Release NAND device, its internal structures and partitions */ nand_release(&info->mtd); iounmap(info->nand.IO_ADDR_R); - kfree(&info->mtd); + kfree(info); return 0; } -- cgit v1.2.3 From 4d3d688da8e7016f15483e9319b41311e1db9515 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 31 Aug 2012 13:35:42 +0200 Subject: mtd: omap2: fix module loading MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unloading the omap2 nand driver missed to release the memory region which will result in not being able to request it again if one want to load the driver later on. This patch fixes following error when loading omap2 module after unloading: ---8<--- ~ $ rmmod omap2 ~ $ modprobe omap2 [ 37.420928] omap2-nand: probe of omap2-nand.0 failed with error -16 ~ $ --->8--- This error was introduced in 67ce04bf2746f8a1f8c2a104b313d20c63f68378 which was the first commit of this driver. Signed-off-by: Andreas Bießmann Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/omap2.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index e604a458c8a6..9142005c3029 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1364,6 +1364,7 @@ static int omap_nand_remove(struct platform_device *pdev) /* Release NAND device, its internal structures and partitions */ nand_release(&info->mtd); iounmap(info->nand.IO_ADDR_R); + release_mem_region(info->phys_base, NAND_IO_SIZE); kfree(info); return 0; } -- cgit v1.2.3 From 3d10095a941a29253102625d8710fe31a1a24b56 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Sep 2012 10:27:33 -0300 Subject: mtd: gpmi-nand: Improve logging style Improve logging style by prefixing the pr_ messages with "gpmi_nand". Signed-off-by: Fabio Estevam Acked-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index c46be6c8b2c4..94935079a328 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -18,6 +18,9 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include #include #include @@ -114,7 +117,7 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this) /* We use the same ECC strength for all chunks. */ geo->ecc_strength = get_ecc_strength(this); if (!geo->ecc_strength) { - pr_err("We get a wrong ECC strength.\n"); + pr_err("wrong ECC strength.\n"); return -EINVAL; } @@ -1685,9 +1688,9 @@ static int __init gpmi_nand_init(void) err = platform_driver_register(&gpmi_nand_driver); if (err == 0) - printk(KERN_INFO "GPMI NAND driver registered. (IMX)\n"); + pr_info("driver registered.\n"); else - pr_err("i.MX GPMI NAND driver registration failed\n"); + pr_err("driver registration failed.\n"); return err; } -- cgit v1.2.3 From 490e280a69cb0707ccb4c7e0c5c0be02d8ae102c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Sep 2012 11:35:24 -0300 Subject: mtd: gpmi-nand: Convert to module_platform_driver() Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 94935079a328..5999b15f3e87 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -1651,6 +1651,8 @@ static int __devinit gpmi_nand_probe(struct platform_device *pdev) if (ret) goto exit_nfc_init; + dev_info(this->dev, "driver registered.\n"); + return 0; exit_nfc_init: @@ -1658,10 +1660,12 @@ exit_nfc_init: exit_acquire_resources: platform_set_drvdata(pdev, NULL); kfree(this); + dev_err(this->dev, "driver registration failed: %d\n", ret); + return ret; } -static int __exit gpmi_nand_remove(struct platform_device *pdev) +static int __devexit gpmi_nand_remove(struct platform_device *pdev) { struct gpmi_nand_data *this = platform_get_drvdata(pdev); @@ -1678,29 +1682,10 @@ static struct platform_driver gpmi_nand_driver = { .of_match_table = gpmi_nand_id_table, }, .probe = gpmi_nand_probe, - .remove = __exit_p(gpmi_nand_remove), + .remove = __devexit_p(gpmi_nand_remove), .id_table = gpmi_ids, }; - -static int __init gpmi_nand_init(void) -{ - int err; - - err = platform_driver_register(&gpmi_nand_driver); - if (err == 0) - pr_info("driver registered.\n"); - else - pr_err("driver registration failed.\n"); - return err; -} - -static void __exit gpmi_nand_exit(void) -{ - platform_driver_unregister(&gpmi_nand_driver); -} - -module_init(gpmi_nand_init); -module_exit(gpmi_nand_exit); +module_platform_driver(gpmi_nand_driver); MODULE_AUTHOR("Freescale Semiconductor, Inc."); MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver"); -- cgit v1.2.3 From ddf16d620bd80b3c99160acd336c985b70399e37 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Sep 2012 11:35:25 -0300 Subject: mtd: mxc_nand: Convert to module_platform_driver() Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by: Fabio Estevam Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/mxc_nand.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index bfee9ebf9ab9..043e989f0578 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1363,7 +1363,7 @@ static int __init mxcnd_probe_pdata(struct mxc_nand_host *host) return 0; } -static int __init mxcnd_probe(struct platform_device *pdev) +static int __devinit mxcnd_probe(struct platform_device *pdev) { struct nand_chip *this; struct mtd_info *mtd; @@ -1555,22 +1555,10 @@ static struct platform_driver mxcnd_driver = { .owner = THIS_MODULE, .of_match_table = of_match_ptr(mxcnd_dt_ids), }, + .probe = mxcnd_probe, .remove = __devexit_p(mxcnd_remove), }; - -static int __init mxc_nd_init(void) -{ - return platform_driver_probe(&mxcnd_driver, mxcnd_probe); -} - -static void __exit mxc_nd_cleanup(void) -{ - /* Unregister the device structure */ - platform_driver_unregister(&mxcnd_driver); -} - -module_init(mxc_nd_init); -module_exit(mxc_nd_cleanup); +module_platform_driver(mxcnd_driver); MODULE_AUTHOR("Freescale Semiconductor, Inc."); MODULE_DESCRIPTION("MXC NAND MTD driver"); -- cgit v1.2.3 From 24b82d3c350dfc16cd4a7de87ca0959ff5fbaa15 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Sep 2012 11:52:27 -0300 Subject: mtd: mxc_nand: Adapt the clock name to the new clock framework With the new i.mx clock framework the mxc_nand clock is registered as: clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0") So we do not need to pass "nfc" string and can use NULL instead. Signed-off-by: Fabio Estevam Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/mxc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 043e989f0578..8ec7cc007dee 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1399,7 +1399,7 @@ static int __devinit mxcnd_probe(struct platform_device *pdev) this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; - host->clk = devm_clk_get(&pdev->dev, "nfc"); + host->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(host->clk)) return PTR_ERR(host->clk); -- cgit v1.2.3 From 2fe87aef33b77d66fada83f5dc57b6798ad5df07 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Wed, 5 Sep 2012 15:31:32 +0530 Subject: mtd: nand/gpio: Convert to module_platform_driver() module_platform_driver simplifies the code by eliminating module_init and module_exit calls. Signed-off-by: Sachin Kamat Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpio.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c index ce6a284c8277..bc73bc5f2713 100644 --- a/drivers/mtd/nand/gpio.c +++ b/drivers/mtd/nand/gpio.c @@ -417,20 +417,7 @@ static struct platform_driver gpio_nand_driver = { }, }; -static int __init gpio_nand_init(void) -{ - printk(KERN_INFO "GPIO NAND driver, © 2004 Simtec Electronics\n"); - - return platform_driver_register(&gpio_nand_driver); -} - -static void __exit gpio_nand_exit(void) -{ - platform_driver_unregister(&gpio_nand_driver); -} - -module_init(gpio_nand_init); -module_exit(gpio_nand_exit); +module_platform_driver(gpio_nand_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Ben Dooks "); -- cgit v1.2.3 From ea73fe7f0d562154975a77fe77ae3da6ab4d3e77 Mon Sep 17 00:00:00 2001 From: "m-karicheri2@ti.com" Date: Wed, 12 Sep 2012 21:06:19 +0000 Subject: mtd: nand: clk: preparation for switch to common clock framework As a first step towards migrating davinci platforms to use common clock framework, replace all instances of clk_enable() with clk_prepare_enable() and clk_disable() with clk_disable_unprepare(). Until the platform is switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just adds a might_sleep() call and would work without any issues. This will make it easy later to switch to common clk based implementation of clk driver from DaVinci specific driver. Signed-off-by: Murali Karicheri Reviewed-by: Mike Turquette Acked-by: Mike Turquette Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/davinci_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index f386b3c55031..df1ab7dc3440 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -724,7 +724,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) goto err_clk; } - ret = clk_enable(info->clk); + ret = clk_prepare_enable(info->clk); if (ret < 0) { dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", ret); @@ -835,7 +835,7 @@ syndrome_done: err_scan: err_timing: - clk_disable(info->clk); + clk_disable_unprepare(info->clk); err_clk_enable: clk_put(info->clk); @@ -872,7 +872,7 @@ static int __exit nand_davinci_remove(struct platform_device *pdev) nand_release(&info->mtd); - clk_disable(info->clk); + clk_disable_unprepare(info->clk); clk_put(info->clk); kfree(info); -- cgit v1.2.3 From b2bc415b6b7bb240b967f6dd95007a2cf7b4c424 Mon Sep 17 00:00:00 2001 From: Christian Daudt Date: Fri, 21 Sep 2012 14:40:25 -0700 Subject: mtd: remove bcmring NAND driver This driver is being removed as part of the cleanup of the bcmring SoC from mainline as it is no longer maintained. Signed-off-by: Christian Daudt Reviewed-by: Jiandong Zheng Acked-by: Will Deacon Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 16 -- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/bcm_umi_bch.c | 210 ---------------- drivers/mtd/nand/bcm_umi_nand.c | 533 ---------------------------------------- drivers/mtd/nand/nand_bcm_umi.c | 149 ----------- drivers/mtd/nand/nand_bcm_umi.h | 337 ------------------------- 6 files changed, 1246 deletions(-) delete mode 100644 drivers/mtd/nand/bcm_umi_bch.c delete mode 100644 drivers/mtd/nand/bcm_umi_nand.c delete mode 100644 drivers/mtd/nand/nand_bcm_umi.c delete mode 100644 drivers/mtd/nand/nand_bcm_umi.h (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 6010b500f93d..baa343634819 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -258,22 +258,6 @@ config MTD_NAND_S3C2410_CLKSTOP when the is NAND chip selected or released, but will save approximately 5mA of power when there is nothing happening. -config MTD_NAND_BCM_UMI - tristate "NAND Flash support for BCM Reference Boards" - depends on ARCH_BCMRING - help - This enables the NAND flash controller on the BCM UMI block. - - No board specific support is done by this driver, each board - must advertise a platform_device for the driver to attach. - -config MTD_NAND_BCM_UMI_HWCS - bool "BCM UMI NAND Hardware CS" - depends on MTD_NAND_BCM_UMI - help - Enable the use of the BCM UMI block's internal CS using NAND. - This should only be used if you know the external NAND CS can toggle. - config MTD_NAND_DISKONCHIP tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)" depends on EXPERIMENTAL diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c4b0ab316bab..2cbd0916b733 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o -obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c deleted file mode 100644 index ce39c8705d62..000000000000 --- a/drivers/mtd/nand/bcm_umi_bch.c +++ /dev/null @@ -1,210 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ -#include "nand_bcm_umi.h" - -/* ---- External Variable Declarations ----------------------------------- */ -/* ---- External Function Prototypes ------------------------------------- */ -/* ---- Public Variables ------------------------------------------------- */ -/* ---- Private Constants and Types -------------------------------------- */ - -/* ---- Private Function Prototypes -------------------------------------- */ -static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, uint8_t *buf, int oob_required, int page); -static int bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required); - -/* ---- Private Variables ------------------------------------------------ */ - -/* -** nand_hw_eccoob -** New oob placement block for use with hardware ecc generation. -*/ -static struct nand_ecclayout nand_hw_eccoob_512 = { - /* Reserve 5 for BI indicator */ - .oobfree = { -#if (NAND_ECC_NUM_BYTES > 3) - {.offset = 0, .length = 2} -#else - {.offset = 0, .length = 5}, - {.offset = 6, .length = 7} -#endif - } -}; - -/* -** We treat the OOB for a 2K page as if it were 4 512 byte oobs, -** except the BI is at byte 0. -*/ -static struct nand_ecclayout nand_hw_eccoob_2048 = { - /* Reserve 0 as BI indicator */ - .oobfree = { -#if (NAND_ECC_NUM_BYTES > 10) - {.offset = 1, .length = 2}, -#elif (NAND_ECC_NUM_BYTES > 7) - {.offset = 1, .length = 5}, - {.offset = 16, .length = 6}, - {.offset = 32, .length = 6}, - {.offset = 48, .length = 6} -#else - {.offset = 1, .length = 8}, - {.offset = 16, .length = 9}, - {.offset = 32, .length = 9}, - {.offset = 48, .length = 9} -#endif - } -}; - -/* We treat the OOB for a 4K page as if it were 8 512 byte oobs, - * except the BI is at byte 0. */ -static struct nand_ecclayout nand_hw_eccoob_4096 = { - /* Reserve 0 as BI indicator */ - .oobfree = { -#if (NAND_ECC_NUM_BYTES > 10) - {.offset = 1, .length = 2}, - {.offset = 16, .length = 3}, - {.offset = 32, .length = 3}, - {.offset = 48, .length = 3}, - {.offset = 64, .length = 3}, - {.offset = 80, .length = 3}, - {.offset = 96, .length = 3}, - {.offset = 112, .length = 3} -#else - {.offset = 1, .length = 5}, - {.offset = 16, .length = 6}, - {.offset = 32, .length = 6}, - {.offset = 48, .length = 6}, - {.offset = 64, .length = 6}, - {.offset = 80, .length = 6}, - {.offset = 96, .length = 6}, - {.offset = 112, .length = 6} -#endif - } -}; - -/* ---- Private Functions ------------------------------------------------ */ -/* ==== Public Functions ================================================= */ - -/**************************************************************************** -* -* bcm_umi_bch_read_page_hwecc - hardware ecc based page read function -* @mtd: mtd info structure -* @chip: nand chip info structure -* @buf: buffer to store read data -* @oob_required: caller expects OOB data read to chip->oob_poi -* -***************************************************************************/ -static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, uint8_t * buf, - int oob_required, int page) -{ - int sectorIdx = 0; - int eccsize = chip->ecc.size; - int eccsteps = chip->ecc.steps; - uint8_t *datap = buf; - uint8_t eccCalc[NAND_ECC_NUM_BYTES]; - int sectorOobSize = mtd->oobsize / eccsteps; - int stat; - unsigned int max_bitflips = 0; - - for (sectorIdx = 0; sectorIdx < eccsteps; - sectorIdx++, datap += eccsize) { - if (sectorIdx > 0) { - /* Seek to page location within sector */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize, - -1); - } - - /* Enable hardware ECC before reading the buf */ - nand_bcm_umi_bch_enable_read_hwecc(); - - /* Read in data */ - bcm_umi_nand_read_buf(mtd, datap, eccsize); - - /* Pause hardware ECC after reading the buf */ - nand_bcm_umi_bch_pause_read_ecc_calc(); - - /* Read the OOB ECC */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, - mtd->writesize + sectorIdx * sectorOobSize, -1); - nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc, - NAND_ECC_NUM_BYTES, - chip->oob_poi + - sectorIdx * sectorOobSize); - - /* Correct any ECC detected errors */ - stat = - nand_bcm_umi_bch_correct_page(datap, eccCalc, - NAND_ECC_NUM_BYTES); - - /* Update Stats */ - if (stat < 0) { -#if defined(NAND_BCM_UMI_DEBUG) - printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n", - __func__, sectorIdx); - printk(KERN_WARNING "%s data %*ph\n", - __func__, 8, datap); - printk(KERN_WARNING "%s ecc %*ph\n", - __func__, 13, eccCalc); - BUG(); -#endif - mtd->ecc_stats.failed++; - } else { -#if defined(NAND_BCM_UMI_DEBUG) - if (stat > 0) { - printk(KERN_INFO - "%s %d correctable_errors detected\n", - __func__, stat); - } -#endif - mtd->ecc_stats.corrected += stat; - max_bitflips = max_t(unsigned int, max_bitflips, stat); - } - } - return max_bitflips; -} - -/**************************************************************************** -* -* bcm_umi_bch_write_page_hwecc - hardware ecc based page write function -* @mtd: mtd info structure -* @chip: nand chip info structure -* @buf: data buffer -* @oob_required: must write chip->oob_poi to OOB -* -***************************************************************************/ -static int bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required) -{ - int sectorIdx = 0; - int eccsize = chip->ecc.size; - int eccsteps = chip->ecc.steps; - const uint8_t *datap = buf; - uint8_t *oobp = chip->oob_poi; - int sectorOobSize = mtd->oobsize / eccsteps; - - for (sectorIdx = 0; sectorIdx < eccsteps; - sectorIdx++, datap += eccsize, oobp += sectorOobSize) { - /* Enable hardware ECC before writing the buf */ - nand_bcm_umi_bch_enable_write_hwecc(); - bcm_umi_nand_write_buf(mtd, datap, eccsize); - nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp, - NAND_ECC_NUM_BYTES); - } - - bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); - - return 0; -} diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c deleted file mode 100644 index 3fcbcbc7b082..000000000000 --- a/drivers/mtd/nand/bcm_umi_nand.c +++ /dev/null @@ -1,533 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include "nand_bcm_umi.h" - -#include - -#define USE_DMA 1 -#include -#include -#include - -/* ---- External Variable Declarations ----------------------------------- */ -/* ---- External Function Prototypes ------------------------------------- */ -/* ---- Public Variables ------------------------------------------------- */ -/* ---- Private Constants and Types -------------------------------------- */ -static const __devinitconst char gBanner[] = KERN_INFO \ - "BCM UMI MTD NAND Driver: 1.00\n"; - -#if NAND_ECC_BCH -static uint8_t scan_ff_pattern[] = { 0xff }; - -static struct nand_bbt_descr largepage_bbt = { - .options = 0, - .offs = 0, - .len = 1, - .pattern = scan_ff_pattern -}; -#endif - -/* -** Preallocate a buffer to avoid having to do this every dma operation. -** This is the size of the preallocated coherent DMA buffer. -*/ -#if USE_DMA -#define DMA_MIN_BUFLEN 512 -#define DMA_MAX_BUFLEN PAGE_SIZE -#define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \ - ((len) > DMA_MAX_BUFLEN)) - -/* - * The current NAND data space goes from 0x80001900 to 0x80001FFF, - * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page - * size NAND flash. Need to break the DMA down to multiple 1Ks. - * - * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000 - */ -#define DMA_MAX_LEN 1024 - -#else /* !USE_DMA */ -#define DMA_MIN_BUFLEN 0 -#define DMA_MAX_BUFLEN 0 -#define USE_DIRECT_IO(len) 1 -#endif -/* ---- Private Function Prototypes -------------------------------------- */ -static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len); -static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf, - int len); - -/* ---- Private Variables ------------------------------------------------ */ -static struct mtd_info *board_mtd; -static void __iomem *bcm_umi_io_base; -static void *virtPtr; -static dma_addr_t physPtr; -static struct completion nand_comp; - -/* ---- Private Functions ------------------------------------------------ */ -#if NAND_ECC_BCH -#include "bcm_umi_bch.c" -#else -#include "bcm_umi_hamming.c" -#endif - -#if USE_DMA - -/* Handler called when the DMA finishes. */ -static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData) -{ - complete(&nand_comp); -} - -static int nand_dma_init(void) -{ - int rc; - - rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM, - nand_dma_handler, NULL); - if (rc != 0) { - printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc); - return rc; - } - - virtPtr = - dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL); - if (virtPtr == NULL) { - printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n"); - return -ENOMEM; - } - - return 0; -} - -static void nand_dma_term(void) -{ - if (virtPtr != NULL) - dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr); -} - -static void nand_dma_read(void *buf, int len) -{ - int offset = 0; - int tmp_len = 0; - int len_left = len; - DMA_Handle_t hndl; - - if (virtPtr == NULL) - panic("nand_dma_read: virtPtr == NULL\n"); - - if ((void *)physPtr == NULL) - panic("nand_dma_read: physPtr == NULL\n"); - - hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM); - if (hndl < 0) { - printk(KERN_ERR - "nand_dma_read: unable to allocate dma channel: %d\n", - (int)hndl); - panic("\n"); - } - - while (len_left > 0) { - if (len_left > DMA_MAX_LEN) { - tmp_len = DMA_MAX_LEN; - len_left -= DMA_MAX_LEN; - } else { - tmp_len = len_left; - len_left = 0; - } - - init_completion(&nand_comp); - dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR, - physPtr + offset, tmp_len); - wait_for_completion(&nand_comp); - - offset += tmp_len; - } - - dma_free_channel(hndl); - - if (buf != NULL) - memcpy(buf, virtPtr, len); -} - -static void nand_dma_write(const void *buf, int len) -{ - int offset = 0; - int tmp_len = 0; - int len_left = len; - DMA_Handle_t hndl; - - if (buf == NULL) - panic("nand_dma_write: buf == NULL\n"); - - if (virtPtr == NULL) - panic("nand_dma_write: virtPtr == NULL\n"); - - if ((void *)physPtr == NULL) - panic("nand_dma_write: physPtr == NULL\n"); - - memcpy(virtPtr, buf, len); - - - hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM); - if (hndl < 0) { - printk(KERN_ERR - "nand_dma_write: unable to allocate dma channel: %d\n", - (int)hndl); - panic("\n"); - } - - while (len_left > 0) { - if (len_left > DMA_MAX_LEN) { - tmp_len = DMA_MAX_LEN; - len_left -= DMA_MAX_LEN; - } else { - tmp_len = len_left; - len_left = 0; - } - - init_completion(&nand_comp); - dma_transfer_mem_to_mem(hndl, physPtr + offset, - REG_NAND_DATA_PADDR, tmp_len); - wait_for_completion(&nand_comp); - - offset += tmp_len; - } - - dma_free_channel(hndl); -} - -#endif - -static int nand_dev_ready(struct mtd_info *mtd) -{ - return nand_bcm_umi_dev_ready(); -} - -/**************************************************************************** -* -* bcm_umi_nand_inithw -* -* This routine does the necessary hardware (board-specific) -* initializations. This includes setting up the timings, etc. -* -***************************************************************************/ -int bcm_umi_nand_inithw(void) -{ - /* Configure nand timing parameters */ - REG_UMI_NAND_TCR &= ~0x7ffff; - REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; - -#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) - /* enable software control of CS */ - REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; -#endif - - /* keep NAND chip select asserted */ - REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; - - REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; - /* enable writes to flash */ - REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; - - writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); - nand_bcm_umi_wait_till_ready(); - -#if NAND_ECC_BCH - nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES); -#endif - - return 0; -} - -/* Used to turn latch the proper register for access. */ -static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - /* send command to hardware */ - struct nand_chip *chip = mtd->priv; - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_CLE) { - chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET; - goto CMD; - } - if (ctrl & NAND_ALE) { - chip->IO_ADDR_W = - bcm_umi_io_base + REG_NAND_ADDR_OFFSET; - goto CMD; - } - chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET; - } - -CMD: - /* Send command to chip directly */ - if (cmd != NAND_CMD_NONE) - writeb(cmd, chip->IO_ADDR_W); -} - -static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf, - int len) -{ - if (USE_DIRECT_IO(len)) { - /* Do it the old way if the buffer is small or too large. - * Probably quicker than starting and checking dma. */ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) - writeb(buf[i], this->IO_ADDR_W); - } -#if USE_DMA - else - nand_dma_write(buf, len); -#endif -} - -static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) -{ - if (USE_DIRECT_IO(len)) { - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) - buf[i] = readb(this->IO_ADDR_R); - } -#if USE_DMA - else - nand_dma_read(buf, len); -#endif -} - -static int __devinit bcm_umi_nand_probe(struct platform_device *pdev) -{ - struct nand_chip *this; - struct resource *r; - int err = 0; - - printk(gBanner); - - /* Allocate memory for MTD device structure and private data */ - board_mtd = - kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), - GFP_KERNEL); - if (!board_mtd) { - printk(KERN_WARNING - "Unable to allocate NAND MTD device structure.\n"); - return -ENOMEM; - } - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (!r) { - err = -ENXIO; - goto out_free; - } - - /* map physical address */ - bcm_umi_io_base = ioremap(r->start, resource_size(r)); - - if (!bcm_umi_io_base) { - printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n"); - err = -EIO; - goto out_free; - } - - /* Get pointer to private data */ - this = (struct nand_chip *)(&board_mtd[1]); - - /* Initialize structures */ - memset((char *)board_mtd, 0, sizeof(struct mtd_info)); - memset((char *)this, 0, sizeof(struct nand_chip)); - - /* Link the private data with the MTD structure */ - board_mtd->priv = this; - - /* Initialize the NAND hardware. */ - if (bcm_umi_nand_inithw() < 0) { - printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n"); - err = -EIO; - goto out_unmap; - } - - /* Set address of NAND IO lines */ - this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET; - this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET; - - /* Set command delay time, see datasheet for correct value */ - this->chip_delay = 0; - /* Assign the device ready function, if available */ - this->dev_ready = nand_dev_ready; - this->options = 0; - - this->write_buf = bcm_umi_nand_write_buf; - this->read_buf = bcm_umi_nand_read_buf; - - this->cmd_ctrl = bcm_umi_nand_hwcontrol; - this->ecc.mode = NAND_ECC_HW; - this->ecc.size = 512; - this->ecc.bytes = NAND_ECC_NUM_BYTES; -#if NAND_ECC_BCH - this->ecc.read_page = bcm_umi_bch_read_page_hwecc; - this->ecc.write_page = bcm_umi_bch_write_page_hwecc; -#else - this->ecc.correct = nand_correct_data512; - this->ecc.calculate = bcm_umi_hamming_get_hw_ecc; - this->ecc.hwctl = bcm_umi_hamming_enable_hwecc; -#endif - -#if USE_DMA - err = nand_dma_init(); - if (err != 0) - goto out_unmap; -#endif - - /* Figure out the size of the device that we have. - * We need to do this to figure out which ECC - * layout we'll be using. - */ - - err = nand_scan_ident(board_mtd, 1, NULL); - if (err) { - printk(KERN_ERR "nand_scan failed: %d\n", err); - goto out_unmap; - } - - /* Now that we know the nand size, we can setup the ECC layout */ - - switch (board_mtd->writesize) { /* writesize is the pagesize */ - case 4096: - this->ecc.layout = &nand_hw_eccoob_4096; - break; - case 2048: - this->ecc.layout = &nand_hw_eccoob_2048; - break; - case 512: - this->ecc.layout = &nand_hw_eccoob_512; - break; - default: - { - printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n", - board_mtd->writesize); - err = -EINVAL; - goto out_unmap; - } - } - -#if NAND_ECC_BCH - if (board_mtd->writesize > 512) { - if (this->bbt_options & NAND_BBT_USE_FLASH) - largepage_bbt.options = NAND_BBT_SCAN2NDPAGE; - this->badblock_pattern = &largepage_bbt; - } - - this->ecc.strength = 8; - -#endif - - /* Now finish off the scan, now that ecc.layout has been initialized. */ - - err = nand_scan_tail(board_mtd); - if (err) { - printk(KERN_ERR "nand_scan failed: %d\n", err); - goto out_unmap; - } - - /* Register the partitions */ - board_mtd->name = "bcm_umi-nand"; - mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0); - - /* Return happy */ - return 0; -out_unmap: - iounmap(bcm_umi_io_base); -out_free: - kfree(board_mtd); - return err; -} - -static int bcm_umi_nand_remove(struct platform_device *pdev) -{ -#if USE_DMA - nand_dma_term(); -#endif - - /* Release resources, unregister device */ - nand_release(board_mtd); - - /* unmap physical address */ - iounmap(bcm_umi_io_base); - - /* Free the MTD device structure */ - kfree(board_mtd); - - return 0; -} - -#ifdef CONFIG_PM -static int bcm_umi_nand_suspend(struct platform_device *pdev, - pm_message_t state) -{ - printk(KERN_ERR "MTD NAND suspend is being called\n"); - return 0; -} - -static int bcm_umi_nand_resume(struct platform_device *pdev) -{ - printk(KERN_ERR "MTD NAND resume is being called\n"); - return 0; -} -#else -#define bcm_umi_nand_suspend NULL -#define bcm_umi_nand_resume NULL -#endif - -static struct platform_driver nand_driver = { - .driver = { - .name = "bcm-nand", - .owner = THIS_MODULE, - }, - .probe = bcm_umi_nand_probe, - .remove = bcm_umi_nand_remove, - .suspend = bcm_umi_nand_suspend, - .resume = bcm_umi_nand_resume, -}; - -module_platform_driver(nand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Broadcom"); -MODULE_DESCRIPTION("BCM UMI MTD NAND driver"); diff --git a/drivers/mtd/nand/nand_bcm_umi.c b/drivers/mtd/nand/nand_bcm_umi.c deleted file mode 100644 index 46a6bc9c4b74..000000000000 --- a/drivers/mtd/nand/nand_bcm_umi.c +++ /dev/null @@ -1,149 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include "nand_bcm_umi.h" -#ifdef BOOT0_BUILD -#include -#endif - -/* ---- External Variable Declarations ----------------------------------- */ -/* ---- External Function Prototypes ------------------------------------- */ -/* ---- Public Variables ------------------------------------------------- */ -/* ---- Private Constants and Types -------------------------------------- */ -/* ---- Private Function Prototypes -------------------------------------- */ -/* ---- Private Variables ------------------------------------------------ */ -/* ---- Private Functions ------------------------------------------------ */ - -#if NAND_ECC_BCH -/**************************************************************************** -* nand_bch_ecc_flip_bit - Routine to flip an errored bit -* -* PURPOSE: -* This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the -* errored bit specified -* -* PARAMETERS: -* datap - Container that holds the 512 byte data -* errorLocation - Location of the bit that needs to be flipped -* -* RETURNS: -* None -****************************************************************************/ -static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int errorLocation) -{ - int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0; - int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3; - int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5; - - uint8_t errorByte = 0; - uint8_t byteMask = 1 << locWithinAByte; - - /* BCH uses big endian, need to change the location - * bits to little endian */ - locWithinAWord = 3 - locWithinAWord; - - errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord]; - -#ifdef BOOT0_BUILD - puthexs("\nECC Correct Offset: ", - locWithinAPage * sizeof(uint32_t) + locWithinAWord); - puthexs(" errorByte:", errorByte); - puthex8(" Bit: ", locWithinAByte); -#endif - - if (errorByte & byteMask) { - /* bit needs to be cleared */ - errorByte &= ~byteMask; - } else { - /* bit needs to be set */ - errorByte |= byteMask; - } - - /* write back the value with the fixed bit */ - datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte; -} - -/**************************************************************************** -* nand_correct_page_bch - Routine to correct bit errors when reading NAND -* -* PURPOSE: -* This routine reads the BCH registers to determine if there are any bit -* errors during the read of the last 512 bytes of data + ECC bytes. If -* errors exists, the routine fixes it. -* -* PARAMETERS: -* datap - Container that holds the 512 byte data -* -* RETURNS: -* 0 or greater = Number of errors corrected -* (No errors are found or errors have been fixed) -* -1 = Error(s) cannot be fixed -****************************************************************************/ -int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, - int numEccBytes) -{ - int numErrors; - int errorLocation; - int idx; - uint32_t regValue; - - /* wait for read ECC to be valid */ - regValue = nand_bcm_umi_bch_poll_read_ecc_calc(); - - /* - * read the control status register to determine if there - * are error'ed bits - * see if errors are correctible - */ - if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) { - int i; - - for (i = 0; i < numEccBytes; i++) { - if (readEccData[i] != 0xff) { - /* errors cannot be fixed, return -1 */ - return -1; - } - } - /* If ECC is unprogrammed then we can't correct, - * assume everything OK */ - return 0; - } - - if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) { - /* no errors */ - return 0; - } - - /* - * Fix errored bits by doing the following: - * 1. Read the number of errors in the control and status register - * 2. Read the error location registers that corresponds to the number - * of errors reported - * 3. Invert the bit in the data - */ - numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20; - - for (idx = 0; idx < numErrors; idx++) { - errorLocation = - REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK; - - /* Flip bit */ - nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation); - } - /* Errors corrected */ - return numErrors; -} -#endif diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h deleted file mode 100644 index 198b304d6f72..000000000000 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ /dev/null @@ -1,337 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ -#ifndef NAND_BCM_UMI_H -#define NAND_BCM_UMI_H - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include - -/* ---- Constants and Types ---------------------------------------------- */ -#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) -#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0) -#else -#define NAND_ECC_BCH 0 -#endif - -#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES 13 - -#if NAND_ECC_BCH -#ifdef BOOT0_BUILD -#define NAND_ECC_NUM_BYTES 13 -#else -#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES -#endif -#else -#define NAND_ECC_NUM_BYTES 3 -#endif - -#define NAND_DATA_ACCESS_SIZE 512 - -/* ---- Variable Externs ------------------------------------------ */ -/* ---- Function Prototypes --------------------------------------- */ -int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, - int numEccBytes); - -/* Check in device is ready */ -static inline int nand_bcm_umi_dev_ready(void) -{ - return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; -} - -/* Wait until device is ready */ -static inline void nand_bcm_umi_wait_till_ready(void) -{ - while (nand_bcm_umi_dev_ready() == 0) - ; -} - -/* Enable Hamming ECC */ -static inline void nand_bcm_umi_hamming_enable_hwecc(void) -{ - /* disable and reset ECC, 512 byte page */ - REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | - REG_UMI_NAND_ECC_CSR_256BYTE); - /* enable ECC */ - REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; -} - -#if NAND_ECC_BCH -/* BCH ECC specifics */ -#define ECC_BITS_PER_CORRECTABLE_BIT 13 - -/* Enable BCH Read ECC */ -static inline void nand_bcm_umi_bch_enable_read_hwecc(void) -{ - /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; - /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; -} - -/* Enable BCH Write ECC */ -static inline void nand_bcm_umi_bch_enable_write_hwecc(void) -{ - /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; - /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; -} - -/* Config number of BCH ECC bytes */ -static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) -{ - uint32_t nValue; - uint32_t tValue; - uint32_t kValue; - uint32_t numBits = numEccBytes * 8; - - /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | - REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; - - /* Every correctible bit requires 13 ECC bits */ - tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); - - /* Total data in number of bits for generating and computing BCH ECC */ - nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8; - - /* K parameter is used internally. K = N - (T * 13) */ - kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); - - /* Write the settings */ - REG_UMI_BCH_N = nValue; - REG_UMI_BCH_T = tValue; - REG_UMI_BCH_K = kValue; -} - -/* Pause during ECC read calculation to skip bytes in OOB */ -static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) -{ - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | - REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC; -} - -/* Resume during ECC read calculation after skipping bytes in OOB */ -static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) -{ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; -} - -/* Poll read ECC calc to check when hardware completes */ -static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) -{ - uint32_t regVal; - - do { - /* wait for ECC to be valid */ - regVal = REG_UMI_BCH_CTRL_STATUS; - } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); - - return regVal; -} - -/* Poll write ECC calc to check when hardware completes */ -static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) -{ - /* wait for ECC to be valid */ - while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) - == 0) - ; -} - -/* Read the OOB and ECC, for kernel write OOB to a buffer */ -#if defined(__KERNEL__) && !defined(STANDALONE) -static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, - uint8_t *eccCalc, int numEccBytes, uint8_t *oobp) -#else -static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, - uint8_t *eccCalc, int numEccBytes) -#endif -{ - int eccPos = 0; - int numToRead = 16; /* There are 16 bytes per sector in the OOB */ - - /* ECC is already paused when this function is called */ - if (pageSize != NAND_DATA_ACCESS_SIZE) { - /* skip BI */ -#if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; -#else - REG_NAND_DATA8; -#endif - numToRead--; - } - - while (numToRead > numEccBytes) { - /* skip free oob region */ -#if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; -#else - REG_NAND_DATA8; -#endif - numToRead--; - } - - if (pageSize == NAND_DATA_ACCESS_SIZE) { - /* read ECC bytes before BI */ - nand_bcm_umi_bch_resume_read_ecc_calc(); - - while (numToRead > 11) { -#if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; - eccCalc[eccPos++] = *oobp; - oobp++; -#else - eccCalc[eccPos++] = REG_NAND_DATA8; -#endif - numToRead--; - } - - nand_bcm_umi_bch_pause_read_ecc_calc(); - - if (numToRead == 11) { - /* read BI */ -#if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; -#else - REG_NAND_DATA8; -#endif - numToRead--; - } - - } - /* read ECC bytes */ - nand_bcm_umi_bch_resume_read_ecc_calc(); - while (numToRead) { -#if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; - eccCalc[eccPos++] = *oobp; - oobp++; -#else - eccCalc[eccPos++] = REG_NAND_DATA8; -#endif - numToRead--; - } -} - -/* Helper function to write ECC */ -static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos, - uint8_t *oobp, uint8_t eccVal) -{ - if (eccBytePos <= numEccBytes) - *oobp = eccVal; -} - -/* Write OOB with ECC */ -static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, - uint8_t *oobp, int numEccBytes) -{ - uint32_t eccVal = 0xffffffff; - - /* wait for write ECC to be valid */ - nand_bcm_umi_bch_poll_write_ecc_calc(); - - /* - ** Get the hardware ecc from the 32-bit result registers. - ** Read after 512 byte accesses. Format B3B2B1B0 - ** where B3 = ecc3, etc. - */ - - if (pageSize == NAND_DATA_ACCESS_SIZE) { - /* Now fill in the ECC bytes */ - if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; - - /* Usually we skip CM in oob[0,1] */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], - (eccVal >> 16) & 0xff); - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1], - (eccVal >> 8) & 0xff); - - /* Write ECC in oob[2,3,4] */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2], - eccVal & 0xff); /* ECC 12 */ - - if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; - - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], - (eccVal >> 24) & 0xff); /* ECC11 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4], - (eccVal >> 16) & 0xff); /* ECC10 */ - - /* Always Skip BI in oob[5] */ - } else { - /* Always Skip BI in oob[0] */ - - /* Now fill in the ECC bytes */ - if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; - - /* Usually skip CM in oob[1,2] */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], - (eccVal >> 16) & 0xff); - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2], - (eccVal >> 8) & 0xff); - - /* Write ECC in oob[3-15] */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3], - eccVal & 0xff); /* ECC12 */ - - if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; - - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], - (eccVal >> 24) & 0xff); /* ECC11 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5], - (eccVal >> 16) & 0xff); /* ECC10 */ - } - - /* Fill in the remainder of ECC locations */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6], - (eccVal >> 8) & 0xff); /* ECC9 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7], - eccVal & 0xff); /* ECC8 */ - - if (numEccBytes >= 5) - eccVal = REG_UMI_BCH_WR_ECC_1; - - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], - (eccVal >> 24) & 0xff); /* ECC7 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9], - (eccVal >> 16) & 0xff); /* ECC6 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10], - (eccVal >> 8) & 0xff); /* ECC5 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11], - eccVal & 0xff); /* ECC4 */ - - if (numEccBytes >= 1) - eccVal = REG_UMI_BCH_WR_ECC_0; - - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], - (eccVal >> 24) & 0xff); /* ECC3 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13], - (eccVal >> 16) & 0xff); /* ECC2 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14], - (eccVal >> 8) & 0xff); /* ECC1 */ - NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15], - eccVal & 0xff); /* ECC0 */ -} -#endif - -#endif /* NAND_BCM_UMI_H */ -- cgit v1.2.3 From 61de9da657e8c52606d45ae67dfa187111bf9b55 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Tue, 11 Sep 2012 15:50:54 +0200 Subject: mtd: nand: use NAND_BBT_SCAN_MAXBLOCKS In nand_bbt.c, a hardcoded value was used instead of the define meant for that, so we use the define. There's no functional change. Signed-off-by: Richard Genoud Acked-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_bbt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 2f744dd90740..916d6e9c0ab1 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -62,6 +62,7 @@ #include #include #include +#include #include #include #include @@ -1258,7 +1259,7 @@ static struct nand_bbt_descr bbt_main_descr = { .offs = 8, .len = 4, .veroffs = 12, - .maxblocks = 4, + .maxblocks = NAND_BBT_SCAN_MAXBLOCKS, .pattern = bbt_pattern }; @@ -1268,7 +1269,7 @@ static struct nand_bbt_descr bbt_mirror_descr = { .offs = 8, .len = 4, .veroffs = 12, - .maxblocks = 4, + .maxblocks = NAND_BBT_SCAN_MAXBLOCKS, .pattern = mirror_pattern }; @@ -1278,7 +1279,7 @@ static struct nand_bbt_descr bbt_main_no_oob_descr = { | NAND_BBT_NO_OOB, .len = 4, .veroffs = 4, - .maxblocks = 4, + .maxblocks = NAND_BBT_SCAN_MAXBLOCKS, .pattern = bbt_pattern }; @@ -1288,7 +1289,7 @@ static struct nand_bbt_descr bbt_mirror_no_oob_descr = { | NAND_BBT_NO_OOB, .len = 4, .veroffs = 4, - .maxblocks = 4, + .maxblocks = NAND_BBT_SCAN_MAXBLOCKS, .pattern = mirror_pattern }; -- cgit v1.2.3 From 5bf3d66a933efb71fa6db08a5043a617b6eadb4a Mon Sep 17 00:00:00 2001 From: Mike Dunn Date: Tue, 11 Sep 2012 08:50:50 -0700 Subject: mtd: docg4: ecc.read_page() returns 0 on uncorrectable errors Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectable bitflips occur. This is wrong; 0 should be returned in this case. An error code should only be returned by this method in the case of a hardware error (probably -EIO). Signed-off-by: Mike Dunn Acked-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/docg4.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c index 793921e56f8e..799da5d1c857 100644 --- a/drivers/mtd/nand/docg4.c +++ b/drivers/mtd/nand/docg4.c @@ -776,6 +776,8 @@ static int read_page(struct mtd_info *mtd, struct nand_chip *nand, } writew(0, docptr + DOC_DATAEND); + if (bits_corrected == -EBADMSG) /* uncorrectable errors */ + return 0; return bits_corrected; } -- cgit v1.2.3 From bb0a13a13411c4ce24c48c8ff3cdf7b48d237240 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Wed, 12 Sep 2012 14:26:26 +0200 Subject: mtd: nandsim: bugfix: fail if overridesize is too big If override size is too big, the module was actually loaded instead of failing, because retval was not set. This lead to memory corruption with the use of the freed structs nandsim and nand_chip. Cc: stable@vger.kernel.org Signed-off-by: Richard Genoud Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nandsim.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c index 21e64b5d352b..a932c485eb04 100644 --- a/drivers/mtd/nand/nandsim.c +++ b/drivers/mtd/nand/nandsim.c @@ -2317,6 +2317,7 @@ static int __init ns_init_module(void) uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize; if (new_size >> overridesize != nsmtd->erasesize) { NS_ERR("overridesize is too big\n"); + retval = -EINVAL; goto err_exit; } /* N.B. This relies on nand_scan not doing anything with the size before we change it */ -- cgit v1.2.3 From 2caf87a49eb53fac266b1271ebd6c1d1daa0d0d0 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 13 Sep 2012 18:56:07 -0500 Subject: mtd: fsl_ifc_nand: fix sparse warnings drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: cast removes address space of expression [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: incorrect type in initializer (different address spaces) [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: expected unsigned int [noderef] [usertype] *mainarea [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: got unsigned int [usertype] * [sparse] ... Signed-off-by: Kim Phillips Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/fsl_ifc_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index e92d223e5e1a..1be83dcc730a 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -193,7 +193,7 @@ static int is_blank(struct mtd_info *mtd, unsigned int bufnum) struct nand_chip *chip = mtd->priv; struct fsl_ifc_mtd *priv = chip->priv; u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2); - u32 __iomem *mainarea = (u32 *)addr; + u32 __iomem *mainarea = (u32 __iomem *)addr; u8 __iomem *oob = addr + mtd->writesize; int i; @@ -591,8 +591,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { - data = in_be16((uint16_t *)&ifc_nand_ctrl-> - addr[ifc_nand_ctrl->index]); + data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl-> + addr[ifc_nand_ctrl->index]); ifc_nand_ctrl->index += 2; return (uint8_t) data; } -- cgit v1.2.3 From 7db03eccfc23783a95dd78383b3fad55224aaa7b Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:52 +0800 Subject: mtd: add helpers to set/get features for ONFI nand Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand. Also add the necessary macros. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 88f671cb96c7..d06a80d4ee75 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2699,6 +2699,50 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) return chip->block_markbad(mtd, ofs); } +/** + * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand + * @mtd: MTD device structure + * @chip: nand chip info structure + * @addr: feature address. + * @subfeature_param: the subfeature parameters, a four bytes array. + */ +static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, + int addr, uint8_t *subfeature_param) +{ + int status; + + if (!chip->onfi_version) + return -EINVAL; + + chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); + chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); + status = chip->waitfunc(mtd, chip); + if (status & NAND_STATUS_FAIL) + return -EIO; + return 0; +} + +/** + * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand + * @mtd: MTD device structure + * @chip: nand chip info structure + * @addr: feature address. + * @subfeature_param: the subfeature parameters, a four bytes array. + */ +static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, + int addr, uint8_t *subfeature_param) +{ + if (!chip->onfi_version) + return -EINVAL; + + /* clear the sub feature parameters */ + memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); + + chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); + chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); + return 0; +} + /** * nand_suspend - [MTD Interface] Suspend the NAND flash * @mtd: MTD device structure @@ -3223,6 +3267,12 @@ int nand_scan_tail(struct mtd_info *mtd) if (!chip->write_page) chip->write_page = nand_write_page; + /* set for ONFI nand */ + if (!chip->onfi_set_features) + chip->onfi_set_features = nand_onfi_set_features; + if (!chip->onfi_get_features) + chip->onfi_get_features = nand_onfi_get_features; + /* * Check ECC mode, default to software if 3byte/512byte hardware ECC is * selected and we have 256 byte pagesize fallback to software ECC -- cgit v1.2.3 From ddab3838aa3332ed2c8ea96accbed5218a2a72b7 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:54 +0800 Subject: mtd: gpmi: add a new field for HW_GPMI_TIMING1 The gpmi_nfc_compute_hardware_timing{} should contains all the fields setting for gpmi timing registers. It already contains the fields for HW_GPMI_TIMING0 and HW_GPMI_CTRL1. So it is better to add a new field setting for HW_GPMI_TIMING1 in this data structure. This makes the code more clear in logic. This patch also changes some comments to make the code more readable. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 17 +++++++++-------- drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 10 ++++++++++ drivers/mtd/nand/gpmi-nand/gpmi-regs.h | 3 +++ 3 files changed, 22 insertions(+), 8 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 2289cf8dc35b..c95dbe8bb272 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -728,6 +728,7 @@ return_results: hw->address_setup_in_cycles = address_setup_in_cycles; hw->use_half_periods = dll_use_half_periods; hw->sample_delay_factor = sample_delay_factor; + hw->device_busy_timeout = GPMI_DEFAULT_BUSY_TIMEOUT; /* Return success. */ return 0; @@ -752,26 +753,26 @@ void gpmi_begin(struct gpmi_nand_data *this) goto err_out; } - /* set ready/busy timeout */ - writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT, - gpmi_regs + HW_GPMI_TIMING1); - /* Get the timing information we need. */ nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]); clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz; gpmi_nfc_compute_hardware_timing(this, &hw); - /* Set up all the simple timing parameters. */ + /* [1] Set HW_GPMI_TIMING0 */ reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) | BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) | BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ; writel(reg, gpmi_regs + HW_GPMI_TIMING0); - /* - * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. - */ + /* [2] Set HW_GPMI_TIMING1 */ + writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout), + gpmi_regs + HW_GPMI_TIMING1); + + /* [3] The following code is to set the HW_GPMI_CTRL1. */ + + /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */ writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); /* Clear out the DLL control fields. */ diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1f6121782330..c814bddaffc4 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -189,14 +189,24 @@ struct gpmi_nand_data { * @data_setup_in_cycles: The data setup time, in cycles. * @data_hold_in_cycles: The data hold time, in cycles. * @address_setup_in_cycles: The address setup time, in cycles. + * @device_busy_timeout: The timeout waiting for NAND Ready/Busy, + * this value is the number of cycles multiplied + * by 4096. * @use_half_periods: Indicates the clock is running slowly, so the * NFC DLL should use half-periods. * @sample_delay_factor: The sample delay factor. */ struct gpmi_nfc_hardware_timing { + /* for HW_GPMI_TIMING0 */ uint8_t data_setup_in_cycles; uint8_t data_hold_in_cycles; uint8_t address_setup_in_cycles; + + /* for HW_GPMI_TIMING1 */ + uint16_t device_busy_timeout; +#define GPMI_DEFAULT_BUSY_TIMEOUT 0x500 /* default busy timeout value.*/ + + /* for HW_GPMI_CTRL1 */ bool use_half_periods; uint8_t sample_delay_factor; }; diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h index 83431240e2f2..8994e201924c 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h @@ -154,6 +154,9 @@ #define HW_GPMI_TIMING1 0x00000080 #define BP_GPMI_TIMING1_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT) +#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) \ + (((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT) #define HW_GPMI_TIMING2 0x00000090 #define HW_GPMI_DATA 0x000000a0 -- cgit v1.2.3 From ae70ba2d6078d60c527c93076133accf59becaf8 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:55 +0800 Subject: mtd: gpmi: do not get the clock frequency in gpmi_begin() The current code will gets the clock frequency which is used by gpmi_nfc_compute_hardware_timing(). It makes the code a little mess. So move the `get clock frequency` code to the gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy and clean. This patch also uses the macro NSEC_PER_SEC to replace the `1000000000`. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index c95dbe8bb272..41e905dfc399 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -293,6 +293,7 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this, struct gpmi_nfc_hardware_timing *hw) { struct timing_threshod *nfc = &timing_default_threshold; + struct resources *r = &this->resources; struct nand_chip *nand = &this->nand; struct nand_timing target = this->timing; bool improved_timing_is_available; @@ -332,8 +333,9 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this, (target.tRHOH_in_ns >= 0) ; /* Inspect the clock. */ + nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]); clock_frequency_in_hz = nfc->clock_frequency_in_hz; - clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + clock_period_in_ns = NSEC_PER_SEC / clock_frequency_in_hz; /* * The NFC quantizes setup and hold parameters in terms of clock cycles. @@ -738,7 +740,6 @@ return_results: void gpmi_begin(struct gpmi_nand_data *this) { struct resources *r = &this->resources; - struct timing_threshod *nfc = &timing_default_threshold; void __iomem *gpmi_regs = r->gpmi_regs; unsigned int clock_period_in_ns; uint32_t reg; @@ -753,10 +754,6 @@ void gpmi_begin(struct gpmi_nand_data *this) goto err_out; } - /* Get the timing information we need. */ - nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]); - clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz; - gpmi_nfc_compute_hardware_timing(this, &hw); /* [1] Set HW_GPMI_TIMING0 */ @@ -801,6 +798,7 @@ void gpmi_begin(struct gpmi_nand_data *this) * * Calculate the amount of time we need to wait, in microseconds. */ + clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]); dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000; if (!dll_wait_time_in_us) -- cgit v1.2.3 From d37e02d8f3a892b57738f1c1431779d5939214d1 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:56 +0800 Subject: mtd: gpmi: add a new field for HW_GPMI_CTRL1 add the WRN_DLY_SEL field for HW_GPMI_CTRL1. This field is used as delay for gpmi write strobe. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 6 ++++++ drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 2 ++ drivers/mtd/nand/gpmi-nand/gpmi-regs.h | 9 +++++++++ 3 files changed, 17 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 41e905dfc399..2d1f77c0527e 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -731,6 +731,7 @@ return_results: hw->use_half_periods = dll_use_half_periods; hw->sample_delay_factor = sample_delay_factor; hw->device_busy_timeout = GPMI_DEFAULT_BUSY_TIMEOUT; + hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS; /* Return success. */ return 0; @@ -769,6 +770,11 @@ void gpmi_begin(struct gpmi_nand_data *this) /* [3] The following code is to set the HW_GPMI_CTRL1. */ + /* Set the WRN_DLY_SEL */ + writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR); + writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel), + gpmi_regs + HW_GPMI_CTRL1_SET); + /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */ writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index c814bddaffc4..5c11e761a32e 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -195,6 +195,7 @@ struct gpmi_nand_data { * @use_half_periods: Indicates the clock is running slowly, so the * NFC DLL should use half-periods. * @sample_delay_factor: The sample delay factor. + * @wrn_dly_sel: The delay on the GPMI write strobe. */ struct gpmi_nfc_hardware_timing { /* for HW_GPMI_TIMING0 */ @@ -209,6 +210,7 @@ struct gpmi_nfc_hardware_timing { /* for HW_GPMI_CTRL1 */ bool use_half_periods; uint8_t sample_delay_factor; + uint8_t wrn_dly_sel; }; /** diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h index 8994e201924c..53397cc290fc 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h @@ -108,6 +108,15 @@ #define HW_GPMI_CTRL1_CLR 0x00000068 #define HW_GPMI_CTRL1_TOG 0x0000006c +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL) +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ + (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0 +#define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1 +#define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2 +#define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3 + #define BM_GPMI_CTRL1_BCH_MODE (1 << 18) #define BP_GPMI_CTRL1_DLL_ENABLE 17 -- cgit v1.2.3 From c50d35a9fdb628c5fcce5c2d4ab5ad9bedb2edb9 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:57 +0800 Subject: mtd: gpmi: simplify the DLL setting code The setting DLL code is a little mess. Just simplify the code and the comments. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 2d1f77c0527e..010665ca631a 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -779,30 +779,26 @@ void gpmi_begin(struct gpmi_nand_data *this) writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); /* Clear out the DLL control fields. */ - writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR); - writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR); + reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD; + writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR); /* If no sample delay is called for, return immediately. */ if (!hw.sample_delay_factor) return; - /* Configure the HALF_PERIOD flag. */ - if (hw.use_half_periods) - writel(BM_GPMI_CTRL1_HALF_PERIOD, - gpmi_regs + HW_GPMI_CTRL1_SET); + /* Set RDN_DELAY or HALF_PERIOD. */ + reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0) + | BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor); - /* Set the delay factor. */ - writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor), - gpmi_regs + HW_GPMI_CTRL1_SET); + writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET); - /* Enable the DLL. */ + /* At last, we enable the DLL. */ writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET); /* * After we enable the GPMI DLL, we have to wait 64 clock cycles before - * we can use the GPMI. - * - * Calculate the amount of time we need to wait, in microseconds. + * we can use the GPMI. Calculate the amount of time we need to wait, + * in microseconds. */ clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]); dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000; -- cgit v1.2.3 From e1ca95e3a93c9a0392163a7a6791deda48b5eeca Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:58 +0800 Subject: mtd: gpmi: do not set the default values for the extra clocks The default frequencies of the extra clocks are 200MHz. The current code sets the extra clocks to 44.5MHz. When i add the EDO feature to gpmi, i have to revert the extra clocks to 200MHz. So it is better that we do not set the default values for the extra clocks. The driver runs well even when we do not set the default values for extra clocks. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 5999b15f3e87..2bfd44876f81 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -516,20 +516,15 @@ static int __devinit gpmi_get_clks(struct gpmi_nand_data *this) r->clock[i] = clk; } - if (GPMI_IS_MX6Q(this)) { + if (GPMI_IS_MX6Q(this)) /* - * Set the default values for the clocks in mx6q: - * The main clock(enfc) : 22MHz - * The others : 44.5MHz + * Set the default value for the gpmi clock in mx6q: * - * These are just the default values. If you want to use - * the ONFI nand which is in the Synchronous Mode, you should - * change the clocks's frequencies as you need. + * If you want to use the ONFI nand which is in the + * Synchronous Mode, you should change the clock as you need. */ clk_set_rate(r->clock[0], 22000000); - for (i = 1; i < GPMI_CLK_MAX && r->clock[i]; i++) - clk_set_rate(r->clock[i], 44500000); - } + return 0; err_clock: -- cgit v1.2.3 From 995fbbf563fcec058a1135bdd112ac969c817e65 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:57:59 +0800 Subject: mtd: gpmi: add EDO feature for imx6q When the frequency on the nand chip pins is above 33MHz, the nand EDO(extended Data Out) timing could be applied. The GPMI implements a Feedback read strobe to sample the read data in the EDO timing mode. This patch adds the EDO feature for the gpmi-nand driver. For some onfi nand chips, the mode 4 is the fastest; while for other onfi nand chips, the mode 5 is the fastest. This patch only adds the support for the fastest asynchronous timing mode. So this patch only supports the mode 4 and mode 5. I tested several Micron's ONFI nand chips with EDO enabled, take Micron MT29F32G08MAA for example (in mode 5, 100MHz): 1) The test result BEFORE we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 3632 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 3554 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 3592 KiB/s ....................................... ================================================= 2) The test result AFTER we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19555 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17319 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 18339 KiB/s ....................................... ================================================= 3) The read data performance is much improved by more then 5 times. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 214 ++++++++++++++++++++++++++++++++- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 8 ++ drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 6 + 3 files changed, 227 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 010665ca631a..c036e51f3200 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -737,6 +737,215 @@ return_results: return 0; } +/* + * <1> Firstly, we should know what's the GPMI-clock means. + * The GPMI-clock is the internal clock in the gpmi nand controller. + * If you set 100MHz to gpmi nand controller, the GPMI-clock's period + * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period. + * + * <2> Secondly, we should know what's the frequency on the nand chip pins. + * The frequency on the nand chip pins is derived from the GPMI-clock. + * We can get it from the following equation: + * + * F = G / (DS + DH) + * + * F : the frequency on the nand chip pins. + * G : the GPMI clock, such as 100MHz. + * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP + * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD + * + * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz, + * the nand EDO(extended Data Out) timing could be applied. + * The GPMI implements a feedback read strobe to sample the read data. + * The feedback read strobe can be delayed to support the nand EDO timing + * where the read strobe may deasserts before the read data is valid, and + * read data is valid for some time after read strobe. + * + * The following figure illustrates some aspects of a NAND Flash read: + * + * |<---tREA---->| + * | | + * | | | + * |<--tRP-->| | + * | | | + * __ ___|__________________________________ + * RDN \________/ | + * | + * /---------\ + * Read Data --------------< >--------- + * \---------/ + * | | + * |<-D->| + * FeedbackRDN ________ ____________ + * \___________/ + * + * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY. + * + * + * <4> Now, we begin to describe how to compute the right RDN_DELAY. + * + * 4.1) From the aspect of the nand chip pins: + * Delay = (tREA + C - tRP) {1} + * + * tREA : the maximum read access time. From the ONFI nand standards, + * we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4. + * Please check it in : www.onfi.org + * C : a constant for adjust the delay. default is 4. + * tRP : the read pulse width. + * Specified by the HW_GPMI_TIMING0:DATA_SETUP: + * tRP = (GPMI-clock-period) * DATA_SETUP + * + * 4.2) From the aspect of the GPMI nand controller: + * Delay = RDN_DELAY * 0.125 * RP {2} + * + * RP : the DLL reference period. + * if (GPMI-clock-period > DLL_THRETHOLD) + * RP = GPMI-clock-period / 2; + * else + * RP = GPMI-clock-period; + * + * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period + * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD + * is 16ns, but in mx6q, we use 12ns. + * + * 4.3) since {1} equals {2}, we get: + * + * (tREA + 4 - tRP) * 8 + * RDN_DELAY = --------------------- {3} + * RP + * + * 4.4) We only support the fastest asynchronous mode of ONFI nand. + * For some ONFI nand, the mode 4 is the fastest mode; + * while for some ONFI nand, the mode 5 is the fastest mode. + * So we only support the mode 4 and mode 5. It is no need to + * support other modes. + */ +static void gpmi_compute_edo_timing(struct gpmi_nand_data *this, + struct gpmi_nfc_hardware_timing *hw) +{ + struct resources *r = &this->resources; + unsigned long rate = clk_get_rate(r->clock[0]); + int mode = this->timing_mode; + int dll_threshold = 16; /* in ns */ + unsigned long delay; + unsigned long clk_period; + int t_rea; + int c = 4; + int t_rp; + int rp; + + /* + * [1] for GPMI_HW_GPMI_TIMING0: + * The async mode requires 40MHz for mode 4, 50MHz for mode 5. + * The GPMI can support 100MHz at most. So if we want to + * get the 40MHz or 50MHz, we have to set DS=1, DH=1. + * Set the ADDRESS_SETUP to 0 in mode 4. + */ + hw->data_setup_in_cycles = 1; + hw->data_hold_in_cycles = 1; + hw->address_setup_in_cycles = ((mode == 5) ? 1 : 0); + + /* [2] for GPMI_HW_GPMI_TIMING1 */ + hw->device_busy_timeout = 0x9000; + + /* [3] for GPMI_HW_GPMI_CTRL1 */ + hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; + + if (GPMI_IS_MX6Q(this)) + dll_threshold = 12; + + /* + * Enlarge 10 times for the numerator and denominator in {3}. + * This make us to get more accurate result. + */ + clk_period = NSEC_PER_SEC / (rate / 10); + dll_threshold *= 10; + t_rea = ((mode == 5) ? 16 : 20) * 10; + c *= 10; + + t_rp = clk_period * 1; /* DATA_SETUP is 1 */ + + if (clk_period > dll_threshold) { + hw->use_half_periods = 1; + rp = clk_period / 2; + } else { + hw->use_half_periods = 0; + rp = clk_period; + } + + /* + * Multiply the numerator with 10, we could do a round off: + * 7.8 round up to 8; 7.4 round down to 7. + */ + delay = (((t_rea + c - t_rp) * 8) * 10) / rp; + delay = (delay + 5) / 10; + + hw->sample_delay_factor = delay; +} + +static int enable_edo_mode(struct gpmi_nand_data *this, int mode) +{ + struct resources *r = &this->resources; + struct nand_chip *nand = &this->nand; + struct mtd_info *mtd = &this->mtd; + uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {}; + unsigned long rate; + int ret; + + nand->select_chip(mtd, 0); + + /* [1] send SET FEATURE commond to NAND */ + feature[0] = mode; + ret = nand->onfi_set_features(mtd, nand, + ONFI_FEATURE_ADDR_TIMING_MODE, feature); + if (ret) + goto err_out; + + /* [2] send GET FEATURE command to double-check the timing mode */ + memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN); + ret = nand->onfi_get_features(mtd, nand, + ONFI_FEATURE_ADDR_TIMING_MODE, feature); + if (ret || feature[0] != mode) + goto err_out; + + nand->select_chip(mtd, -1); + + /* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */ + rate = (mode == 5) ? 100000000 : 80000000; + clk_set_rate(r->clock[0], rate); + + this->flags |= GPMI_ASYNC_EDO_ENABLED; + this->timing_mode = mode; + dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode); + return 0; + +err_out: + nand->select_chip(mtd, -1); + dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode); + return -EINVAL; +} + +int gpmi_extra_init(struct gpmi_nand_data *this) +{ + struct nand_chip *chip = &this->nand; + + /* Enable the asynchronous EDO feature. */ + if (GPMI_IS_MX6Q(this) && chip->onfi_version) { + int mode = onfi_get_async_timing_mode(chip); + + /* We only support the timing mode 4 and mode 5. */ + if (mode & ONFI_TIMING_MODE_5) + mode = 5; + else if (mode & ONFI_TIMING_MODE_4) + mode = 4; + else + return 0; + + return enable_edo_mode(this, mode); + } + return 0; +} + /* Begin the I/O */ void gpmi_begin(struct gpmi_nand_data *this) { @@ -755,7 +964,10 @@ void gpmi_begin(struct gpmi_nand_data *this) goto err_out; } - gpmi_nfc_compute_hardware_timing(this, &hw); + if (this->flags & GPMI_ASYNC_EDO_ENABLED) + gpmi_compute_edo_timing(this, &hw); + else + gpmi_nfc_compute_hardware_timing(this, &hw); /* [1] Set HW_GPMI_TIMING0 */ reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) | diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 2bfd44876f81..d79696b2f19b 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -1517,6 +1517,14 @@ static int gpmi_scan_bbt(struct mtd_info *mtd) if (ret) return ret; + /* + * Can we enable the extra features? such as EDO or Sync mode. + * + * We do not check the return value now. That's means if we fail in + * enable the extra features, we still can run in the normal way. + */ + gpmi_extra_init(this); + /* use the default BBT implementation */ return nand_default_bbt(mtd); } diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 5c11e761a32e..5b6d546711a6 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -122,6 +122,10 @@ struct nand_timing { }; struct gpmi_nand_data { + /* flags */ +#define GPMI_ASYNC_EDO_ENABLED (1 << 0) + int flags; + /* System Interface */ struct device *dev; struct platform_device *pdev; @@ -132,6 +136,7 @@ struct gpmi_nand_data { /* Flash Hardware */ struct nand_timing timing; + int timing_mode; /* BCH */ struct bch_geometry bch_geometry; @@ -259,6 +264,7 @@ extern int start_dma_with_bch_irq(struct gpmi_nand_data *, /* GPMI-NAND helper function library */ extern int gpmi_init(struct gpmi_nand_data *); +extern int gpmi_extra_init(struct gpmi_nand_data *); extern void gpmi_clear_bch(struct gpmi_nand_data *); extern void gpmi_dump_info(struct gpmi_nand_data *); extern int bch_set_geometry(struct gpmi_nand_data *); -- cgit v1.2.3 From 9c95f11b9e743aa6134134a6dcf866a9d5661972 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Thu, 13 Sep 2012 14:58:00 +0800 Subject: mtd: gpmi: initialize the timing registers only one time The current code initializes the timing registers at very time we call the gpmi_begin(). This really wastes the cpu cycles. Add a new flag to let the gpmi driver initializes the timing registers only one time. Signed-off-by: Huang Shijie Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 8 ++++++++ drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 1 + 2 files changed, 9 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index c036e51f3200..3502accd4bc3 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -914,6 +914,9 @@ static int enable_edo_mode(struct gpmi_nand_data *this, int mode) rate = (mode == 5) ? 100000000 : 80000000; clk_set_rate(r->clock[0], rate); + /* Let the gpmi_begin() re-compute the timing again. */ + this->flags &= ~GPMI_TIMING_INIT_OK; + this->flags |= GPMI_ASYNC_EDO_ENABLED; this->timing_mode = mode; dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode); @@ -964,6 +967,11 @@ void gpmi_begin(struct gpmi_nand_data *this) goto err_out; } + /* Only initialize the timing once */ + if (this->flags & GPMI_TIMING_INIT_OK) + return; + this->flags |= GPMI_TIMING_INIT_OK; + if (this->flags & GPMI_ASYNC_EDO_ENABLED) gpmi_compute_edo_timing(this, &hw); else diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 5b6d546711a6..7ac25c1e58f9 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -124,6 +124,7 @@ struct nand_timing { struct gpmi_nand_data { /* flags */ #define GPMI_ASYNC_EDO_ENABLED (1 << 0) +#define GPMI_TIMING_INIT_OK (1 << 1) int flags; /* System Interface */ -- cgit v1.2.3 From e5570f0c873e3be68a66b479308f21d2dc280a1c Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Sat, 15 Sep 2012 00:41:09 +0200 Subject: mtd: docg4: add missing HAS_IOMEM dependency While building an allyesconfig for UML I received this error message(s): drivers/mtd/nand/docg4.c: In function 'probe_docg4': drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function 'ioremap' [-Werror=implicit-function-declaration] drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from integer without a cast [enabled by default] drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function 'iounmap' [-Werror=implicit-function-declaration] which is caused by the missing implementations on UML. This patch adds this missing HAS_IOMEM dependency and prevents the driver from being build on platforms with no HAS_IOMEM Signed-off-by: Peter Huewe Acked-by: Mike Dunn Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index baa343634819..4883139460be 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -331,7 +331,7 @@ config MTD_NAND_DISKONCHIP_BBTWRITE config MTD_NAND_DOCG4 tristate "Support for DiskOnChip G4 (EXPERIMENTAL)" - depends on EXPERIMENTAL + depends on EXPERIMENTAL && HAS_IOMEM select BCH select BITREVERSE help -- cgit v1.2.3 From 47450b35915c45309974c74f11c2d236db1b950f Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:47 -0700 Subject: mtd: nand: remove unnecessary variable We don't actually use the 'ret' variable; we set it, test it, and then it dies. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index d06a80d4ee75..d4107848ec0a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2916,7 +2916,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int i, maf_idx; u8 id_data[8]; - int ret; /* Select the device */ chip->select_chip(mtd, 0); @@ -2963,8 +2962,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->onfi_version = 0; if (!type->name || !type->pagesize) { /* Check is chip is ONFI compliant */ - ret = nand_flash_detect_onfi(mtd, chip, &busw); - if (ret) + if (nand_flash_detect_onfi(mtd, chip, &busw)) goto ident_done; } -- cgit v1.2.3 From 4aef9b78de057349ad9d620851b14800af0b962c Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:48 -0700 Subject: mtd: nand: remove redundant ID read Instead of reading 2 bytes then later 8 bytes, we can simply read all 8 bytes from the start. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index d4107848ec0a..77b340068c6e 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2942,7 +2942,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); - for (i = 0; i < 2; i++) + /* Read entire ID string */ + for (i = 0; i < 8; i++) id_data[i] = chip->read_byte(mtd); if (id_data[0] != *maf_id || id_data[1] != *dev_id) { @@ -2966,13 +2967,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, goto ident_done; } - chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); - - /* Read entire ID string */ - - for (i = 0; i < 8; i++) - id_data[i] = chip->read_byte(mtd); - if (!type->name) return ERR_PTR(-ENODEV); -- cgit v1.2.3 From 7e74c2d7141e8929049233e28c74cd089f6ae962 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:49 -0700 Subject: mtd: nand: split BB marker options decoding into its own function When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits the bad block marker options detection into its own function, away from the other parameters (e.g., chip size, page size, etc.). Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 66 ++++++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 27 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 77b340068c6e..16bb17f93997 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2905,6 +2905,43 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } +/* + * Set the bad block marker/indicator (BBM/BBI) patterns according to some + * heuristic patterns using various detected parameters (e.g., manufacturer, + * page size, cell-type information). + */ +static void nand_decode_bbm_options(struct mtd_info *mtd, + struct nand_chip *chip, u8 id_data[8]) +{ + int maf_id = id_data[0]; + + /* Set the bad block position */ + if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) + chip->badblockpos = NAND_LARGE_BADBLOCK_POS; + else + chip->badblockpos = NAND_SMALL_BADBLOCK_POS; + + /* + * Bad block marker is stored in the last page of each block on Samsung + * and Hynix MLC devices; stored in first two pages of each block on + * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, + * AMD/Spansion, and Macronix. All others scan only the first page. + */ + if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + (maf_id == NAND_MFR_SAMSUNG || + maf_id == NAND_MFR_HYNIX)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + (maf_id == NAND_MFR_SAMSUNG || + maf_id == NAND_MFR_HYNIX || + maf_id == NAND_MFR_TOSHIBA || + maf_id == NAND_MFR_AMD || + maf_id == NAND_MFR_MACRONIX)) || + (mtd->writesize == 2048 && + maf_id == NAND_MFR_MICRON)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; +} + /* * Get the flash and manufacturer id and lookup if the type is supported. */ @@ -3087,6 +3124,8 @@ ident_done: return ERR_PTR(-EINVAL); } + nand_decode_bbm_options(mtd, chip, id_data); + /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; /* Convert chipsize to number of pages per chip -1 */ @@ -3103,33 +3142,6 @@ ident_done: chip->badblockbits = 8; - /* Set the bad block position */ - if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16)) - chip->badblockpos = NAND_LARGE_BADBLOCK_POS; - else - chip->badblockpos = NAND_SMALL_BADBLOCK_POS; - - /* - * Bad block marker is stored in the last page of each block - * on Samsung and Hynix MLC devices; stored in first two pages - * of each block on Micron devices with 2KiB pages and on - * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix. - * All others scan only the first page. - */ - if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && - (*maf_id == NAND_MFR_SAMSUNG || - *maf_id == NAND_MFR_HYNIX)) - chip->bbt_options |= NAND_BBT_SCANLASTPAGE; - else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && - (*maf_id == NAND_MFR_SAMSUNG || - *maf_id == NAND_MFR_HYNIX || - *maf_id == NAND_MFR_TOSHIBA || - *maf_id == NAND_MFR_AMD || - *maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && - *maf_id == NAND_MFR_MICRON)) - chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; - /* Check for AND chips with 4 page planes */ if (chip->options & NAND_4PAGE_ARRAY) chip->erase_cmd = multi_erase_cmd; -- cgit v1.2.3 From fc09bbc04ccd7f069c1928a0156968b888393833 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:50 -0700 Subject: mtd: nand: split extended ID decoding into its own function When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the extended ID decode functionality, which handles decoding the 3rd-8th ID bytes to determine NAND device parameters. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 122 ++++++++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 55 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 16bb17f93997..e017af02da1c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2905,6 +2905,71 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } +/* + * Many new NAND share similar device ID codes, which represent the size of the + * chip. The rest of the parameters must be decoded according to generic or + * manufacturer-specific "extended ID" decoding patterns. + */ +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, + u8 id_data[8], int *busw) +{ + int extid; + /* The 3rd id byte holds MLC / multichip data */ + chip->cellinfo = id_data[2]; + /* The 4th id byte is the important one */ + extid = id_data[3]; + + /* + * Field definitions are in the following datasheets: + * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) + * New style (6 byte ID): Samsung K9GBG08U0M (p.40) + * + * Check for wraparound + Samsung ID + nonzero 6th byte + * to decide what to do. + */ + if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && + id_data[0] == NAND_MFR_SAMSUNG && + (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + id_data[5] != 0x00) { + /* Calc pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + switch (extid & 0x03) { + case 1: + mtd->oobsize = 128; + break; + case 2: + mtd->oobsize = 218; + break; + case 3: + mtd->oobsize = 400; + break; + default: + mtd->oobsize = 436; + break; + } + extid >>= 2; + /* Calc blocksize */ + mtd->erasesize = (128 * 1024) << + (((extid >> 1) & 0x04) | (extid & 0x03)); + *busw = 0; + } else { + /* Calc pagesize */ + mtd->writesize = 1024 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + } +} + /* * Set the bad block marker/indicator (BBM/BBI) patterns according to some * heuristic patterns using various detected parameters (e.g., manufacturer, @@ -3016,61 +3081,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Set the pagesize, oobsize, erasesize by the driver */ busw = chip->init_size(mtd, chip, id_data); } else if (!type->pagesize) { - int extid; - /* The 3rd id byte holds MLC / multichip data */ - chip->cellinfo = id_data[2]; - /* The 4th id byte is the important one */ - extid = id_data[3]; - - /* - * Field definitions are in the following datasheets: - * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * New style (6 byte ID): Samsung K9GBG08U0M (p.40) - * - * Check for wraparound + Samsung ID + nonzero 6th byte - * to decide what to do. - */ - if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && - id_data[0] == NAND_MFR_SAMSUNG && - (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && - id_data[5] != 0x00) { - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (extid & 0x03) { - case 1: - mtd->oobsize = 128; - break; - case 2: - mtd->oobsize = 218; - break; - case 3: - mtd->oobsize = 400; - break; - default: - mtd->oobsize = 436; - break; - } - extid >>= 2; - /* Calc blocksize */ - mtd->erasesize = (128 * 1024) << - (((extid >> 1) & 0x04) | (extid & 0x03)); - busw = 0; - } else { - /* Calc pagesize */ - mtd->writesize = 1024 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * - (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; - } + /* Decode parameters from extended ID */ + nand_decode_ext_id(mtd, chip, id_data, &busw); } else { /* * Old devices have chip data hardcoded in the device id table. -- cgit v1.2.3 From f23a481c4e0ccb006470b1c890cc7236ba634e67 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:51 -0700 Subject: mtd: nand: split simple ID decode into its own function When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the simple ID decode functionality, where all the information regarding NAND size/blocksize/pagesize/oobsize/busw is encoded in the first two bytes of the ID string. Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 51 +++++++++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 20 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index e017af02da1c..4e1ea7283a95 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2970,6 +2970,36 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, } } +/* + * Old devices have chip data hardcoded in the device ID table. nand_decode_id + * decodes a matching ID table entry and assigns the MTD size parameters for + * the chip. + */ +static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, + struct nand_flash_dev *type, u8 id_data[8], + int *busw) +{ + int maf_id = id_data[0]; + + mtd->erasesize = type->erasesize; + mtd->writesize = type->pagesize; + mtd->oobsize = mtd->writesize / 32; + *busw = type->options & NAND_BUSWIDTH_16; + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table. + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 + && id_data[6] == 0x00 && id_data[7] == 0x00 + && mtd->writesize == 512) { + mtd->erasesize = 128 * 1024; + mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + } +} + /* * Set the bad block marker/indicator (BBM/BBI) patterns according to some * heuristic patterns using various detected parameters (e.g., manufacturer, @@ -3084,26 +3114,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Decode parameters from extended ID */ nand_decode_ext_id(mtd, chip, id_data, &busw); } else { - /* - * Old devices have chip data hardcoded in the device id table. - */ - mtd->erasesize = type->erasesize; - mtd->writesize = type->pagesize; - mtd->oobsize = mtd->writesize / 32; - busw = type->options & NAND_BUSWIDTH_16; - - /* - * Check for Spansion/AMD ID + repeating 5th, 6th byte since - * some Spansion chips have erasesize that conflicts with size - * listed in nand_ids table. - * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) - */ - if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && - id_data[5] == 0x00 && id_data[6] == 0x00 && - id_data[7] == 0x00 && mtd->writesize == 512) { - mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); - } + nand_decode_id(mtd, chip, type, id_data, &busw); } /* Get chip options */ chip->options |= type->options; -- cgit v1.2.3 From e3b88bd604283ef83ae6e8f53622d5b1ffe9d43a Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:52 -0700 Subject: mtd: nand: add generic READ ID length calculation functions When decoding the extended ID bytes of a NAND chip, we have to calculate the ID length according to some heuristic patterns (e.g., Does the ID wrap around? Does it end in trailing zeros?). Currently, these heuristics are built into complicated if/else blocks that can be hard to understand. Now, these checks can be done generically in a function, making them more robust and reusable. In fact, this sort of calculation is needed in future additions to nand_base.c. And with this advancement, we get the added benefit of a more readable "extended ID decode". Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 72 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 65 insertions(+), 7 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 4e1ea7283a95..5365ad569f5a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2905,6 +2905,65 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } +/* + * nand_id_has_period - Check if an ID string has a given wraparound period + * @id_data: the ID string + * @arrlen: the length of the @id_data array + * @period: the period of repitition + * + * Check if an ID string is repeated within a given sequence of bytes at + * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a + * period of 2). This is a helper function for nand_id_len(). Returns non-zero + * if the repetition has a period of @period; otherwise, returns zero. + */ +static int nand_id_has_period(u8 *id_data, int arrlen, int period) +{ + int i, j; + for (i = 0; i < period; i++) + for (j = i + period; j < arrlen; j += period) + if (id_data[i] != id_data[j]) + return 0; + return 1; +} + +/* + * nand_id_len - Get the length of an ID string returned by CMD_READID + * @id_data: the ID string + * @arrlen: the length of the @id_data array + + * Returns the length of the ID string, according to known wraparound/trailing + * zero patterns. If no pattern exists, returns the length of the array. + */ +static int nand_id_len(u8 *id_data, int arrlen) +{ + int last_nonzero, period; + + /* Find last non-zero byte */ + for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) + if (id_data[last_nonzero]) + break; + + /* All zeros */ + if (last_nonzero < 0) + return 0; + + /* Calculate wraparound period */ + for (period = 1; period < arrlen; period++) + if (nand_id_has_period(id_data, arrlen, period)) + break; + + /* There's a repeated pattern */ + if (period < arrlen) + return period; + + /* There are trailing zeros */ + if (last_nonzero < arrlen - 1) + return last_nonzero + 1; + + /* No pattern detected */ + return arrlen; +} + /* * Many new NAND share similar device ID codes, which represent the size of the * chip. The rest of the parameters must be decoded according to generic or @@ -2913,24 +2972,23 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, u8 id_data[8], int *busw) { - int extid; + int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ chip->cellinfo = id_data[2]; /* The 4th id byte is the important one */ extid = id_data[3]; + id_len = nand_id_len(id_data, 8); + /* * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) * New style (6 byte ID): Samsung K9GBG08U0M (p.40) * - * Check for wraparound + Samsung ID + nonzero 6th byte - * to decide what to do. + * Check for ID length + Samsung ID to decide what to do. */ - if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && - id_data[0] == NAND_MFR_SAMSUNG && - (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && - id_data[5] != 0x00) { + if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && + (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; -- cgit v1.2.3 From 73ca392f7d4a175dcf7b56a3c35efc92a55a5473 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:54 -0700 Subject: mtd: nand: decode Hynix MLC, 6-byte ID length Hynix has introduced a new ID decoding scheme for their newer MLC, some of which don't support ONFI. The following devices all follow the pattern given in the datasheet for Hynix H27UBG8T2B, p.22: Hynix H27UAG8T2A Hynix H27UBG8T2A Hynix H27UBG8T2B Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 45 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 5365ad569f5a..304765140634 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2984,8 +2984,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) * New style (6 byte ID): Samsung K9GBG08U0M (p.40) + * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) * - * Check for ID length + Samsung ID to decide what to do. + * Check for ID length, cell type, and Hynix/Samsung ID to decide what + * to do. */ if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { @@ -3012,6 +3014,47 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); *busw = 0; + } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { + unsigned int tmp; + + /* Calc pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + switch (((extid >> 2) & 0x04) | (extid & 0x03)) { + case 0: + mtd->oobsize = 128; + break; + case 1: + mtd->oobsize = 224; + break; + case 2: + mtd->oobsize = 448; + break; + case 3: + mtd->oobsize = 64; + break; + case 4: + mtd->oobsize = 32; + break; + case 5: + mtd->oobsize = 16; + break; + default: + mtd->oobsize = 640; + break; + } + extid >>= 2; + /* Calc blocksize */ + tmp = ((extid >> 1) & 0x04) | (extid & 0x03); + if (tmp < 0x03) + mtd->erasesize = (128 * 1024) << tmp; + else if (tmp == 0x03) + mtd->erasesize = 768 * 1024; + else + mtd->erasesize = (64 * 1024) << tmp; + *busw = 0; } else { /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); -- cgit v1.2.3 From e2d3a35ee427aaba99b6c68a56609ce276c51270 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 24 Sep 2012 20:40:55 -0700 Subject: mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID Datasheets for the following Samsung NAND parts (both MLC and SLC) describe extensions to the Samsung 6-byte extended ID decoding table: K9GBG08U0A (MLC, 6-byte ID) K9GAG08U0F (MLC, 6-byte ID) K9FAG08U0M (SLC, 6-byte ID) The table found in K9GAG08U0F, p.44, contains a superset of the information found in other previous datasheets. This patch adds support for all of these chips, with 512B and 640B OOB sizes. It also changes the detection pattern such that this table applies to all Samsung 6-byte ID NAND, not just MLC. This is safe, according to the NAND parameter data I have collected: Note that nand_base.c does not yet support the bad block marker scheme defined for these chips (i.e., scan 1st and last page for BB markers). Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 304765140634..ec6841d8e956 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2983,19 +2983,18 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * New style (6 byte ID): Samsung K9GBG08U0M (p.40) + * New style (6 byte ID): Samsung K9GAG08U0F (p.44) * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) * * Check for ID length, cell type, and Hynix/Samsung ID to decide what * to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { + if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; /* Calc oobsize */ - switch (extid & 0x03) { + switch (((extid >> 2) & 0x04) | (extid & 0x03)) { case 1: mtd->oobsize = 128; break; @@ -3005,9 +3004,16 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, case 3: mtd->oobsize = 400; break; - default: + case 4: mtd->oobsize = 436; break; + case 5: + mtd->oobsize = 512; + break; + case 6: + default: /* Other cases are "reserved" (unknown) */ + mtd->oobsize = 640; + break; } extid >>= 2; /* Calc blocksize */ -- cgit v1.2.3