From ef41603d09f124fcebb86bcc4a648ffafbfa120b Mon Sep 17 00:00:00 2001 From: Jacob Keller Date: Wed, 18 Jun 2025 15:24:36 -0700 Subject: ice: add support for reading and unpacking Rx queue context In order to support live migration, the ice driver will need to read certain data from the Rx queue context. This is stored in the hardware in a packed format. Since we use for the mapping between the packed hardware format and the unpacked structure, it is trivial to enable unpacking support via the unpack_fields() function. Add the ice_unpack_rxq_ctx() function based on the unpack_fields() API. Re-use the same field definitions from the packing implementation. Add ice_copy_rxq_ctx_from_hw() to copy the Rx queue context data from the hardware registers. Use these to implement ice_read_rxq_ctx() which will return the Rx queue context to the caller in its unpacked ice_rlan_ctx struct. This will enable the migration logic access to the relevant data about the Rx device queues. It can easily be copied to the target system as part of the migration payload, where it will be used to configure the Rx queues. Signed-off-by: Jacob Keller Reviewed-by: Madhu Chittim Reviewed-by: Przemek Kitszel Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_common.c | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'drivers/net/ethernet/intel/ice/ice_common.c') diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index 84cd8c6dcf39..ddde3487aea9 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -1342,6 +1342,26 @@ static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, } } +/** + * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers + * @hw: pointer to the hardware structure + * @rxq_ctx: pointer to the packed Rx queue context + * @rxq_index: the index of the Rx queue + */ +static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, + ice_rxq_ctx_buf_t *rxq_ctx, + u32 rxq_index) +{ + u32 *ctx = (u32 *)rxq_ctx; + + /* Copy each dword separately from HW */ + for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { + *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); + + ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); + } +} + #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) @@ -1385,6 +1405,21 @@ static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); } +/** + * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer + * @buf: the HW buffer to unpack from + * @ctx: the Rx queue context to unpack + * + * Unpack the Rx queue context from the HW buffer into the CPU-friendly + * structure. + */ +static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, + struct ice_rlan_ctx *ctx) +{ + unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, + QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); +} + /** * ice_write_rxq_ctx - Write Rx Queue context to hardware * @hw: pointer to the hardware structure @@ -1410,6 +1445,31 @@ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, return 0; } +/** + * ice_read_rxq_ctx - Read Rx queue context from HW + * @hw: pointer to the hardware structure + * @rlan_ctx: pointer to the Rx queue context + * @rxq_index: the index of the Rx queue + * + * Read the Rx queue context from the hardware registers, and unpack it into + * the sparse Rx queue context structure. + * + * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. + */ +int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index) +{ + ice_rxq_ctx_buf_t buf = {}; + + if (rxq_index > QRX_CTRL_MAX_INDEX) + return -EINVAL; + + ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); + ice_unpack_rxq_ctx(&buf, rlan_ctx); + + return 0; +} + /* LAN Tx Queue Context */ static const struct packed_field_u8 ice_tlan_ctx_fields[] = { /* Field Width LSB */ -- cgit v1.2.3 From b6f82e9b79b1b0d6eb8861502c6069b7cdff03f9 Mon Sep 17 00:00:00 2001 From: Jacob Keller Date: Wed, 18 Jun 2025 15:24:37 -0700 Subject: ice: add functions to get and set Tx queue context The live migration driver will need to save and restore the Tx queue context state from the hardware registers. This state contains both static fields which do not change during Tx traffic as well as dynamic fields which may change during Tx traffic. Unlike the Rx context, the Tx queue context is accessed indirectly from GLCOMM_QTX_CNTX_CTL and GLCOMM_QTX_CNTX_DATA registers. These registers are shared by multiple PFs on the same PCIe card. Multiple PFs cannot safely access the registers simultaneously, and there is no hardware semaphore or logic to control access. To handle this, introduce the txq_ctx_lock to the ice_adapter structure. This is similar to the ptp_gltsyn_time_lock. All PFs on the same adapter share this structure, and use it to serialize access to the registers to prevent error. Add a new functions to get and set the Tx queue context through the GLCOMM_QTX_CNTX_CTL interface. The hardware context values are stored in the registers using the same packed format as the Admin Queue buffer. The hardware buffer is 40 bytes wide, as it contains an additional 18 bytes of internal state not sent with the Admin Queue buffer. For this reason, a separate typedef and packing function must be used. We can share the same packed fields definitions because we never need to unpack the internal state. This is preferred, as it ensures the internal state is zero'd when writing into HW, and avoids issues with reading by u32 registers into a buffer of 22 bytes in length. Thanks to the typedefs, misuse of the API with the wrong size buffer can easily be caught at compile time. Note reading this data from hardware is essential because the current Tx queue context may be different from the context as initially programmed by the driver during VF initialization. When migrating a VF we must ensure the target VF has identical context as the source VF did. Co-developed-by: Yahui Cao Signed-off-by: Yahui Cao Signed-off-by: Jacob Keller Reviewed-by: Madhu Chittim Reviewed-by: Przemek Kitszel Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_common.c | 173 +++++++++++++++++++++++++++- 1 file changed, 170 insertions(+), 3 deletions(-) (limited to 'drivers/net/ethernet/intel/ice/ice_common.c') diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index ddde3487aea9..1b435e108d3c 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -1503,12 +1503,12 @@ static const struct packed_field_u8 ice_tlan_ctx_fields[] = { }; /** - * ice_pack_txq_ctx - Pack Tx queue context into a HW buffer + * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer * @ctx: the Tx queue context to pack - * @buf: the HW buffer to pack into + * @buf: the Admin Queue HW buffer to pack into * * Pack the Tx queue context from the CPU-friendly unpacked buffer into its - * bit-packed HW layout. + * bit-packed Admin Queue layout. */ void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) { @@ -1516,6 +1516,173 @@ void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); } +/** + * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer + * @ctx: the Tx queue context to pack + * @buf: the HW buffer to pack into + * + * Pack the Tx queue context from the CPU-friendly unpacked buffer into its + * bit-packed HW layout, including the internal data portion. + */ +static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, + ice_txq_ctx_buf_full_t *buf) +{ + pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, + QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); +} + +/** + * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer + * @buf: the HW buffer to unpack from + * @ctx: the Tx queue context to unpack + * + * Unpack the Tx queue context from the HW buffer (including the full internal + * state) into the CPU-friendly structure. + */ +static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, + struct ice_tlan_ctx *ctx) +{ + unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, + QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); +} + +/** + * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers + * @hw: pointer to the hardware structure + * @txq_ctx: pointer to the packed Tx queue context, including internal state + * @txq_index: the index of the Tx queue + * + * Copy Tx Queue context from HW register space to dense structure + */ +static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, + ice_txq_ctx_buf_full_t *txq_ctx, + u32 txq_index) +{ + struct ice_pf *pf = container_of(hw, struct ice_pf, hw); + u32 *ctx = (u32 *)txq_ctx; + u32 txq_base, reg; + + /* Get Tx queue base within card space */ + txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); + txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); + + reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, + GLCOMM_QTX_CNTX_CTL_CMD_READ) | + FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, + txq_base + txq_index) | + GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; + + /* Prevent other PFs on the same adapter from accessing the Tx queue + * context interface concurrently. + */ + spin_lock(&pf->adapter->txq_ctx_lock); + + wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); + ice_flush(hw); + + /* Copy each dword separately from HW */ + for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { + *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); + + ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); + } + + spin_unlock(&pf->adapter->txq_ctx_lock); +} + +/** + * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers + * @hw: pointer to the hardware structure + * @txq_ctx: pointer to the packed Tx queue context, including internal state + * @txq_index: the index of the Tx queue + */ +static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, + const ice_txq_ctx_buf_full_t *txq_ctx, + u32 txq_index) +{ + struct ice_pf *pf = container_of(hw, struct ice_pf, hw); + u32 txq_base, reg; + + /* Get Tx queue base within card space */ + txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); + txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); + + reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, + GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | + FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, + txq_base + txq_index) | + GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; + + /* Prevent other PFs on the same adapter from accessing the Tx queue + * context interface concurrently. + */ + spin_lock(&pf->adapter->txq_ctx_lock); + + /* Copy each dword separately to HW */ + for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { + u32 ctx = ((const u32 *)txq_ctx)[i]; + + wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); + + ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); + } + + wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); + ice_flush(hw); + + spin_unlock(&pf->adapter->txq_ctx_lock); +} + +/** + * ice_read_txq_ctx - Read Tx queue context from HW + * @hw: pointer to the hardware structure + * @tlan_ctx: pointer to the Tx queue context + * @txq_index: the index of the Tx queue + * + * Read the Tx queue context from the HW registers, then unpack it into the + * ice_tlan_ctx structure for use. + * + * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. + */ +int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, + u32 txq_index) +{ + ice_txq_ctx_buf_full_t buf = {}; + + if (txq_index > QTX_COMM_HEAD_MAX_INDEX) + return -EINVAL; + + ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); + ice_unpack_txq_ctx_full(&buf, tlan_ctx); + + return 0; +} + +/** + * ice_write_txq_ctx - Write Tx queue context to HW + * @hw: pointer to the hardware structure + * @tlan_ctx: pointer to the Tx queue context + * @txq_index: the index of the Tx queue + * + * Pack the Tx queue context into the dense HW layout, then write it into the + * HW registers. + * + * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. + */ +int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, + u32 txq_index) +{ + ice_txq_ctx_buf_full_t buf = {}; + + if (txq_index > QTX_COMM_HEAD_MAX_INDEX) + return -EINVAL; + + ice_pack_txq_ctx_full(tlan_ctx, &buf); + ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); + + return 0; +} + /* Sideband Queue command wrappers */ /** -- cgit v1.2.3