From 115ddc491922c3c133551e9cff2d3bfaed02a27e Mon Sep 17 00:00:00 2001 From: Alexander Duyck Date: Tue, 24 Apr 2018 16:47:22 -0500 Subject: net: ena: Use pci_sriov_configure_simple() to enable VFs Instead of implementing our own version of a SR-IOV configuration stub in the ena driver, use the existing pci_sriov_configure_simple() function. Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas Reviewed-by: Greg Rose Reviewed-by: Christoph Hellwig --- drivers/net/ethernet/amazon/ena/ena_netdev.c | 28 +--------------------------- 1 file changed, 1 insertion(+), 27 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c index a822e70c2af3..f2af87d70594 100644 --- a/drivers/net/ethernet/amazon/ena/ena_netdev.c +++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c @@ -3385,32 +3385,6 @@ err_disable_device: return rc; } -/*****************************************************************************/ -static int ena_sriov_configure(struct pci_dev *dev, int numvfs) -{ - int rc; - - if (numvfs > 0) { - rc = pci_enable_sriov(dev, numvfs); - if (rc != 0) { - dev_err(&dev->dev, - "pci_enable_sriov failed to enable: %d vfs with the error: %d\n", - numvfs, rc); - return rc; - } - - return numvfs; - } - - if (numvfs == 0) { - pci_disable_sriov(dev); - return 0; - } - - return -EINVAL; -} - -/*****************************************************************************/ /*****************************************************************************/ /* ena_remove - Device Removal Routine @@ -3526,7 +3500,7 @@ static struct pci_driver ena_pci_driver = { .suspend = ena_suspend, .resume = ena_resume, #endif - .sriov_configure = ena_sriov_configure, + .sriov_configure = pci_sriov_configure_simple, }; static int __init ena_init(void) -- cgit v1.2.3 From cc04a1dd3f4af21d1a2cd3715e7b337b470a693d Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 30 Mar 2018 13:09:04 -0500 Subject: bnx2x: Report PCIe link properties with pcie_print_link_status() Previously the driver used pcie_get_minimum_link() to warn when the NIC is in a slot that can't supply as much bandwidth as the NIC could use. pcie_get_minimum_link() can be misleading because it finds the slowest link and the narrowest link (which may be different links) without considering the total bandwidth of each link. For a path with a 16 GT/s x1 link and a 2.5 GT/s x16 link, it returns 2.5 GT/s x1, which corresponds to 250 MB/s of bandwidth, not the true available bandwidth of about 1969 MB/s for a 16 GT/s x1 link. Use pcie_print_link_status() to report PCIe link speed and possible limitations instead of implementing this in the driver itself. This finds the slowest link in the path to the device by computing the total bandwidth of each link and compares that with the capabilities of the device. The dmesg change is: - %s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM + %s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM + %u.%03u Gb/s available PCIe bandwidth (%s x%d link) Signed-off-by: Bjorn Helgaas --- drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index c766ae23bc74..5b1ed240bf18 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -13922,8 +13922,6 @@ static int bnx2x_init_one(struct pci_dev *pdev, { struct net_device *dev = NULL; struct bnx2x *bp; - enum pcie_link_width pcie_width; - enum pci_bus_speed pcie_speed; int rc, max_non_def_sbs; int rx_count, tx_count, rss_count, doorbell_size; int max_cos_est; @@ -14091,21 +14089,12 @@ static int bnx2x_init_one(struct pci_dev *pdev, dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); rtnl_unlock(); } - if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) || - pcie_speed == PCI_SPEED_UNKNOWN || - pcie_width == PCIE_LNK_WIDTH_UNKNOWN) - BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n"); - else - BNX2X_DEV_INFO( - "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", - board_info[ent->driver_data].name, - (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), - pcie_width, - pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" : - pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" : - pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" : - "Unknown", - dev->base_addr, bp->pdev->irq, dev->dev_addr); + BNX2X_DEV_INFO( + "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n", + board_info[ent->driver_data].name, + (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), + dev->base_addr, bp->pdev->irq, dev->dev_addr); + pcie_print_link_status(bp->pdev); bnx2x_register_phc(bp); -- cgit v1.2.3 From af125b754e2f09e6061e65db8f4eda0f7730011d Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 30 Mar 2018 14:09:54 -0500 Subject: bnxt_en: Report PCIe link properties with pcie_print_link_status() Previously the driver used pcie_get_minimum_link() to warn when the NIC is in a slot that can't supply as much bandwidth as the NIC could use. pcie_get_minimum_link() can be misleading because it finds the slowest link and the narrowest link (which may be different links) without considering the total bandwidth of each link. For a path with a 16 GT/s x1 link and a 2.5 GT/s x16 link, it returns 2.5 GT/s x1, which corresponds to 250 MB/s of bandwidth, not the true available bandwidth of about 1969 MB/s for a 16 GT/s x1 link. Use pcie_print_link_status() to report PCIe link speed and possible limitations instead of implementing this in the driver itself. This finds the slowest link in the path to the device by computing the total bandwidth of each link and compares that with the capabilities of the device. The dmesg change is: - PCIe: Speed %s Width x%d + %u.%03u Gb/s available PCIe bandwidth (%s x%d link) Signed-off-by: Bjorn Helgaas --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index f83769d8047b..34fddb48fecc 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -8621,22 +8621,6 @@ static int bnxt_init_mac_addr(struct bnxt *bp) return rc; } -static void bnxt_parse_log_pcie_link(struct bnxt *bp) -{ - enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; - enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; - - if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) || - speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) - netdev_info(bp->dev, "Failed to determine PCIe Link Info\n"); - else - netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n", - speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : - speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : - speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : - "Unknown", width); -} - static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { static int version_printed; @@ -8851,8 +8835,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) netdev_info(dev, "%s found at mem %lx, node addr %pM\n", board_info[ent->driver_data].name, (long)pci_resource_start(pdev, 0), dev->dev_addr); - - bnxt_parse_log_pcie_link(bp); + pcie_print_link_status(pdev); return 0; -- cgit v1.2.3 From 57d12fc6f78889677ec49d049fcec35ef8a03c53 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 30 Mar 2018 14:16:06 -0500 Subject: cxgb4: Report PCIe link properties with pcie_print_link_status() Previously the driver used pcie_get_minimum_link() to warn when the NIC is in a slot that can't supply as much bandwidth as the NIC could use. pcie_get_minimum_link() can be misleading because it finds the slowest link and the narrowest link (which may be different links) without considering the total bandwidth of each link. For a path with a 16 GT/s x1 link and a 2.5 GT/s x16 link, it returns 2.5 GT/s x1, which corresponds to 250 MB/s of bandwidth, not the true available bandwidth of about 1969 MB/s for a 16 GT/s x1 link. Use pcie_print_link_status() to report PCIe link speed and possible limitations instead of implementing this in the driver itself. This finds the slowest link in the path to the device by computing the total bandwidth of each link and compares that with the capabilities of the device. The dmesg change is: - PCIe link speed is %s, device supports %s - PCIe link width is x%d, device supports x%d + %u.%03u Gb/s available PCIe bandwidth (%s x%d link) or, if the device is capable of better performance than is available in the current slot: - A slot with more lanes and/or higher speed is suggested for optimal performance. + %u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link) Signed-off-by: Bjorn Helgaas --- drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 75 +------------------------ 1 file changed, 1 insertion(+), 74 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index 24d2865b8806..7328f24ba1dd 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c @@ -5042,79 +5042,6 @@ static int init_rss(struct adapter *adap) return 0; } -static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, - enum pci_bus_speed *speed, - enum pcie_link_width *width) -{ - u32 lnkcap1, lnkcap2; - int err1, err2; - -#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ - - *speed = PCI_SPEED_UNKNOWN; - *width = PCIE_LNK_WIDTH_UNKNOWN; - - err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, - &lnkcap1); - err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, - &lnkcap2); - if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) - *speed = PCIE_SPEED_8_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) - *speed = PCIE_SPEED_5_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) - *speed = PCIE_SPEED_2_5GT; - } - if (!err1) { - *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; - if (!lnkcap2) { /* pre-r3.0 */ - if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) - *speed = PCIE_SPEED_5_0GT; - else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) - *speed = PCIE_SPEED_2_5GT; - } - } - - if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) - return err1 ? err1 : err2 ? err2 : -EINVAL; - return 0; -} - -static void cxgb4_check_pcie_caps(struct adapter *adap) -{ - enum pcie_link_width width, width_cap; - enum pci_bus_speed speed, speed_cap; - -#define PCIE_SPEED_STR(speed) \ - (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ - speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ - speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ - "Unknown") - - if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { - dev_warn(adap->pdev_dev, - "Unable to determine PCIe device BW capabilities\n"); - return; - } - - if (pcie_get_minimum_link(adap->pdev, &speed, &width) || - speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { - dev_warn(adap->pdev_dev, - "Unable to determine PCI Express bandwidth.\n"); - return; - } - - dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", - PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); - dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", - width, width_cap); - if (speed < speed_cap || width < width_cap) - dev_info(adap->pdev_dev, - "A slot with more lanes and/or higher speed is " - "suggested for optimal performance.\n"); -} - /* Dump basic information about the adapter */ static void print_adapter_info(struct adapter *adapter) { @@ -5750,7 +5677,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) } /* check for PCI Express bandwidth capabiltites */ - cxgb4_check_pcie_caps(adapter); + pcie_print_link_status(pdev); err = init_rss(adapter); if (err) -- cgit v1.2.3 From 4695ca9d17a2f47e0be3011ef25a4d77b973b547 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 30 Mar 2018 14:26:07 -0500 Subject: ixgbe: Report PCIe link properties with pcie_print_link_status() Previously the driver used pcie_get_minimum_link() to warn when the NIC is in a slot that can't supply as much bandwidth as the NIC could use. pcie_get_minimum_link() can be misleading because it finds the slowest link and the narrowest link (which may be different links) without considering the total bandwidth of each link. For a path with a 16 GT/s x1 link and a 2.5 GT/s x16 link, it returns 2.5 GT/s x1, which corresponds to 250 MB/s of bandwidth, not the true available bandwidth of about 1969 MB/s for a 16 GT/s x1 link. Use pcie_print_link_status() to report PCIe link speed and possible limitations instead of implementing this in the driver itself. This finds the slowest link in the path to the device by computing the total bandwidth of each link and compares that with the capabilities of the device. The dmesg change is: - PCI Express bandwidth of %dGT/s available - (Speed:%s, Width: x%d, Encoding Loss:%s) + %u.%03u Gb/s available PCIe bandwidth (%s x%d link) or, if the device is capable of better performance than is available in the current slot: - This is not sufficient for optimal performance of this card. - For optimal performance, at least %dGT/s of bandwidth is required. - A slot with more lanes and/or higher speed is suggested. + %u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link) Note that the driver previously used dev_warn() to suggest using a different slot, but pcie_print_link_status() uses dev_info() because if the platform has no faster slot available, the user can't do anything about the warning and may not want to be bothered with it. Signed-off-by: Bjorn Helgaas Acked-by: Jeff Kirsher --- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 47 +-------------------------- 1 file changed, 1 insertion(+), 46 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index afadba99f7b8..8990285f6e12 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -270,9 +270,6 @@ static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, int expected_gts) { struct ixgbe_hw *hw = &adapter->hw; - int max_gts = 0; - enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; - enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; struct pci_dev *pdev; /* Some devices are not connected over PCIe and thus do not negotiate @@ -288,49 +285,7 @@ static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, else pdev = adapter->pdev; - if (pcie_get_minimum_link(pdev, &speed, &width) || - speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { - e_dev_warn("Unable to determine PCI Express bandwidth.\n"); - return; - } - - switch (speed) { - case PCIE_SPEED_2_5GT: - /* 8b/10b encoding reduces max throughput by 20% */ - max_gts = 2 * width; - break; - case PCIE_SPEED_5_0GT: - /* 8b/10b encoding reduces max throughput by 20% */ - max_gts = 4 * width; - break; - case PCIE_SPEED_8_0GT: - /* 128b/130b encoding reduces throughput by less than 2% */ - max_gts = 8 * width; - break; - default: - e_dev_warn("Unable to determine PCI Express bandwidth.\n"); - return; - } - - e_dev_info("PCI Express bandwidth of %dGT/s available\n", - max_gts); - e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", - (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : - speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : - speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : - "Unknown"), - width, - (speed == PCIE_SPEED_2_5GT ? "20%" : - speed == PCIE_SPEED_5_0GT ? "20%" : - speed == PCIE_SPEED_8_0GT ? "<2%" : - "Unknown")); - - if (max_gts < expected_gts) { - e_dev_warn("This is not sufficient for optimal performance of this card.\n"); - e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", - expected_gts); - e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); - } + pcie_print_link_status(pdev); } static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) -- cgit v1.2.3