From e0b047bd8fc73b35ba1081097e0223eb778d982c Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Wed, 10 Jun 2015 03:23:42 -0400 Subject: spi: davinci: change the lower limit of pre-scale divider to 1 SPI hardware spec for Keystone specify a lower value of 0 for pre-scale divider which determine what max value of spi clock (spi-max-frequency) the device can support. This translates to a clock divider of 2. So fix the lower limit value used for the boundary check in davinci_spi_get_prescale() function to 1 so that a maximum of spi device clock rate / 2 is possible to be set for spi-max-frequency. Signed-off-by: Murali Karicheri Acked-by: Sekhar Nori Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi/spi-davinci.c') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 5e991065f5b0..987afebea093 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -265,7 +265,7 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); - if (ret < 3 || ret > 256) + if (ret < 1 || ret > 256) return -EINVAL; return ret - 1; -- cgit v1.2.3