From 088da2a17619cf0113b62a76ad38c6a14470ffa6 Mon Sep 17 00:00:00 2001 From: Peter Hurley Date: Sat, 16 Jan 2016 15:23:43 -0800 Subject: of: earlycon: Initialize port fields from DT properties Read the optional "reg-offset", "reg-shift", "reg-io-width" and endianness properties and initialize the respective struct uart_port field if found. NB: These bindings are common to several drivers and the values merely indicate the default value; the registering earlycon setup() method can simply override the values if required. Acked-by: Rob Herring Signed-off-by: Peter Hurley Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/earlycon.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers/tty/serial/earlycon.c') diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c index 7509ee34de28..7089667bde93 100644 --- a/drivers/tty/serial/earlycon.c +++ b/drivers/tty/serial/earlycon.c @@ -19,6 +19,7 @@ #include #include #include +#include #ifdef CONFIG_FIX_EARLYCON_MEM #include @@ -219,10 +220,13 @@ early_param("earlycon", param_setup_earlycon); int __init of_setup_earlycon(unsigned long addr, const struct earlycon_id *match, + unsigned long node, const char *options) { int err; struct uart_port *port = &early_console_dev.port; + const __be32 *val; + bool big_endian; spin_lock_init(&port->lock); port->iotype = UPIO_MEM; @@ -230,6 +234,33 @@ int __init of_setup_earlycon(unsigned long addr, port->uartclk = BASE_BAUD * 16; port->membase = earlycon_map(addr, SZ_4K); + val = of_get_flat_dt_prop(node, "reg-offset", NULL); + if (val) + port->mapbase += be32_to_cpu(*val); + val = of_get_flat_dt_prop(node, "reg-shift", NULL); + if (val) + port->regshift = be32_to_cpu(*val); + big_endian = of_get_flat_dt_prop(node, "big-endian", NULL) != NULL || + (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) && + of_get_flat_dt_prop(node, "native-endian", NULL) != NULL); + val = of_get_flat_dt_prop(node, "reg-io-width", NULL); + if (val) { + switch (be32_to_cpu(*val)) { + case 1: + port->iotype = UPIO_MEM; + break; + case 2: + port->iotype = UPIO_MEM16; + break; + case 4: + port->iotype = (big_endian) ? UPIO_MEM32BE : UPIO_MEM32; + break; + default: + pr_warn("[%s] unsupported reg-io-width\n", match->name); + return -EINVAL; + } + } + if (options) { strlcpy(early_console_dev.options, options, sizeof(early_console_dev.options)); -- cgit v1.2.3