From 17e357dfdacb17ab03c54d9966e24b3426a187b5 Mon Sep 17 00:00:00 2001 From: Pradeep Goudagunta Date: Thu, 4 Aug 2011 11:34:12 +0530 Subject: serial: tegra: Add delay after TX DMA complete Add 30 micro seconds delay after TX DMA burst complete, to make sure DMA burst completed before writing to tx fifo. Bug 847599 Original-Change-Id: Ifcc1f3f208f8c2396ef410bedfa1158643b94015 Reviewed-on: http://git-master/r/44933 Tested-by: Pradeep Goudagunta Tested-by: Om Prakash Singh Reviewed-by: Laxman Dewangan Rebase-Id: R16d2c723f934b72ee770795d988c8ef9659c55e2 --- drivers/tty/serial/tegra_hsuart.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/tty') diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c index caec27fdaf16..ba855c51a57f 100644 --- a/drivers/tty/serial/tegra_hsuart.c +++ b/drivers/tty/serial/tegra_hsuart.c @@ -479,6 +479,7 @@ static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req) unsigned long flags; dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count); + udelay(30); spin_lock_irqsave(&t->uport.lock, flags); xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); -- cgit v1.2.3