From 678708d95daa7d29ad5f49944f1b5385e3f27401 Mon Sep 17 00:00:00 2001 From: Jihoon Bang Date: Tue, 19 Jun 2012 16:12:00 -0700 Subject: WAR: gr3d: limit 3d clock when camera is on As WAR, limit 3d clock frequency and emc clock frequency when camera is on and chip is AP37. 3d clock is set to 361MHz and 437MHz is requested for emc clock with this change. This change allows 3d to request 1.1V in Core instead of 1.3V in AP37. Bug 1001262 Bug 1019309 Change-Id: I9f46f93d8da0fcf5afe05839177bf0d6e43a5840 Signed-off-by: Jihoon Bang Reviewed-on: http://git-master/r/130945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- drivers/video/tegra/host/gr3d/scale3d.c | 38 +++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 7 deletions(-) (limited to 'drivers/video/tegra/host') diff --git a/drivers/video/tegra/host/gr3d/scale3d.c b/drivers/video/tegra/host/gr3d/scale3d.c index 9a6a8e73b513..fc30c2259ad4 100644 --- a/drivers/video/tegra/host/gr3d/scale3d.c +++ b/drivers/video/tegra/host/gr3d/scale3d.c @@ -3,7 +3,7 @@ * * Tegra Graphics Host 3D clock scaling * - * Copyright (c) 2010-2012, NVIDIA Corporation. + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -41,12 +41,22 @@ #include #include "scale3d.h" #include "dev.h" +#include static int scale3d_is_enabled(void); static void scale3d_enable(int enable); #define POW2(x) ((x) * (x)) +/* + * 3D clock scaling should be treated differently when camera is on in AP37. + * 3D in AP37 requires 1.3V and combining it with MPE reaches to EDP limit. + * 3D clock really needs to be set to lower frequency which requires 1.0V. + * The same thing applies to 3D EMC clock. + */ +#define CAMERA_3D_CLK 300000000 +#define CAMERA_3D_EMC_CLK 437000000 + /* * debugfs parameters to control 3d clock scaling test * @@ -169,12 +179,26 @@ void nvhost_scale3d_suspend(struct nvhost_device *dev) static void reset_3d_clocks(void) { if (clk_get_rate(scale3d.clk_3d) != scale3d.max_rate_3d) { - clk_set_rate(scale3d.clk_3d, scale3d.max_rate_3d); - if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) - clk_set_rate(scale3d.clk_3d2, scale3d.max_rate_3d); - if (scale3d.p_scale_emc) - clk_set_rate(scale3d.clk_3d_emc, - clk_round_rate(scale3d.clk_3d_emc, UINT_MAX)); + if (is_tegra_camera_on()) + clk_set_rate(scale3d.clk_3d, CAMERA_3D_CLK); + else + clk_set_rate(scale3d.clk_3d, scale3d.max_rate_3d); + if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) { + if (is_tegra_camera_on()) + clk_set_rate(scale3d.clk_3d2, CAMERA_3D_CLK); + else + clk_set_rate(scale3d.clk_3d2, + scale3d.max_rate_3d); + } + if (scale3d.p_scale_emc) { + if (is_tegra_camera_on()) + clk_set_rate(scale3d.clk_3d_emc, + CAMERA_3D_EMC_CLK); + else + clk_set_rate(scale3d.clk_3d_emc, + clk_round_rate(scale3d.clk_3d_emc, + UINT_MAX)); + } } } -- cgit v1.2.3