From 13ebeef6a1b9c4e5c9789f835cc4ec34873f0bb1 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 23 Dec 2025 18:09:09 +0800 Subject: ACPI: processor: idle: Optimize ACPI idle driver registration Currently, the ACPI idle driver is registered from within a CPU hotplug callback. Although this didn't cause any functional issues, this is questionable and confusing. And it is better to register the cpuidle driver when all of the CPUs have been brought up. So add a new function to initialize acpi_idle_driver based on the power management information of an available CPU and register cpuidle driver in acpi_processor_driver_init(). This commit has four changes under the commit 7a8c994cbb2d (ACPI: processor: idle: Optimize ACPI idle driver registration): 1) move acpi_processor_register_idle_driver() ahead of the driver_register(). 2) add acpi_processor_cstate_first_run_checks() before calling acpi_processor_get_power_info(). 3) squash the commit 9d68320b2bca (ACPI: processor: idle: Fix function defined but not used warning) into this change. 4) use for_each_possible_cpu(cpu) to scan all possible cpus. Signed-off-by: Huisong Li Tested-by: Borislav Petkov (AMD) [ rjw: New comment edits, changelog tweak ] Link: https://patch.msgid.link/20251223100914.2407069-2-lihuisong@huawei.com Signed-off-by: Rafael J. Wysocki --- include/acpi/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/processor.h b/include/acpi/processor.h index d0eccbd920e5..ff864c1cee3a 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -423,6 +423,8 @@ int acpi_processor_power_init(struct acpi_processor *pr); int acpi_processor_power_exit(struct acpi_processor *pr); int acpi_processor_power_state_has_changed(struct acpi_processor *pr); int acpi_processor_hotplug(struct acpi_processor *pr); +void acpi_processor_register_idle_driver(void); +void acpi_processor_unregister_idle_driver(void); #else static inline int acpi_processor_power_init(struct acpi_processor *pr) { -- cgit v1.2.3 From 8ada9e11b3fc5d9e21c3a45c6c136944f7b28a14 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 23 Dec 2025 18:09:10 +0800 Subject: ACPI: processor: Remove unused empty stubs of some functions Empty stubs are defined in processor.h for some functions provided by the ACPI processor idle driver, but those functions are only used in the main ACPI processor driver which requires the ACPI processor idle driver to be present (selecting CONFIG_ACPI_PROCESSOR causes CONFIG_ACPI_PROCESSOR_IDLE to be selected too automatically). This means that the empty stubs in question are not really necessary and if both CONFIG_ACPI_PROCESSOR and CONFIG_ACPI_PROCESSOR_IDLE are unset, the compiler complains that they are defined, but not used. Drop them to get rid of the compiler warning. Signed-off-by: Huisong Li Tested-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20251223100914.2407069-3-lihuisong@huawei.com Signed-off-by: Rafael J. Wysocki --- include/acpi/processor.h | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/processor.h b/include/acpi/processor.h index ff864c1cee3a..2976a6d0c54f 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -425,26 +425,6 @@ int acpi_processor_power_state_has_changed(struct acpi_processor *pr); int acpi_processor_hotplug(struct acpi_processor *pr); void acpi_processor_register_idle_driver(void); void acpi_processor_unregister_idle_driver(void); -#else -static inline int acpi_processor_power_init(struct acpi_processor *pr) -{ - return -ENODEV; -} - -static inline int acpi_processor_power_exit(struct acpi_processor *pr) -{ - return -ENODEV; -} - -static inline int acpi_processor_power_state_has_changed(struct acpi_processor *pr) -{ - return -ENODEV; -} - -static inline int acpi_processor_hotplug(struct acpi_processor *pr) -{ - return -ENODEV; -} #endif /* CONFIG_ACPI_PROCESSOR_IDLE */ /* in processor_thermal.c */ -- cgit v1.2.3 From 31612f3642b1ec813c9c5915b4704e669630db28 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Tue, 23 Dec 2025 18:09:12 +0800 Subject: ACPI: processor: idle: Redefine two functions as void Notice that acpi_processor_power_init() and acpi_processor_power_exit() don't need to return any values because their callers don't check them anyway, so redefine those functions as void. While at it, rearrange the code in acpi_processor_power_init() to reduce the indentation level, get rid of a redundant local variable in that function, and rephrase a code comment in it. No intentional functional impact. Signed-off-by: Rafael J. Wysocki Reviewed-by: Mario Limonciello (AMD) Tested-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20251223100914.2407069-5-lihuisong@huawei.com Signed-off-by: Rafael J. Wysocki --- include/acpi/processor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 2976a6d0c54f..0200aef6e754 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -419,8 +419,8 @@ static inline void acpi_processor_throttling_init(void) {} /* in processor_idle.c */ extern struct cpuidle_driver acpi_idle_driver; #ifdef CONFIG_ACPI_PROCESSOR_IDLE -int acpi_processor_power_init(struct acpi_processor *pr); -int acpi_processor_power_exit(struct acpi_processor *pr); +void acpi_processor_power_init(struct acpi_processor *pr); +void acpi_processor_power_exit(struct acpi_processor *pr); int acpi_processor_power_state_has_changed(struct acpi_processor *pr); int acpi_processor_hotplug(struct acpi_processor *pr); void acpi_processor_register_idle_driver(void); -- cgit v1.2.3 From d8e43c89cf08ffea4825a24fb8dfd8bde4de9bb1 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 23 Dec 2025 18:09:13 +0800 Subject: ACPI: processor: idle: Rearrange declarations in header file Group all of the declarations of functions that belong to the ACPI processor idle driver together in one place in processor.h. While at it, drop the unnecessary extern modifier from the declaraions of two functions. Signed-off-by: Huisong Li Tested-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20251223100914.2407069-6-lihuisong@huawei.com Signed-off-by: Rafael J. Wysocki --- include/acpi/processor.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 0200aef6e754..24fdaa3c2899 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -425,6 +425,8 @@ int acpi_processor_power_state_has_changed(struct acpi_processor *pr); int acpi_processor_hotplug(struct acpi_processor *pr); void acpi_processor_register_idle_driver(void); void acpi_processor_unregister_idle_driver(void); +int acpi_processor_ffh_lpi_probe(unsigned int cpu); +int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi); #endif /* CONFIG_ACPI_PROCESSOR_IDLE */ /* in processor_thermal.c */ @@ -447,11 +449,6 @@ static inline void acpi_thermal_cpufreq_exit(struct cpufreq_policy *policy) } #endif /* CONFIG_CPU_FREQ */ -#ifdef CONFIG_ACPI_PROCESSOR_IDLE -extern int acpi_processor_ffh_lpi_probe(unsigned int cpu); -extern int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi); -#endif - void acpi_processor_init_invariance_cppc(void); #endif -- cgit v1.2.3 From 24b09e849139f92bce0bb966f21409c95c60564a Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 23 Dec 2025 18:09:14 +0800 Subject: ACPI: processor: Do not expose global variable acpi_idle_driver Move the cpuidle driver check from __acpi_processor_start() to acpi_processor_power_init() which allows variable acpi_idle_driver to become static. No intentional functional impact. Signed-off-by: Huisong Li Tested-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20251223100914.2407069-7-lihuisong@huawei.com Signed-off-by: Rafael J. Wysocki --- include/acpi/processor.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/acpi') diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 24fdaa3c2899..7146a8e9e9c2 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -417,7 +417,6 @@ static inline void acpi_processor_throttling_init(void) {} #endif /* CONFIG_ACPI_CPU_FREQ_PSS */ /* in processor_idle.c */ -extern struct cpuidle_driver acpi_idle_driver; #ifdef CONFIG_ACPI_PROCESSOR_IDLE void acpi_processor_power_init(struct acpi_processor *pr); void acpi_processor_power_exit(struct acpi_processor *pr); -- cgit v1.2.3 From fa2408a24f8f0db14d9cfc613ef162dc267d7ad4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 8 Jan 2026 12:35:05 +0100 Subject: APEI/GHES: ensure that won't go past CPER allocated record The logic at ghes_new() prevents allocating too large records, by checking if they're bigger than GHES_ESTATUS_MAX_SIZE (currently, 64KB). Yet, the allocation is done with the actual number of pages from the CPER bios table location, which can be smaller. Yet, a bad firmware could send data with a different size, which might be bigger than the allocated memory, causing an OOPS: Unable to handle kernel paging request at virtual address fff00000f9b40000 Mem abort info: ESR = 0x0000000096000007 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x07: level 3 translation fault Data abort info: ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000 CM = 0, WnR = 0, TnD = 0, TagAccess = 0 GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 swapper pgtable: 4k pages, 52-bit VAs, pgdp=000000008ba16000 [fff00000f9b40000] pgd=180000013ffff403, p4d=180000013fffe403, pud=180000013f85b403, pmd=180000013f68d403, pte=0000000000000000 Internal error: Oops: 0000000096000007 [#1] SMP Modules linked in: CPU: 0 UID: 0 PID: 303 Comm: kworker/0:1 Not tainted 6.19.0-rc1-00002-gda407d200220 #34 PREEMPT Hardware name: QEMU QEMU Virtual Machine, BIOS unknown 02/02/2022 Workqueue: kacpi_notify acpi_os_execute_deferred pstate: 214020c5 (nzCv daIF +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : hex_dump_to_buffer+0x30c/0x4a0 lr : hex_dump_to_buffer+0x328/0x4a0 sp : ffff800080e13880 x29: ffff800080e13880 x28: ffffac9aba86f6a8 x27: 0000000000000083 x26: fff00000f9b3fffc x25: 0000000000000004 x24: 0000000000000004 x23: ffff800080e13905 x22: 0000000000000010 x21: 0000000000000083 x20: 0000000000000001 x19: 0000000000000008 x18: 0000000000000010 x17: 0000000000000001 x16: 00000007c7f20fec x15: 0000000000000020 x14: 0000000000000008 x13: 0000000000081020 x12: 0000000000000008 x11: ffff800080e13905 x10: ffff800080e13988 x9 : 0000000000000000 x8 : 0000000000000000 x7 : 0000000000000001 x6 : 0000000000000020 x5 : 0000000000000030 x4 : 00000000fffffffe x3 : 0000000000000000 x2 : ffffac9aba78c1c8 x1 : ffffac9aba76d0a8 x0 : 0000000000000008 Call trace: hex_dump_to_buffer+0x30c/0x4a0 (P) print_hex_dump+0xac/0x170 cper_estatus_print_section+0x90c/0x968 cper_estatus_print+0xf0/0x158 __ghes_print_estatus+0xa0/0x148 ghes_proc+0x1bc/0x220 ghes_notify_hed+0x5c/0xb8 notifier_call_chain+0x78/0x148 blocking_notifier_call_chain+0x4c/0x80 acpi_hed_notify+0x28/0x40 acpi_ev_notify_dispatch+0x50/0x80 acpi_os_execute_deferred+0x24/0x48 process_one_work+0x15c/0x3b0 worker_thread+0x2d0/0x400 kthread+0x148/0x228 ret_from_fork+0x10/0x20 Code: 6b14033f 540001ad a94707e2 f100029f (b8747b44) ---[ end trace 0000000000000000 ]--- Prevent that by taking the actual allocated are into account when checking for CPER length. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Acked-by: Ard Biesheuvel Reviewed-by: Hanjun Guo [ rjw: Subject tweaks ] Link: https://patch.msgid.link/4e70310a816577fabf37d94ed36cde4ad62b1e0a.1767871950.git.mchehab+huawei@kernel.org Signed-off-by: Rafael J. Wysocki --- include/acpi/ghes.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/acpi') diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index ebd21b05fe6e..93db60da5934 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -21,6 +21,7 @@ struct ghes { struct acpi_hest_generic_v2 *generic_v2; }; struct acpi_hest_generic_status *estatus; + unsigned int estatus_length; unsigned long flags; union { struct list_head list; -- cgit v1.2.3 From f2edc1fb9c81b7b57a092204455e4d159a10873e Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Mon, 12 Jan 2026 11:22:37 +0800 Subject: ACPI: APEI: GHES: Improve ghes_notify_nmi() status check ghes_notify_nmi() is called for every NMI and must check whether the NMI was generated because an error was signalled by platform firmware. This check is very expensive as for each registered GHES NMI source it reads from the acpi generic address attached to this error source to get the physical address of the acpi_hest_generic_status block. It then checks the "block_status" to see if an error was logged. The ACPI/APEI code must create virtual mappings for each of those physical addresses, and tear them down afterwards. On an Icelake system this takes around 15,000 TSC cycles. Enough to disturb efforts to profile system performance. If that were not bad enough, there are some atomic accesses in the code path that will cause cache line bounces between CPUs. A problem that gets worse as the core count increases. But BIOS changes neither the acpi generic address nor the physical address of the acpi_hest_generic_status block. So this walk can be done once when the NMI is registered to save the virtual address (unmapping if the NMI is ever unregistered). The "block_status" can be checked directly in the NMI handler. This can be done without any atomic accesses. Resulting time to check that there is not an error record is around 900 cycles. Reported-by: Andi Kleen Signed-off-by: Tony Luck Tested-by: Tony Luck Signed-off-by: Shuai Xue Reviewed-by: Hanjun Guo Link: https://patch.msgid.link/20260112032239.30023-2-xueshuai@linux.alibaba.com Signed-off-by: Rafael J. Wysocki --- include/acpi/ghes.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/acpi') diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index 93db60da5934..7bea522c0657 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -30,6 +30,7 @@ struct ghes { }; struct device *dev; struct list_head elist; + void __iomem *error_status_vaddr; }; struct ghes_estatus_node { -- cgit v1.2.3 From d6f6bae3ecba665e18a6b6cfcd575f8e9f46b204 Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:16:23 +0100 Subject: ACPICA: Add support for the new ACPI Table: DTPR Define a new the ACPI Table, structure and registers, related with it, according to the latest version of the Intel TXT DMA Protection Ranges (TPR) specification (Revision 0.73): * DTPR ACPI Table * TPR Base Register * TPR Serialize Request Register * TPR Limit Register * TPR Instance Structure * DMAR TXT Protected Reporting Structure These structures will be used to handle TPRs on the Intel CPU's. Link: https://github.com/acpica/acpica/commit/10e7a88f70da Link: https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Protection_Ranges_rev_0p73.pdf Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/6234415.lOV4Wx5bFT@rafael.j.wysocki --- include/acpi/actbl1.h | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 7f35eb0e8458..23449a068c5c 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -47,6 +47,7 @@ #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ #define ACPI_SIG_IBFT "IBFT" /* iSCSI Boot Firmware Table */ #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ +#define ACPI_SIG_DTPR "DTPR" /* TXT DMA Protection Ranges reporting table */ #define ACPI_SIG_S3PT "S3PT" /* S3 Performance (sub)Table */ #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */ @@ -1973,6 +1974,91 @@ struct acpi_ibft_target { u16 reverse_chap_secret_offset; }; +/******************************************************************************* + * + * DTPR - DMA TPR Reporting + * Version 1 + * + * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection + * Ranges", + * Revision 0.73, August 2021 + * + ******************************************************************************/ + +struct acpi_table_dtpr { + struct acpi_table_header header; + u32 flags; // 36 +}; + +struct acpi_tpr_array { + u64 base; +}; + +struct acpi_dtpr_instance { + u32 flags; + u32 tpr_cnt; + struct acpi_tpr_array tpr_array[]; +}; + +/******************************************************************************* + * TPRn_BASE + * + * Specifies the start address of TPRn region. TPR region address and size must + * be with 1MB resolution. These bits are compared with the result of the + * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an + * access fall within the TPRn defined region. +*******************************************************************************/ +struct acpi_dtprn_base_reg { + u64 reserved0:3; + u64 rw:1; // access: 1 == RO, 0 == RW (for TPR must be RW) + u64 enable:1; // 0 == range enabled, 1 == range disabled + u64 reserved1:15; + u64 tpr_base_rw:44; // minimal TPrn_base resolution is 1MB. + // applied to the incoming address, to determine if an + // access fall within the TPrn defined region. + // width is determined by a bus width which can be + // obtainedvia CPUID function 0x80000008. + //u64 unused : 1; +}; + +/******************************************************************************* + * TPRn_LIMIT + * + * This register defines an isolated region of memory that can be enabled + * to prohibit certain system agents from accessing memory. When an agent + * sends a request upstream, whether snooped or not, a TPR prevents that + * transaction from changing the state of memory. +*******************************************************************************/ + +struct acpi_dtprn_limit_reg { + u64 reserved0:3; + u64 rw:1; // access: 1 == RO, 0 == RW (for TPR must be RW) + u64 enable:1; // 0 == range enabled, 1 == range disabled + u64 reserved1:15; + u64 tpr_limit_rw:44; // minimal TPrn_limit resolution is 1MB. + // these bits define TPR limit address. + // width is determined by a bus width. + + //u64 unused : 1; +}; + +/******************************************************************************* + * SERIALIZE_REQUEST + * + * This register is used to request serialization of non-coherent DMA + * transactions. OS shall issue it before changing of TPR settings + * (base / size). +*******************************************************************************/ + +struct acpi_tpr_serialize_request { + u64 sts:1; // status of serialization request (RO) + // 0 == register idle, 1 == serialization in progress + u64 ctrl:1; // control field to initiate serialization (RW) + // 0 == normal, 1 == initialize serialization + // (self-clear to allow multiple serialization requests) + u64 unused:62; +}; + /* Reset to default packing */ #pragma pack() -- cgit v1.2.3 From 19df9f21ca1a2f728deb880a526db0742059ca9f Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Wed, 14 Jan 2026 13:18:33 +0100 Subject: ACPICA: Add UUID for Microsoft fan extensions Microsoft has designed an interface for reading/writing fan speed trip points. Add the associated UUID to the list of known UUIDs so that the ASL compiler stops complaining about it. Link: https://github.com/acpica/acpica/commit/67f0202c0fb4 Signed-off-by: Armin Wolf Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/5045837.GXAFRqVoOG@rafael.j.wysocki --- include/acpi/acuuid.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/acpi') diff --git a/include/acpi/acuuid.h b/include/acpi/acuuid.h index 25dd3e998727..0eda9d997f31 100644 --- a/include/acpi/acuuid.h +++ b/include/acpi/acuuid.h @@ -71,4 +71,5 @@ #define UUID_USB4_CAPABILITIES "23a0d13a-26ab-486c-9c5f-0ffa525a575a" #define UUID_1ST_FUNCTION_ID "893f00a6-660c-494e-bcfd-3043f4fb67c0" #define UUID_2ND_FUNCTION_ID "107ededd-d381-4fd7-8da9-08e9a6c79644" +#define UUID_FAN_TRIP_POINTS "a7611840-99fe-41ae-a488-35c75926c8eb" #endif /* __ACUUID_H__ */ -- cgit v1.2.3 From ce04af0a1bf96a6adbbe57b2d1548491cd59772b Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Wed, 14 Jan 2026 13:19:22 +0100 Subject: ACPICA: Add UUIDs associated with TPM 2.0 devices The Trusted Computing Group has designed multiple interface extensions around TPM 2.0 devices including the ACPI start method, hardware information and memory clear features. Add the associated UUIDs to the list of known UUIDs so that the ASL compiler stops complaining about them. Link: https://github.com/acpica/acpica/commit/0e8b10b05825 Signed-off-by: Armin Wolf Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2254685.irdbgypaU6@rafael.j.wysocki --- include/acpi/acuuid.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/acuuid.h b/include/acpi/acuuid.h index 0eda9d997f31..b2e29da6ba0a 100644 --- a/include/acpi/acuuid.h +++ b/include/acpi/acuuid.h @@ -37,6 +37,11 @@ #define UUID_DEVICE_LABELING "e5c937d0-3553-4d7a-9117-ea4d19c3434d" #define UUID_PHYSICAL_PRESENCE "3dddfaa6-361b-4eb4-a424-8d10089d1653" +/* TPM */ +#define UUID_HARDWARE_INFORMATION "cf8e16a5-c1e8-4e25-b712-4f54a96702c8" +#define UUID_START_METHOD "6bbf6cab-5463-4714-b7cd-f0203c0368d4" +#define UUID_MEMORY_CLEAR "376054ed-cc13-4675-901c-4756d7f2d45d" + /* NVDIMM - NFIT table */ #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66" -- cgit v1.2.3 From 55e81991e1e4f8e220e83677919a65e919a407bc Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Wed, 14 Jan 2026 13:21:05 +0100 Subject: ACPICA: Add KEYP table definition Software uses this table to discover the base address of the Key Configuration Unit (KCU) register block associated with each IDE capable host bridge. [1]: Root Complex IDE Key Configuration Unit Software Programming Guide https://cdrdv2.intel.com/v1/dl/getContent/732838 Link: https://github.com/acpica/acpica/commit/af970172e2dd Signed-off-by: Dave Jiang Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/3401908.44csPzL39Z@rafael.j.wysocki --- include/acpi/actbl2.h | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index f726bce3eb84..4040e4df051b 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -32,6 +32,7 @@ #define ACPI_SIG_ERDT "ERDT" /* Enhanced Resource Director Technology */ #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */ #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ +#define ACPI_SIG_KEYP "KEYP" /* Key Programming Interface for IDE */ #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ @@ -1065,6 +1066,64 @@ struct acpi_ivrs_memory { u64 memory_length; }; +/******************************************************************************* + * + * KEYP - Key Programming Interface for Root Complex Integrity and Data + * Encryption (IDE) + * Version 1 + * + * Conforms to "Key Programming Interface for Root Complex Integrity and Data + * Encryption (IDE)" document. See under ACPI-Related Documents. + * + ******************************************************************************/ +struct acpi_table_keyp { + struct acpi_table_header header; /* Common ACPI table header */ + u32 reserved; +}; + +/* KEYP common subtable header */ + +struct acpi_keyp_common_header { + u8 type; + u8 reserved; + u16 length; +}; + +/* Values for Type field above */ + +enum acpi_keyp_type { + ACPI_KEYP_TYPE_CONFIG_UNIT = 0, +}; + +/* Root Port Information Structure */ + +struct acpi_keyp_rp_info { + u16 segment; + u8 bus; + u8 devfn; +}; + +/* Key Configuration Unit Structure */ + +struct acpi_keyp_config_unit { + struct acpi_keyp_common_header header; + u8 protocol_type; + u8 version; + u8 root_port_count; + u8 flags; + u64 register_base_address; + struct acpi_keyp_rp_info rp_info[]; +}; + +enum acpi_keyp_protocol_type { + ACPI_KEYP_PROTO_TYPE_INVALID = 0, + ACPI_KEYP_PROTO_TYPE_PCIE, + ACPI_KEYP_PROTO_TYPE_CXL, + ACPI_KEYP_PROTO_TYPE_RESERVED +}; + +#define ACPI_KEYP_F_TVM_USABLE (1) + /******************************************************************************* * * LPIT - Low Power Idle Table -- cgit v1.2.3 From 75c3b2d97c2a7e2197437e673c5140731dd0004a Mon Sep 17 00:00:00 2001 From: Xianglai Li Date: Wed, 14 Jan 2026 13:22:50 +0100 Subject: ACPICA: iASL: Add definitions for the IOVT table Add definitions for the IOVT table and its subtables. Link: https://github.com/acpica/acpica/commit/14c0def532ac Signed-off-by: Xianglai Li Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2031013.PYKUYFuaPT@rafael.j.wysocki --- include/acpi/actbl2.h | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 4040e4df051b..617be4bd3d4a 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -31,6 +31,7 @@ #define ACPI_SIG_CDAT "CDAT" /* Coherent Device Attribute Table */ #define ACPI_SIG_ERDT "ERDT" /* Enhanced Resource Director Technology */ #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */ +#define ACPI_SIG_IOVT "IOVT" /* I/O Virtualization Table */ #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ #define ACPI_SIG_KEYP "KEYP" /* Key Programming Interface for IDE */ #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ @@ -859,6 +860,73 @@ struct acpi_iort_rmr_desc { u32 reserved; }; +/******************************************************************************* + * + * IOVT - I/O Virtualization Table + * + * Conforms to "LoongArch I/O Virtualization Table", + * Version 0.1, October 2024 + * + ******************************************************************************/ + +struct acpi_table_iovt { + struct acpi_table_header header; /* Common ACPI table header */ + u16 iommu_count; + u16 iommu_offset; + u8 reserved[8]; +}; + +/* IOVT subtable header */ + +struct acpi_iovt_header { + u16 type; + u16 length; +}; + +/* Values for Type field above */ + +enum acpi_iovt_iommu_type { + ACPI_IOVT_IOMMU_V1 = 0x00, + ACPI_IOVT_IOMMU_RESERVED = 0x01 /* 1 and greater are reserved */ +}; + +/* IOVT subtables */ + +struct acpi_iovt_iommu { + struct acpi_iovt_header header; + u32 flags; + u16 segment; + u16 phy_width; /* Physical Address Width */ + u16 virt_width; /* Virtual Address Width */ + u16 max_page_level; + u64 page_size; + u32 device_id; + u64 base_address; + u32 address_space_size; + u8 interrupt_type; + u8 reserved[3]; + u32 gsi_number; + u32 proximity_domain; + u32 max_device_num; + u32 device_entry_num; + u32 device_entry_offset; +}; + +struct acpi_iovt_device_entry { + u8 type; + u8 length; + u8 flags; + u8 reserved[3]; + u16 device_id; +}; + +enum acpi_iovt_device_entry_type { + ACPI_IOVT_DEVICE_ENTRY_SINGLE = 0x00, + ACPI_IOVT_DEVICE_ENTRY_START = 0x01, + ACPI_IOVT_DEVICE_ENTRY_END = 0x02, + ACPI_IOVT_DEVICE_ENTRY_RESERVED = 0x03 /* 3 and greater are reserved */ +}; + /******************************************************************************* * * IVRS - I/O Virtualization Reporting Structure -- cgit v1.2.3 From c5ecbc65bb2287b66b3b8adbdbe0fddb81bc297f Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:23:40 +0100 Subject: ACPICA: Add DTPR table support for the ASL compiler Define DTPR related structures offsets. Link: https://github.com/acpica/acpica/commit/c6fc16c8936d Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/7902293.EvYhyI6sBW@rafael.j.wysocki --- include/acpi/actbl1.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 23449a068c5c..423e7232974a 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -37,6 +37,7 @@ #define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ #define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ #define ACPI_SIG_DRTM "DRTM" /* Dynamic Root of Trust for Measurement table */ +#define ACPI_SIG_DTPR "DTPR" /* DMA TXT Protection Ranges table */ #define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */ #define ACPI_SIG_EINJ "EINJ" /* Error Injection table */ #define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */ @@ -47,7 +48,6 @@ #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ #define ACPI_SIG_IBFT "IBFT" /* iSCSI Boot Firmware Table */ #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ -#define ACPI_SIG_DTPR "DTPR" /* TXT DMA Protection Ranges reporting table */ #define ACPI_SIG_S3PT "S3PT" /* S3 Performance (sub)Table */ #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */ @@ -1994,7 +1994,7 @@ struct acpi_tpr_array { u64 base; }; -struct acpi_dtpr_instance { +struct acpi_tpr_instance { u32 flags; u32 tpr_cnt; struct acpi_tpr_array tpr_array[]; @@ -2008,7 +2008,7 @@ struct acpi_dtpr_instance { * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an * access fall within the TPRn defined region. *******************************************************************************/ -struct acpi_dtprn_base_reg { +struct acpi_tprn_base_reg { u64 reserved0:3; u64 rw:1; // access: 1 == RO, 0 == RW (for TPR must be RW) u64 enable:1; // 0 == range enabled, 1 == range disabled @@ -2030,7 +2030,7 @@ struct acpi_dtprn_base_reg { * transaction from changing the state of memory. *******************************************************************************/ -struct acpi_dtprn_limit_reg { +struct acpi_tprn_limit_reg { u64 reserved0:3; u64 rw:1; // access: 1 == RO, 0 == RW (for TPR must be RW) u64 enable:1; // 0 == range enabled, 1 == range disabled -- cgit v1.2.3 From 30c2a333aa90c4265bed7629980eb0df72f56dfb Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:24:38 +0100 Subject: ACPICA: Define DTPR structure related info tables and data template * DTPR Table Info * TPR Instance Table Info * TPR Array Table Info * TPR Serialize Request Table Info * DTPR Table Data Template Link: https://github.com/acpica/acpica/commit/abadf1d34732 Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/3676546.iIbC2pHGDl@rafael.j.wysocki --- include/acpi/actbl1.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 423e7232974a..f16020829f42 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1976,7 +1976,7 @@ struct acpi_ibft_target { /******************************************************************************* * - * DTPR - DMA TPR Reporting + * DTPR - DMA TXT Protection Ranges Table * Version 1 * * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection @@ -1988,6 +1988,7 @@ struct acpi_ibft_target { struct acpi_table_dtpr { struct acpi_table_header header; u32 flags; // 36 + u32 ins_cnt; }; struct acpi_tpr_array { -- cgit v1.2.3 From 091c4af3562d0b8484c7098fd16cf3cf9f39e7c9 Mon Sep 17 00:00:00 2001 From: Ben Horgan Date: Wed, 14 Jan 2026 13:26:26 +0100 Subject: ACPICA: ACPI 6.4: PPTT: include all fields in subtable type1 In PPTT version 3 an extra field, Cache ID, was added to the Cache Type Structure. The struct, struct acpi_pptt_cache_v1, contains only this field. This differs from the treatment of other versioned structures and is unexpected for linux which reuses the actbl2.h header file. Include all the fields of the new Cache Type Structure in struct acpi_pptt_cache_v1 and fix up all uses. Link: https://github.com/acpica/acpica/commit/a9ec9105f552 Signed-off-by: Ben Horgan Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/1851677.VLH7GnMWUR@rafael.j.wysocki --- include/acpi/actbl2.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 617be4bd3d4a..15856ae8b1e1 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -2953,6 +2953,15 @@ struct acpi_pptt_cache { /* 1: Cache Type Structure for PPTT version 3 */ struct acpi_pptt_cache_v1 { + struct acpi_subtable_header header; + u16 reserved; + u32 flags; + u32 next_level_of_cache; + u32 size; + u32 number_of_sets; + u8 associativity; + u8 attributes; + u16 line_size; u32 cache_id; }; -- cgit v1.2.3 From 0cc5b091ecf8d3695551b654863c3a05cdd69089 Mon Sep 17 00:00:00 2001 From: Jose Marinho Date: Wed, 14 Jan 2026 13:29:05 +0100 Subject: ACPICA: Add GICv5 MADT structures The GICv5 adds the following MADT structures: - IRS - ITS Config Frame - ITS Translate Frame The ACPI spec ECR is at https://github.com/tianocore/edk2/issues/11148 Link: https://github.com/acpica/acpica/commit/69cca52ddf04 Signed-off-by: Jose Marinho Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/1953107.CQOukoFCf9@rafael.j.wysocki --- include/acpi/actbl2.h | 49 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 4 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 15856ae8b1e1..05ce897f1eeb 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1294,7 +1294,10 @@ enum acpi_madt_type { ACPI_MADT_TYPE_IMSIC = 25, ACPI_MADT_TYPE_APLIC = 26, ACPI_MADT_TYPE_PLIC = 27, - ACPI_MADT_TYPE_RESERVED = 28, /* 28 to 0x7F are reserved */ + ACPI_MADT_TYPE_GICV5_IRS = 28, + ACPI_MADT_TYPE_GICV5_ITS = 29, + ACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30, + ACPI_MADT_TYPE_RESERVED = 31, /* 31 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -1416,7 +1419,7 @@ struct acpi_madt_local_x2apic_nmi { u8 reserved[3]; /* reserved - must be zero */ }; -/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 changes) */ +/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 + ACPI 6.7 changes) */ struct acpi_madt_generic_interrupt { struct acpi_subtable_header header; @@ -1437,6 +1440,8 @@ struct acpi_madt_generic_interrupt { u8 reserved2[1]; u16 spe_interrupt; /* ACPI 6.3 */ u16 trbe_interrupt; /* ACPI 6.5 */ + u16 iaffid; /* ACPI 6.7 */ + u32 irs_id; }; /* Masks for Flags field above */ @@ -1459,7 +1464,7 @@ struct acpi_madt_generic_distributor { u8 reserved2[3]; /* reserved - must be zero */ }; -/* Values for Version field above */ +/* Values for Version field above and Version field in acpi_madt_gicv5_irs */ enum acpi_madt_gic_version { ACPI_MADT_GIC_VERSION_NONE = 0, @@ -1467,7 +1472,8 @@ enum acpi_madt_gic_version { ACPI_MADT_GIC_VERSION_V2 = 2, ACPI_MADT_GIC_VERSION_V3 = 3, ACPI_MADT_GIC_VERSION_V4 = 4, - ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */ + ACPI_MADT_GIC_VERSION_V5 = 5, + ACPI_MADT_GIC_VERSION_RESERVED = 6 /* 6 and greater are reserved */ }; /* 13: Generic MSI Frame (ACPI 5.1) */ @@ -1738,6 +1744,41 @@ struct acpi_madt_plic { u32 gsi_base; }; +/* 28: Arm GICv5 IRS (ACPI 6.7) */ +struct acpi_madt_gicv5_irs { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 irs_id; + u32 flags; + u32 reserved2; + u64 config_base_address; + u64 setlpi_base_address; +}; + +#define ACPI_MADT_IRS_NON_COHERENT (1) + +/* 29: Arm GICv5 ITS Config Frame (ACPI 6.7) */ +struct acpi_madt_gicv5_translator { + struct acpi_subtable_header header; + u8 flags; + u8 reserved; /* reserved - must be zero */ + u32 translator_id; + u64 base_address; +}; + +#define ACPI_MADT_GICV5_ITS_NON_COHERENT (1) + +/* 30: Arm GICv5 ITS Translate Frame (ACPI 6.7) */ +struct acpi_madt_gicv5_translate_frame { + struct acpi_subtable_header header; + u16 reserved; /* reserved - must be zero */ + u32 linked_translator_id; + u32 translate_frame_id; + u32 reserved2; + u64 base_address; +}; + /* 80: OEM data */ struct acpi_madt_oem_data { -- cgit v1.2.3 From 522ceeceff12426b5d9e0f577921c873b9d6af6a Mon Sep 17 00:00:00 2001 From: Jose Marinho Date: Wed, 14 Jan 2026 13:29:59 +0100 Subject: ACPICA: Add Arm IORT IWB node definitions The IORT IUWB node is defined in IORT issue E.g See https://developer.arm.com/documentation/den0049/eg Link: https://github.com/acpica/acpica/commit/a90dc2f5380c Signed-off-by: Jose Marinho Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2691130.Lt9SDvczpP@rafael.j.wysocki --- include/acpi/actbl2.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 05ce897f1eeb..01dc35e4b60a 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -682,6 +682,7 @@ enum acpi_iort_node_type { ACPI_IORT_NODE_SMMU_V3 = 0x04, ACPI_IORT_NODE_PMCG = 0x05, ACPI_IORT_NODE_RMR = 0x06, + ACPI_IORT_NODE_IWB = 0x07, }; struct acpi_iort_id_mapping { @@ -860,6 +861,12 @@ struct acpi_iort_rmr_desc { u32 reserved; }; +struct acpi_iort_iwb { + u64 base_address; + u16 iwb_index; /* Unique IWB identifier matching with the IWB GSI namespace. */ + char device_name[]; /* Path of the IWB namespace object */ +}; + /******************************************************************************* * * IOVT - I/O Virtualization Table -- cgit v1.2.3 From 8059c6230617b7f69c36958d59e1025a62f7185b Mon Sep 17 00:00:00 2001 From: Pawel Chmielewski Date: Wed, 14 Jan 2026 13:31:06 +0100 Subject: ACPICA: actbl2.h: ACPI 6.6: RAS2: Update Parameter Block structure ACPI 6.6 introduces RAS2 enhancements for patrol scrub functionality, adding new fields to the Parameter Block structure. These fields are applicable only in the response to the GET_PATROL_PARAMETERS command. Link: https://github.com/acpica/acpica/commit/062842024000 Signed-off-by: Pawel Chmielewski Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2263284.Mh6RI2rZIc@rafael.j.wysocki --- include/acpi/actbl2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 01dc35e4b60a..5c0b55e7b3e4 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -3249,6 +3249,8 @@ struct acpi_ras2_patrol_scrub_param { u32 flags; u32 scrub_params_out; u32 scrub_params_in; + u32 ext_scrub_params; + u8 scrub_rate_desc[256]; }; /* Masks for Flags field above */ -- cgit v1.2.3 From 146b5e78b3ea6ae1594f5029109c2ddaf251b1cb Mon Sep 17 00:00:00 2001 From: Pawel Chmielewski Date: Wed, 14 Jan 2026 13:31:59 +0100 Subject: ACPICA: actbl3.h: ACPI 6.6: SRAT: New flag in Memory Affinity Structure ACPI 6.6 introduces Specific-Purpose flag to Memory Affinity structure. Link: https://github.com/acpica/acpica/commit/cfce3b689b5e Signed-off-by: Pawel Chmielewski Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/3868802.MHq7AAxBmi@rafael.j.wysocki --- include/acpi/actbl3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl3.h b/include/acpi/actbl3.h index 79d3aa5a4bad..7ca456e88377 100644 --- a/include/acpi/actbl3.h +++ b/include/acpi/actbl3.h @@ -238,6 +238,7 @@ struct acpi_srat_mem_affinity { #define ACPI_SRAT_MEM_ENABLED (1) /* 00: Use affinity structure */ #define ACPI_SRAT_MEM_HOT_PLUGGABLE (1<<1) /* 01: Memory region is hot pluggable */ #define ACPI_SRAT_MEM_NON_VOLATILE (1<<2) /* 02: Memory region is non-volatile */ +#define ACPI_SRAT_MEM_SPEC_PURPOSE (1<<3) /* 03: Memory is intended for specific-purpose usage */ /* 2: Processor Local X2_APIC Affinity (ACPI 4.0) */ -- cgit v1.2.3 From 6f99d3fe224feefabc012869e10cbff52eb5f5f8 Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:33:49 +0100 Subject: ACPICA: Create auxiliary ACPI_TPR_AUX_SR structure for iASL compiler Define unofficial structure ACPI_TPR_AUX_SR, which holds information about the number of serialization registers for TPRs. It simplifies DTPR Serialization Request Info Table compilation. Link: https://github.com/acpica/acpica/commit/31f470e708a9 Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2266165.Icojqenx9y@rafael.j.wysocki --- include/acpi/actbl1.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index f16020829f42..89541cd0c9b0 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -2001,6 +2001,11 @@ struct acpi_tpr_instance { struct acpi_tpr_array tpr_array[]; }; +struct acpi_tpr_aux_sr { + u32 srl_cnt; + //ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; +}; + /******************************************************************************* * TPRn_BASE * -- cgit v1.2.3 From b110e28c3bf52c984c232ee633139ea10f754c0c Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:34:43 +0100 Subject: ACPICA: Fix Segmentation Fault error related to DTPR Fix Segmentation Fault error, caused by invalid buffer lenght in DTPR Table Template: * Update buffer length for TPR Table, which invalid value caused Segmentation Fault, during ASL file production. * Refactor invalid values of TPR instances, arrays and serialization requests count and TPR Base addresses in the DTPR table template. * Fix offset updating in the acpi_dm_dump_dtpr function. Link: https://github.com/acpica/acpica/commit/f75850bc4717 Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2541195.jE0xQCEvom@rafael.j.wysocki --- include/acpi/actbl1.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 89541cd0c9b0..59fbd64405be 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -2057,12 +2057,12 @@ struct acpi_tprn_limit_reg { *******************************************************************************/ struct acpi_tpr_serialize_request { - u64 sts:1; // status of serialization request (RO) - // 0 == register idle, 1 == serialization in progress - u64 ctrl:1; // control field to initiate serialization (RW) - // 0 == normal, 1 == initialize serialization + u64 sr_register; + // BIT 1 - status of serialization request (RO) + // 0 == register idle, 1 == serialization in progress + // BIT 2 - control field to initiate serialization (RW) + // 0 == normal, 1 == initialize serialization // (self-clear to allow multiple serialization requests) - u64 unused:62; }; /* Reset to default packing */ -- cgit v1.2.3 From 9565d4713ba6d3711d7b47fee9dde6725721ac06 Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:35:31 +0100 Subject: ACPICA: Verify DTPR and TPR Instance buffer pointers Verify DTPR and TPR Instance buffer pointers and refactor comments. Link: https://github.com/acpica/acpica/commit/bdec5b61cf5b Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/884204745.0ifERbkFSE@rafael.j.wysocki --- include/acpi/actbl1.h | 59 ++++++++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 27 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 59fbd64405be..a580b993cc48 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1987,7 +1987,7 @@ struct acpi_ibft_target { struct acpi_table_dtpr { struct acpi_table_header header; - u32 flags; // 36 + u32 flags; /* 36 */ u32 ins_cnt; }; @@ -2003,66 +2003,71 @@ struct acpi_tpr_instance { struct acpi_tpr_aux_sr { u32 srl_cnt; - //ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; + /* ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; */ }; -/******************************************************************************* +/* * TPRn_BASE * * Specifies the start address of TPRn region. TPR region address and size must * be with 1MB resolution. These bits are compared with the result of the * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an * access fall within the TPRn defined region. -*******************************************************************************/ + */ + struct acpi_tprn_base_reg { u64 reserved0:3; - u64 rw:1; // access: 1 == RO, 0 == RW (for TPR must be RW) - u64 enable:1; // 0 == range enabled, 1 == range disabled + u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ + u64 enable:1; /* 0 == range enabled, 1 == range disabled */ u64 reserved1:15; - u64 tpr_base_rw:44; // minimal TPrn_base resolution is 1MB. - // applied to the incoming address, to determine if an - // access fall within the TPrn defined region. - // width is determined by a bus width which can be - // obtainedvia CPUID function 0x80000008. - //u64 unused : 1; + u64 tpr_base_rw:44; /* Minimal TPRn_Base resolution is 1MB. + * Applied to the incoming address, to determine if + * an access fall within the TPRn defined region. + * Width is determined by a bus width which can be + * obtained via CPUID function 0x80000008. + */ + /* u64 unused : 1; */ }; -/******************************************************************************* +/* * TPRn_LIMIT * * This register defines an isolated region of memory that can be enabled * to prohibit certain system agents from accessing memory. When an agent * sends a request upstream, whether snooped or not, a TPR prevents that * transaction from changing the state of memory. -*******************************************************************************/ + */ struct acpi_tprn_limit_reg { u64 reserved0:3; - u64 rw:1; // access: 1 == RO, 0 == RW (for TPR must be RW) - u64 enable:1; // 0 == range enabled, 1 == range disabled + u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ + u64 enable:1; /* 0 == range enabled, 1 == range disabled */ u64 reserved1:15; - u64 tpr_limit_rw:44; // minimal TPrn_limit resolution is 1MB. - // these bits define TPR limit address. - // width is determined by a bus width. + u64 tpr_limit_rw:44; /* Minimal TPRn_Limit resolution is 1MB. + * These bits define TPR limit address. + * Width is determined by a bus width. + */ - //u64 unused : 1; + /* u64 unused : 1; */ }; -/******************************************************************************* +/* * SERIALIZE_REQUEST * * This register is used to request serialization of non-coherent DMA * transactions. OS shall issue it before changing of TPR settings * (base / size). -*******************************************************************************/ + */ struct acpi_tpr_serialize_request { u64 sr_register; - // BIT 1 - status of serialization request (RO) - // 0 == register idle, 1 == serialization in progress - // BIT 2 - control field to initiate serialization (RW) - // 0 == normal, 1 == initialize serialization - // (self-clear to allow multiple serialization requests) + /* + * BIT 1 - Status of serialization request (RO) + * 0 == register idle, 1 == serialization in progress + * BIT 2 - Control field to initiate serialization (RW) + * 0 == normal, 1 == initialize serialization + * (self-clear to allow multiple serialization requests) + */ }; /* Reset to default packing */ -- cgit v1.2.3 From 9b02cf9ee67b284020d051da126694d555977e12 Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:36:32 +0100 Subject: ACPICA: Cleanup comments and DTPR Table handle functions Link: https://github.com/acpica/acpica/commit/cc480264335e Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2042656.yKVeVyVuyW@rafael.j.wysocki --- include/acpi/actbl1.h | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index a580b993cc48..c5ff63fc3b72 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -2003,7 +2003,9 @@ struct acpi_tpr_instance { struct acpi_tpr_aux_sr { u32 srl_cnt; - /* ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; */ + /* + * ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; + */ }; /* @@ -2020,13 +2022,13 @@ struct acpi_tprn_base_reg { u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ u64 enable:1; /* 0 == range enabled, 1 == range disabled */ u64 reserved1:15; - u64 tpr_base_rw:44; /* Minimal TPRn_Base resolution is 1MB. - * Applied to the incoming address, to determine if - * an access fall within the TPRn defined region. - * Width is determined by a bus width which can be - * obtained via CPUID function 0x80000008. + u64 tpr_base_rw:44; /* + * Minimal TPRn_Base resolution is 1MB. + * Applied to the incoming address, to determine if + * an access fall within the TPRn defined region. + * Width is determined by a bus width which can be + * obtained via CPUID function 0x80000008. */ - /* u64 unused : 1; */ }; /* @@ -2043,12 +2045,11 @@ struct acpi_tprn_limit_reg { u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ u64 enable:1; /* 0 == range enabled, 1 == range disabled */ u64 reserved1:15; - u64 tpr_limit_rw:44; /* Minimal TPRn_Limit resolution is 1MB. - * These bits define TPR limit address. - * Width is determined by a bus width. + u64 tpr_limit_rw:44; /* + * Minimal TPRn_Limit resolution is 1MB. + * These bits define TPR limit address. + * Width is determined by a bus width. */ - - /* u64 unused : 1; */ }; /* @@ -2062,11 +2063,11 @@ struct acpi_tprn_limit_reg { struct acpi_tpr_serialize_request { u64 sr_register; /* - * BIT 1 - Status of serialization request (RO) - * 0 == register idle, 1 == serialization in progress - * BIT 2 - Control field to initiate serialization (RW) - * 0 == normal, 1 == initialize serialization - * (self-clear to allow multiple serialization requests) + * BIT 1 - Status of serialization request (RO) + * 0 == register idle, 1 == serialization in progress + * BIT 2 - Control field to initiate serialization (RW) + * 0 == normal, 1 == initialize serialization + * (self-clear to allow multiple serialization requests) */ }; -- cgit v1.2.3 From 691474b1ae63845044a28debe0e06b88a836770b Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:37:19 +0100 Subject: ACPICA: Align comments in TPRn-related structures Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures. Link: https://github.com/acpica/acpica/commit/95815d550969 Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2286538.NgBsaNRSFp@rafael.j.wysocki --- include/acpi/actbl1.h | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index c5ff63fc3b72..cdcda64d1d8e 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1998,14 +1998,10 @@ struct acpi_tpr_array { struct acpi_tpr_instance { u32 flags; u32 tpr_cnt; - struct acpi_tpr_array tpr_array[]; }; struct acpi_tpr_aux_sr { u32 srl_cnt; - /* - * ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; - */ }; /* @@ -2022,13 +2018,14 @@ struct acpi_tprn_base_reg { u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ u64 enable:1; /* 0 == range enabled, 1 == range disabled */ u64 reserved1:15; - u64 tpr_base_rw:44; /* - * Minimal TPRn_Base resolution is 1MB. - * Applied to the incoming address, to determine if - * an access fall within the TPRn defined region. - * Width is determined by a bus width which can be - * obtained via CPUID function 0x80000008. - */ + u64 tpr_base_rw:44; + /* + * Minimal TPRn_Base resolution is 1MB. + * Applied to the incoming address, to determine if + * an access fall within the TPRn defined region. + * Width is determined by a bus width which can be + * obtained via CPUID function 0x80000008. + */ }; /* @@ -2045,11 +2042,12 @@ struct acpi_tprn_limit_reg { u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ u64 enable:1; /* 0 == range enabled, 1 == range disabled */ u64 reserved1:15; - u64 tpr_limit_rw:44; /* - * Minimal TPRn_Limit resolution is 1MB. - * These bits define TPR limit address. - * Width is determined by a bus width. - */ + u64 tpr_limit_rw:44; + /* + * Minimal TPRn_Limit resolution is 1MB. + * These bits define TPR limit address. + * Width is determined by a bus width. + */ }; /* -- cgit v1.2.3 From 099b050699c739797f6dd2bf47f6e15f11504db4 Mon Sep 17 00:00:00 2001 From: Saket Dumbre Date: Wed, 14 Jan 2026 13:38:12 +0100 Subject: ACPICA: Logfile: Changes for version 20251212 Link: https://github.com/acpica/acpica/commit/446be438238e Signed-off-by: Saket Dumbre Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/15657187.tv2OnDr8pf@rafael.j.wysocki --- include/acpi/acpixf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/acpi') diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index e65a2afe9250..49d1749f30bb 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -12,7 +12,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20250807 +#define ACPI_CA_VERSION 0x20251212 #include #include -- cgit v1.2.3 From 3b8907925a7964903955b59d974d98c7ae707d7a Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:39:10 +0100 Subject: ACPICA: Replace TPRn Base and Limit registers Replace TPRn Base and Limit registers with compatible bitmasks for them. Link: https://github.com/acpica/acpica/commit/be91c5813936 Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki --- include/acpi/actbl1.h | 99 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 72 insertions(+), 27 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index cdcda64d1d8e..8331a3494b75 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -2005,28 +2005,57 @@ struct acpi_tpr_aux_sr { }; /* - * TPRn_BASE + * TPRn_BASE (ACPI_TPRN_BASE_REG) * * Specifies the start address of TPRn region. TPR region address and size must * be with 1MB resolution. These bits are compared with the result of the * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an * access fall within the TPRn defined region. + * + * Minimal TPRn_Base resolution is 1MB. + * Applied to the incoming address, to determine if + * an access fall within the TPRn defined region. + * Width is determined by a bus width which can be + * obtained via CPUID function 0x80000008. */ -struct acpi_tprn_base_reg { - u64 reserved0:3; - u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ - u64 enable:1; /* 0 == range enabled, 1 == range disabled */ - u64 reserved1:15; - u64 tpr_base_rw:44; - /* - * Minimal TPRn_Base resolution is 1MB. - * Applied to the incoming address, to determine if - * an access fall within the TPRn defined region. - * Width is determined by a bus width which can be - * obtained via CPUID function 0x80000008. - */ -}; +typedef u64 ACPI_TPRN_BASE_REG; + +/* TPRn_BASE Register Bit Masks */ + +/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ +#define ACPI_TPRN_BASE_RW_SHIFT 3 +#define ACPI_TPRN_BASE_RW_MASK ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT) + +/* + * Bit 4 - Enable: 0 – TPRn address range enabled; + * 1 – TPRn address range disabled. + */ +#define ACPI_TPRN_BASE_ENABLE_SHIFT 4 +#define ACPI_TPRN_BASE_ENABLE_MASK ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT) + +/* Bits 63:20 - tpr_base_rw */ +#define ACPI_TPRN_BASE_ADDR_SHIFT 20 +#define ACPI_TPRN_BASE_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ + ACPI_TPRN_BASE_ADDR_SHIFT) + +/* TPRn_BASE Register Bit Handlers*/ +#define GET_TPRN_BASE_RW(reg) (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >> \ + ACPI_TPRN_BASE_RW_SHIFT) +#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \ + >> ACPI_TPRN_BASE_ENABLE_SHIFT) +#define GET_TPRN_BASE_ADDR(reg) (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK) \ + >> ACPI_TPRN_BASE_ADDR_SHIFT) + +#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_BASE_RW_SHIFT, \ + ACPI_TPRN_BASE_RW_MASK, val); +#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_BASE_ENABLE_SHIFT, \ + ACPI_TPRN_BASE_ENABLE_MASK, val); +#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_BASE_ADDR_SHIFT, \ + ACPI_TPRN_BASE_ADDR_MASK, val); /* * TPRn_LIMIT @@ -2035,20 +2064,36 @@ struct acpi_tprn_base_reg { * to prohibit certain system agents from accessing memory. When an agent * sends a request upstream, whether snooped or not, a TPR prevents that * transaction from changing the state of memory. + * + * Minimal TPRn_Limit resolution is 1MB. + * Width is determined by a bus width */ -struct acpi_tprn_limit_reg { - u64 reserved0:3; - u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */ - u64 enable:1; /* 0 == range enabled, 1 == range disabled */ - u64 reserved1:15; - u64 tpr_limit_rw:44; - /* - * Minimal TPRn_Limit resolution is 1MB. - * These bits define TPR limit address. - * Width is determined by a bus width. - */ -}; +typedef u64 ACPI_TPRN_LIMIT_REG; + +/* TPRn_LIMIT Register Bit Masks */ + +/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ +#define ACPI_TPRN_LIMIT_RW_SHIFT 3 +#define ACPI_TPRN_LIMIT_RW_MASK ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT) + +/* Bits 63:20 - tpr_limit_rw */ +#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20 +#define ACPI_TPRN_LIMIT_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ + ACPI_TPRN_LIMIT_ADDR_SHIFT) + +/* TPRn_LIMIT Register Bit Handlers*/ +#define GET_TPRN_LIMIT_RW(reg) (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK) \ + >> ACPI_TPRN_LIMIT_RW_SHIFT) +#define GET_TPRN_LIMIT_ADDR(reg) (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \ + >> ACPI_TPRN_LIMIT_ADDR_SHIFT) + +#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_LIMIT_RW_SHIFT, \ + ACPI_TPRN_LIMIT_RW_MASK, val); +#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_LIMIT_ADDR_SHIFT, \ + ACPI_TPRN_LIMIT_ADDR_MASK, val); /* * SERIALIZE_REQUEST -- cgit v1.2.3 From e8f614dabd2238e462e4543abd1eb5c59e612836 Mon Sep 17 00:00:00 2001 From: Michal Camacho Romero Date: Wed, 14 Jan 2026 13:40:06 +0100 Subject: ACPICA: Refactor for TPR Base/Limit registers bitmasks Link: https://github.com/acpica/acpica/commit/5cb62a1d4970 Signed-off-by: Michal Camacho Romero Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/3193976.CbtlEUcBR6@rafael.j.wysocki --- include/acpi/actbl1.h | 396 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 256 insertions(+), 140 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 8331a3494b75..4e15583e0d25 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1000,6 +1000,262 @@ struct acpi_drtm_dps_id { u8 dps_id[16]; }; +/******************************************************************************* + * + * DTPR - DMA TXT Protection Ranges Table + * Version 1 + * + * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection + * Ranges", + * Revision 0.73, August 2021 + * + ******************************************************************************/ + +struct acpi_table_dtpr { + struct acpi_table_header header; + u32 flags; /* 36 */ + u32 ins_cnt; +}; + +struct acpi_tpr_array { + u64 base; +}; + +struct acpi_tpr_instance { + u32 flags; + u32 tpr_cnt; +}; + +struct acpi_tpr_aux_sr { + u32 srl_cnt; +}; + +/* + * TPRn_BASE (ACPI_TPRN_BASE_REG) + * + * Specifies the start address of TPRn region. TPR region address and size must + * be with 1MB resolution. These bits are compared with the result of the + * TPRn_LIMIT[63:20], which is applied to the incoming address, to + * determine if an access fall within the TPRn defined region. + * + * Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to + * determine if an access fall within the TPRn defined region. Width is + * determined by a bus width which can be obtained via CPUID + * function 0x80000008. + */ + +typedef u64 ACPI_TPRN_BASE_REG; + +/* TPRn_BASE Register Bit Masks */ + +/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ +#define ACPI_TPRN_BASE_RW_SHIFT 3 + +#define ACPI_TPRN_BASE_RW_MASK ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT) + +/* + * Bit 4 - Enable: 0 – TPRn address range enabled; + * 1 – TPRn address range disabled. + */ +#define ACPI_TPRN_BASE_ENABLE_SHIFT 4 + +#define ACPI_TPRN_BASE_ENABLE_MASK ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT) + +/* Bits 63:20 - tpr_base_rw */ +#define ACPI_TPRN_BASE_ADDR_SHIFT 20 + +#define ACPI_TPRN_BASE_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ + ACPI_TPRN_BASE_ADDR_SHIFT) + +/* TPRn_BASE Register Bit Handlers*/ + +/* + * GET_TPRN_BASE_RW: + * + * Read RW bit from TPRn Base register - bit 3. + * + * Input: + * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) + * + * Output: + * + * Returns RW bit value (u64). + */ +#define GET_TPRN_BASE_RW(reg) (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >> \ + ACPI_TPRN_BASE_RW_SHIFT) + +/* + * GET_TPRN_BASE_ENABLE: + * + * Read Enable bit from TPRn Base register - bit 4. + * + * Input: + * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) + * + * Output: + * + * Returns Enable bit value (u64). + */ +#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \ + >> ACPI_TPRN_BASE_ENABLE_SHIFT) + +/* + * GET_TPRN_BASE_ADDR: + * + * Read TPRn Base Register address from bits 63:20. + * + * Input: + * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) + * + * Output: + * + * Returns TPRn Base Register address (u64). + */ +#define GET_TPRN_BASE_ADDR(reg) (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK) \ + >> ACPI_TPRN_BASE_ADDR_SHIFT) + +/* + * SET_TPRN_BASE_RW: + * + * Set RW bit in TPRn Base register - bit 3. + * + * Input: + * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) + * - val (represents RW value to be set (u64)) + */ +#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_BASE_RW_SHIFT, \ + ACPI_TPRN_BASE_RW_MASK, val); + +/* + * SET_TPRN_BASE_ENABLE: + * + * Set Enable bit in TPRn Base register - bit 4. + * + * Input: + * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) + * - val (represents Enable value to be set (u64)) + */ +#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_BASE_ENABLE_SHIFT, \ + ACPI_TPRN_BASE_ENABLE_MASK, val); + +/* + * SET_TPRN_BASE_ADDR: + * + * Set TPRn Base Register address - bits 63:20 + * + * Input + * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) + * - val (represents address value to be set (u64)) + */ +#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_BASE_ADDR_SHIFT, \ + ACPI_TPRN_BASE_ADDR_MASK, val); + +/* + * TPRn_LIMIT + * + * This register defines an isolated region of memory that can be enabled + * to prohibit certain system agents from accessing memory. When an agent + * sends a request upstream, whether snooped or not, a TPR prevents that + * transaction from changing the state of memory. + * + * Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width. + */ + +typedef u64 ACPI_TPRN_LIMIT_REG; + +/* TPRn_LIMIT Register Bit Masks */ + +/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ +#define ACPI_TPRN_LIMIT_RW_SHIFT 3 + +#define ACPI_TPRN_LIMIT_RW_MASK ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT) + +/* Bits 63:20 - tpr_limit_rw */ +#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20 + +#define ACPI_TPRN_LIMIT_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ + ACPI_TPRN_LIMIT_ADDR_SHIFT) + +/* TPRn_LIMIT Register Bit Handlers*/ + +/* + * GET_TPRN_LIMIT_RW: + * + * Read RW bit from TPRn Limit register - bit 3. + * + * Input: + * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) + * + * Output: + * + * Returns RW bit value (u64). + */ +#define GET_TPRN_LIMIT_RW(reg) (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK) \ + >> ACPI_TPRN_LIMIT_RW_SHIFT) + +/* + * GET_TPRN_LIMIT_ADDR: + * + * Read TPRn Limit Register address from bits 63:20. + * + * Input: + * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) + * + * Output: + * + * Returns TPRn Limit Register address (u64). + */ +#define GET_TPRN_LIMIT_ADDR(reg) (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \ + >> ACPI_TPRN_LIMIT_ADDR_SHIFT) + +/* + * SET_TPRN_LIMIT_RW: + * + * Set RW bit in TPRn Limit register - bit 3. + * + * Input: + * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) + * - val (represents RW value to be set (u64)) + */ +#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_LIMIT_RW_SHIFT, \ + ACPI_TPRN_LIMIT_RW_MASK, val); + +/* + * SET_TPRN_LIMIT_ADDR: + * + * Set TPRn Limit Register address - bits 63:20. + * + * Input: + * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) + * - val (represents address value to be set (u64)) + */ +#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ + ACPI_TPRN_LIMIT_ADDR_SHIFT, \ + ACPI_TPRN_LIMIT_ADDR_MASK, val); + +/* + * SERIALIZE_REQUEST + * + * This register is used to request serialization of non-coherent DMA + * transactions. OS shall issue it before changing of TPR settings + * (base / size). + */ + +struct acpi_tpr_serialize_request { + u64 sr_register; + /* + * BIT 1 - Status of serialization request (RO) + * 0 == register idle, 1 == serialization in progress + * BIT 2 - Control field to initiate serialization (RW) + * 0 == normal, 1 == initialize serialization + * (self-clear to allow multiple serialization requests) + */ +}; + /******************************************************************************* * * ECDT - Embedded Controller Boot Resources Table @@ -1974,146 +2230,6 @@ struct acpi_ibft_target { u16 reverse_chap_secret_offset; }; -/******************************************************************************* - * - * DTPR - DMA TXT Protection Ranges Table - * Version 1 - * - * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection - * Ranges", - * Revision 0.73, August 2021 - * - ******************************************************************************/ - -struct acpi_table_dtpr { - struct acpi_table_header header; - u32 flags; /* 36 */ - u32 ins_cnt; -}; - -struct acpi_tpr_array { - u64 base; -}; - -struct acpi_tpr_instance { - u32 flags; - u32 tpr_cnt; -}; - -struct acpi_tpr_aux_sr { - u32 srl_cnt; -}; - -/* - * TPRn_BASE (ACPI_TPRN_BASE_REG) - * - * Specifies the start address of TPRn region. TPR region address and size must - * be with 1MB resolution. These bits are compared with the result of the - * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an - * access fall within the TPRn defined region. - * - * Minimal TPRn_Base resolution is 1MB. - * Applied to the incoming address, to determine if - * an access fall within the TPRn defined region. - * Width is determined by a bus width which can be - * obtained via CPUID function 0x80000008. - */ - -typedef u64 ACPI_TPRN_BASE_REG; - -/* TPRn_BASE Register Bit Masks */ - -/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ -#define ACPI_TPRN_BASE_RW_SHIFT 3 -#define ACPI_TPRN_BASE_RW_MASK ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT) - -/* - * Bit 4 - Enable: 0 – TPRn address range enabled; - * 1 – TPRn address range disabled. - */ -#define ACPI_TPRN_BASE_ENABLE_SHIFT 4 -#define ACPI_TPRN_BASE_ENABLE_MASK ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT) - -/* Bits 63:20 - tpr_base_rw */ -#define ACPI_TPRN_BASE_ADDR_SHIFT 20 -#define ACPI_TPRN_BASE_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ - ACPI_TPRN_BASE_ADDR_SHIFT) - -/* TPRn_BASE Register Bit Handlers*/ -#define GET_TPRN_BASE_RW(reg) (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >> \ - ACPI_TPRN_BASE_RW_SHIFT) -#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \ - >> ACPI_TPRN_BASE_ENABLE_SHIFT) -#define GET_TPRN_BASE_ADDR(reg) (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK) \ - >> ACPI_TPRN_BASE_ADDR_SHIFT) - -#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ - ACPI_TPRN_BASE_RW_SHIFT, \ - ACPI_TPRN_BASE_RW_MASK, val); -#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ - ACPI_TPRN_BASE_ENABLE_SHIFT, \ - ACPI_TPRN_BASE_ENABLE_MASK, val); -#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ - ACPI_TPRN_BASE_ADDR_SHIFT, \ - ACPI_TPRN_BASE_ADDR_MASK, val); - -/* - * TPRn_LIMIT - * - * This register defines an isolated region of memory that can be enabled - * to prohibit certain system agents from accessing memory. When an agent - * sends a request upstream, whether snooped or not, a TPR prevents that - * transaction from changing the state of memory. - * - * Minimal TPRn_Limit resolution is 1MB. - * Width is determined by a bus width - */ - -typedef u64 ACPI_TPRN_LIMIT_REG; - -/* TPRn_LIMIT Register Bit Masks */ - -/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ -#define ACPI_TPRN_LIMIT_RW_SHIFT 3 -#define ACPI_TPRN_LIMIT_RW_MASK ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT) - -/* Bits 63:20 - tpr_limit_rw */ -#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20 -#define ACPI_TPRN_LIMIT_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ - ACPI_TPRN_LIMIT_ADDR_SHIFT) - -/* TPRn_LIMIT Register Bit Handlers*/ -#define GET_TPRN_LIMIT_RW(reg) (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK) \ - >> ACPI_TPRN_LIMIT_RW_SHIFT) -#define GET_TPRN_LIMIT_ADDR(reg) (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \ - >> ACPI_TPRN_LIMIT_ADDR_SHIFT) - -#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ - ACPI_TPRN_LIMIT_RW_SHIFT, \ - ACPI_TPRN_LIMIT_RW_MASK, val); -#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ - ACPI_TPRN_LIMIT_ADDR_SHIFT, \ - ACPI_TPRN_LIMIT_ADDR_MASK, val); - -/* - * SERIALIZE_REQUEST - * - * This register is used to request serialization of non-coherent DMA - * transactions. OS shall issue it before changing of TPR settings - * (base / size). - */ - -struct acpi_tpr_serialize_request { - u64 sr_register; - /* - * BIT 1 - Status of serialization request (RO) - * 0 == register idle, 1 == serialization in progress - * BIT 2 - Control field to initiate serialization (RW) - * 0 == normal, 1 == initialize serialization - * (self-clear to allow multiple serialization requests) - */ -}; - /* Reset to default packing */ #pragma pack() -- cgit v1.2.3 From f82c3e62b6b8c31d8c56415bf38658f306fda4cb Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 16 Oct 2025 20:08:15 +0100 Subject: Revert "mailbox/pcc: support mailbox management of the shared buffer" This reverts commit 5378bdf6a611a32500fccf13d14156f219bb0c85. Commit 5378bdf6a611 ("mailbox/pcc: support mailbox management of the shared buffer") attempted to introduce generic helpers for managing the PCC shared memory, but it largely duplicates functionality already provided by the mailbox core and leaves gaps: 1. TX preparation: The mailbox framework already supports this via ->tx_prepare callback for mailbox clients. The patch adds pcc_write_to_buffer() and expects clients to toggle pchan->chan.manage_writes, but no drivers set manage_writes, so pcc_write_to_buffer() has no users. 2. RX handling: Data reception is already delivered through mbox_chan_received_data() and client ->rx_callback. The patch adds an optional pchan->chan.rx_alloc, which again has no users and duplicates the existing path. 3. Completion handling: While adding last_tx_done is directionally useful, the implementation only covers Type 3/4 and fails to handle the absence of a command_complete register, so it is incomplete for other types. Given the duplication and incomplete coverage, revert this change. Any new requirements should be addressed in focused follow-ups rather than bundling multiple behavioral changes together. Fixes: 5378bdf6a611 ("mailbox/pcc: support mailbox management of the shared buffer") Signed-off-by: Sudeep Holla Signed-off-by: Jassi Brar --- include/acpi/pcc.h | 29 ----------------------------- 1 file changed, 29 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/pcc.h b/include/acpi/pcc.h index 9af3b502f839..840bfc95bae3 100644 --- a/include/acpi/pcc.h +++ b/include/acpi/pcc.h @@ -17,35 +17,6 @@ struct pcc_mbox_chan { u32 latency; u32 max_access_rate; u16 min_turnaround_time; - - /* Set to true to indicate that the mailbox should manage - * writing the dat to the shared buffer. This differs from - * the case where the drivesr are writing to the buffer and - * using send_data only to ring the doorbell. If this flag - * is set, then the void * data parameter of send_data must - * point to a kernel-memory buffer formatted in accordance with - * the PCC specification. - * - * The active buffer management will include reading the - * notify_on_completion flag, and will then - * call mbox_chan_txdone when the acknowledgment interrupt is - * received. - */ - bool manage_writes; - - /* Optional callback that allows the driver - * to allocate the memory used for receiving - * messages. The return value is the location - * inside the buffer where the mailbox should write the data. - */ - void *(*rx_alloc)(struct mbox_client *cl, int size); -}; - -struct pcc_header { - u32 signature; - u32 flags; - u32 length; - u32 command; }; /* Generic Communications Channel Shared Memory Region */ -- cgit v1.2.3 From f9cadb3d56912a70571fdd95f426b757557c465b Mon Sep 17 00:00:00 2001 From: Jie Zhan Date: Tue, 23 Dec 2025 15:21:17 +0800 Subject: ACPI: CPPC: Factor out and export per-cpu cppc_perf_ctrs_in_pcc_cpu() Factor out cppc_perf_ctrs_in_pcc_cpu() for checking whether per-cpu CPC regs are defined in PCC channels, and export it out for further use. Reviewed-by: Lifeng Zheng Reviewed-by: Pierre Gondois Signed-off-by: Jie Zhan Acked-by: Rafael J. Wysocki (Intel) Signed-off-by: Viresh Kumar --- include/acpi/cppc_acpi.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/acpi') diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 13fa81504844..4bcdcaf8bf2c 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -154,6 +154,7 @@ extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); +extern bool cppc_perf_ctrs_in_pcc_cpu(unsigned int cpu); extern bool cppc_perf_ctrs_in_pcc(void); extern unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf); extern unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq); @@ -204,6 +205,10 @@ static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps) { return -EOPNOTSUPP; } +static inline bool cppc_perf_ctrs_in_pcc_cpu(unsigned int cpu) +{ + return false; +} static inline bool cppc_perf_ctrs_in_pcc(void) { return false; -- cgit v1.2.3 From 7cb6f10ce3edc9b7bb543daafd72c396a96978ee Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 20 Jan 2026 20:26:16 +0530 Subject: ACPI: CPPC: Clean up cppc_perf_caps and cppc_perf_ctrls structs - Remove redundant energy_perf field from 'struct cppc_perf_caps' as the same is available in 'struct cppc_perf_ctrls' which is used. - Move the 'auto_sel' field from 'struct cppc_perf_caps' to 'struct cppc_perf_ctrls' as it represents a control register. Signed-off-by: Sumit Gupta Reviewed-by: Pierre Gondois Reviewed-by: Lifeng Zheng Link: https://patch.msgid.link/20260120145623.2959636-3-sumitg@nvidia.com Signed-off-by: Rafael J. Wysocki --- include/acpi/cppc_acpi.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/acpi') diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 13fa81504844..a090b010f5f1 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -119,8 +119,6 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; - u32 energy_perf; - bool auto_sel; }; struct cppc_perf_ctrls { @@ -128,6 +126,7 @@ struct cppc_perf_ctrls { u32 min_perf; u32 desired_perf; u32 energy_perf; + bool auto_sel; }; struct cppc_perf_fb_ctrs { -- cgit v1.2.3 From 83e2908c1d425a6ef2e96457ad95b886b8ddfc48 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 20 Jan 2026 20:26:17 +0530 Subject: ACPI: CPPC: Rename EPP constants for clarity Update EPP (Energy Performance Preference) constants for more clarity: - Add CPPC_EPP_PERFORMANCE_PREF (0x00) for performance preference. - Rename CPPC_ENERGY_PERF_MAX to CPPC_EPP_ENERGY_EFFICIENCY_PREF (0xFF) for energy efficiency. Signed-off-by: Sumit Gupta Reviewed-by: Lifeng Zheng [ rjw: Changelog edits ] Link: https://patch.msgid.link/20260120145623.2959636-4-sumitg@nvidia.com Signed-off-by: Rafael J. Wysocki --- include/acpi/cppc_acpi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/acpi') diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index a090b010f5f1..44d41ecb1b1d 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -39,7 +39,8 @@ /* CPPC_AUTO_ACT_WINDOW_MAX_SIG is 127, so 128 and 129 will decay to 127 when writing */ #define CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH 129 -#define CPPC_ENERGY_PERF_MAX (0xFF) +#define CPPC_EPP_PERFORMANCE_PREF 0x00 +#define CPPC_EPP_ENERGY_EFFICIENCY_PREF 0xFF /* Each register has the folowing format. */ struct cpc_reg { -- cgit v1.2.3