From 285f5fa7e9a35e75d9022f9b036ed709721c5cdf Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Thu, 7 Dec 2006 02:59:39 +0100 Subject: [ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/uncompress.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/asm-arm/arch-iop13xx/uncompress.h (limited to 'include/asm-arm/arch-iop13xx/uncompress.h') diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h new file mode 100644 index 000000000000..b9525d59b7ad --- /dev/null +++ b/include/asm-arm/arch-iop13xx/uncompress.h @@ -0,0 +1,24 @@ +#include +#include +#include +#include + +#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) + cpu_relax(); + UART_BASE[UART_TX] = c; +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() -- cgit v1.2.3