From c0feb268da73ae3ede23ae60d6ccc551c4e93250 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 8 Dec 2015 14:46:54 +0100 Subject: clk: samsung: exynos542x: add missing parent GSCL block clocks This patch adds clocks, which are required for preserving parent clock configuration on GSCL power domain on/off. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5420.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/dt-bindings/clock/exynos5420.h') diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 99da0d117a7d..b5af23afb974 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -210,6 +210,8 @@ #define CLK_MOUT_SW_ACLK300 649 #define CLK_MOUT_USER_ACLK400_DISP1 650 #define CLK_MOUT_SW_ACLK400 651 +#define CLK_MOUT_USER_ACLK300_GSCL 652 +#define CLK_MOUT_SW_ACLK300_GSCL 653 /* divider clocks */ #define CLK_DOUT_PIXEL 768 -- cgit v1.2.3