From 17f458d0a4373b8c6d824b343b1b3dad9532c2f3 Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Thu, 22 Aug 2019 20:03:48 +0800 Subject: clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock The mipi pll clock comes from the MIPI PHY PLL output, so it should not be a fixed clock. MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock for transfering the pixel data out and its output clock is configured according to the display mode. So it should be used only for MIPI DSI and not be exported out for other usages. Signed-off-by: Fancy Fang --- include/dt-bindings/clock/imx7ulp-clock.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 6f66f9005c81..f8d34fb4378f 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -49,15 +49,14 @@ #define IMX7ULP_CLK_NIC1_DIV 36 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 #define IMX7ULP_CLK_NIC1_EXT_DIV 38 -#define IMX7ULP_CLK_MIPI_PLL 39 -#define IMX7ULP_CLK_SIRC 40 -#define IMX7ULP_CLK_SOSC_BUS_CLK 41 -#define IMX7ULP_CLK_FIRC_BUS_CLK 42 -#define IMX7ULP_CLK_SPLL_BUS_CLK 43 -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 +#define IMX7ULP_CLK_SIRC 39 +#define IMX7ULP_CLK_SOSC_BUS_CLK 40 +#define IMX7ULP_CLK_FIRC_BUS_CLK 41 +#define IMX7ULP_CLK_SPLL_BUS_CLK 42 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 43 +#define IMX7ULP_CLK_HSRUN_CORE_DIV 44 -#define IMX7ULP_CLK_SCG1_END 46 +#define IMX7ULP_CLK_SCG1_END 45 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 -- cgit v1.2.3