From ef98682a4e1257ff45405bb1372939e8dfe774bb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 11 May 2019 00:15:22 +0530 Subject: dt-bindings: reset: Add devicetree binding for BM1880 reset controller Add devicetree binding for Bitmain BM1880 SoC reset controller. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Philipp Zabel --- include/dt-bindings/reset/bitmain,bm1880-reset.h | 51 ++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 include/dt-bindings/reset/bitmain,bm1880-reset.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/reset/bitmain,bm1880-reset.h b/include/dt-bindings/reset/bitmain,bm1880-reset.h new file mode 100644 index 000000000000..4c0de5223773 --- /dev/null +++ b/include/dt-bindings/reset/bitmain,bm1880-reset.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Bitmain Ltd. + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_BM1880_RESET_H +#define _DT_BINDINGS_BM1880_RESET_H + +#define BM1880_RST_MAIN_AP 0 +#define BM1880_RST_SECOND_AP 1 +#define BM1880_RST_DDR 2 +#define BM1880_RST_VIDEO 3 +#define BM1880_RST_JPEG 4 +#define BM1880_RST_VPP 5 +#define BM1880_RST_GDMA 6 +#define BM1880_RST_AXI_SRAM 7 +#define BM1880_RST_TPU 8 +#define BM1880_RST_USB 9 +#define BM1880_RST_ETH0 10 +#define BM1880_RST_ETH1 11 +#define BM1880_RST_NAND 12 +#define BM1880_RST_EMMC 13 +#define BM1880_RST_SD 14 +#define BM1880_RST_SDMA 15 +#define BM1880_RST_I2S0 16 +#define BM1880_RST_I2S1 17 +#define BM1880_RST_UART0_1_CLK 18 +#define BM1880_RST_UART0_1_ACLK 19 +#define BM1880_RST_UART2_3_CLK 20 +#define BM1880_RST_UART2_3_ACLK 21 +#define BM1880_RST_MINER 22 +#define BM1880_RST_I2C0 23 +#define BM1880_RST_I2C1 24 +#define BM1880_RST_I2C2 25 +#define BM1880_RST_I2C3 26 +#define BM1880_RST_I2C4 27 +#define BM1880_RST_PWM0 28 +#define BM1880_RST_PWM1 29 +#define BM1880_RST_PWM2 30 +#define BM1880_RST_PWM3 31 +#define BM1880_RST_SPI 32 +#define BM1880_RST_GPIO0 33 +#define BM1880_RST_GPIO1 34 +#define BM1880_RST_GPIO2 35 +#define BM1880_RST_EFUSE 36 +#define BM1880_RST_WDT 37 +#define BM1880_RST_AHB_ROM 38 +#define BM1880_RST_SPIC 39 + +#endif /* _DT_BINDINGS_BM1880_RESET_H */ -- cgit v1.2.3 From 0cb93b1503c19f19966402c3ed841626ac9db266 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 13 May 2019 15:50:10 +0530 Subject: dt-bindings: power: Add rpm power domain bindings for qcs404 Add RPM power domain bindings for the qcs404 family of SoC Reviewed-by: Rob Herring Reviewed-by: Jeffrey Hugo Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson [sibis: Add supported rpmpd states for qcs404] Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- include/dt-bindings/power/qcom-rpmpd.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 87d9c6611682..450378662944 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -36,4 +36,26 @@ #define MSM8996_VDDSSCX 5 #define MSM8996_VDDSSCX_VFC 6 +/* QCS404 Power Domains */ +#define QCS404_VDDMX 0 +#define QCS404_VDDMX_AO 1 +#define QCS404_VDDMX_VFL 2 +#define QCS404_LPICX 3 +#define QCS404_LPICX_VFL 4 +#define QCS404_LPIMX 5 +#define QCS404_LPIMX_VFL 6 + +/* RPM SMD Power Domain performance levels */ +#define RPM_SMD_LEVEL_RETENTION 16 +#define RPM_SMD_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_LEVEL_MIN_SVS 48 +#define RPM_SMD_LEVEL_LOW_SVS 64 +#define RPM_SMD_LEVEL_SVS 128 +#define RPM_SMD_LEVEL_SVS_PLUS 192 +#define RPM_SMD_LEVEL_NOM 256 +#define RPM_SMD_LEVEL_NOM_PLUS 320 +#define RPM_SMD_LEVEL_TURBO 384 +#define RPM_SMD_LEVEL_TURBO_NO_CPR 416 +#define RPM_SMD_LEVEL_BINNING 512 + #endif -- cgit v1.2.3 From dec9a05a147e4988e1f743c0d0a1389a0552e322 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 13 May 2019 15:50:13 +0530 Subject: dt-bindings: power: Add rpm power domain bindings for msm8998 Add RPM power domain bindings for the msm8998 family of SoC Reviewed-by: Rob Herring Reviewed-by: Jeffrey Hugo Reviewed-by: Vinod Koul Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- include/dt-bindings/power/qcom-rpmpd.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 450378662944..93e36d011527 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -36,6 +36,18 @@ #define MSM8996_VDDSSCX 5 #define MSM8996_VDDSSCX_VFC 6 +/* MSM8998 Power Domain Indexes */ +#define MSM8998_VDDCX 0 +#define MSM8998_VDDCX_AO 1 +#define MSM8998_VDDCX_VFL 2 +#define MSM8998_VDDMX 3 +#define MSM8998_VDDMX_AO 4 +#define MSM8998_VDDMX_VFL 5 +#define MSM8998_SSCCX 6 +#define MSM8998_SSCCX_VFL 7 +#define MSM8998_SSCMX 8 +#define MSM8998_SSCMX_VFL 9 + /* QCS404 Power Domains */ #define QCS404_VDDMX 0 #define QCS404_VDDMX_AO 1 -- cgit v1.2.3 From 8ad2b4b371bcfe7069ee28ad18d722e1240a0a97 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 11 Jun 2019 21:45:33 -0700 Subject: dt-bindings: soc: qcom: Add AOSS QMP binding Add binding for the QMP based side-channel communication mechanism to the AOSS, which is used to control resources not exposed through the RPMh interface. Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- include/dt-bindings/power/qcom-aoss-qmp.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h new file mode 100644 index 000000000000..ec336d31dee4 --- /dev/null +++ b/include/dt-bindings/power/qcom-aoss-qmp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H + +#define AOSS_QMP_LS_CDSP 0 +#define AOSS_QMP_LS_LPASS 1 +#define AOSS_QMP_LS_MODEM 2 +#define AOSS_QMP_LS_SLPI 3 +#define AOSS_QMP_LS_SPSS 4 +#define AOSS_QMP_LS_VENUS 5 + +#endif -- cgit v1.2.3