From 8ba338783196af05fc7bae0e3e57bccc8728d211 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Mon, 29 Jul 2019 16:57:33 +0800 Subject: clk: imx: scu: remove legacy scu clock binding support remove legacy scu clock binding support to avoid confusing Signed-off-by: Dong Aisheng --- include/dt-bindings/clock/imx8-clock.h | 161 --------------------------------- 1 file changed, 161 deletions(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 91a99f5250b0..50a1090a1f5b 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -7,167 +7,6 @@ #ifndef __DT_BINDINGS_CLOCK_IMX_H #define __DT_BINDINGS_CLOCK_IMX_H -/* SCU Clocks */ - -#define IMX_CLK_DUMMY 0 - -/* CPU */ -#define IMX_A35_CLK 1 - -#define IMX_24MHZ 4 - -#define IMX_24MHZ 4 - -/* LSIO SS */ -#define IMX_LSIO_MEM_CLK 2 -#define IMX_LSIO_BUS_CLK 3 -#define IMX_LSIO_PWM0_CLK 10 -#define IMX_LSIO_PWM1_CLK 11 -#define IMX_LSIO_PWM2_CLK 12 -#define IMX_LSIO_PWM3_CLK 13 -#define IMX_LSIO_PWM4_CLK 14 -#define IMX_LSIO_PWM5_CLK 15 -#define IMX_LSIO_PWM6_CLK 16 -#define IMX_LSIO_PWM7_CLK 17 -#define IMX_LSIO_GPT0_CLK 18 -#define IMX_LSIO_GPT1_CLK 19 -#define IMX_LSIO_GPT2_CLK 20 -#define IMX_LSIO_GPT3_CLK 21 -#define IMX_LSIO_GPT4_CLK 22 -#define IMX_LSIO_FSPI0_CLK 23 -#define IMX_LSIO_FSPI1_CLK 24 - -/* Connectivity SS */ -#define IMX_CONN_AXI_CLK_ROOT 30 -#define IMX_CONN_AHB_CLK_ROOT 31 -#define IMX_CONN_IPG_CLK_ROOT 32 -#define IMX_CONN_PLL0_CLK 33 -#define IMX_CONN_PLL1_CLK 34 -#define IMX_CONN_SDHC0_CLK 40 -#define IMX_CONN_SDHC1_CLK 41 -#define IMX_CONN_SDHC2_CLK 42 -#define IMX_CONN_ENET0_ROOT_CLK 43 -#define IMX_CONN_ENET0_BYPASS_CLK 44 -#define IMX_CONN_ENET0_RGMII_RX_CLK 45 -#define IMX_CONN_ENET1_ROOT_CLK 46 -#define IMX_CONN_ENET1_BYPASS_CLK 47 -#define IMX_CONN_ENET1_RGMII_RX_CLK 48 -#define IMX_CONN_GPMI_BCH_IO_CLK 49 -#define IMX_CONN_GPMI_BCH_CLK 50 -#define IMX_CONN_USB2_ACLK 51 -#define IMX_CONN_USB2_BUS_CLK 52 -#define IMX_CONN_USB2_LPM_CLK 53 -#define IMX_CONN_ENET0_REF_DIV 54 -#define IMX_CONN_ENET0_RGMII_TXC_SEL 55 -#define IMX_CONN_ENET1_REF_DIV 56 -#define IMX_CONN_ENET1_RGMII_TXC_SEL 57 -#define IMX_CONN_ENET0_RMII_REF_50MHZ_CLK 58 -#define IMX_CONN_ENET1_RMII_REF_50MHZ_CLK 59 - -/* HSIO SS */ -#define IMX_HSIO_AXI_CLK 60 -#define IMX_HSIO_PER_CLK 61 - -/* Display controller SS */ -#define IMX_DC_AXI_EXT_CLK 70 -#define IMX_DC_AXI_INT_CLK 71 -#define IMX_DC_CFG_CLK 72 -#define IMX_DC0_PLL0_CLK 80 -#define IMX_DC0_PLL1_CLK 81 -#define IMX_DC0_DISP0_CLK 82 -#define IMX_DC0_DISP1_CLK 83 -#define IMX_DC0_BYPASS0_CLK 84 -#define IMX_DC0_BYPASS1_CLK 85 - -/* MIPI-LVDS SS */ -#define IMX_MIPI_IPG_CLK 90 -#define IMX_MIPI1_DSI_TX_ESC_CLK 98 -#define IMX_MIPI1_DSI_RX_ESC_CLK 99 -#define IMX_MIPI0_PIXEL_CLK 100 -#define IMX_MIPI0_BYPASS_CLK 101 -#define IMX_LVDS0_PIXEL_CLK 102 -#define IMX_LVDS0_BYPASS_CLK 103 -#define IMX_LVDS0_PHY_CLK 104 -#define IMX_MIPI0_I2C0_CLK 105 -#define IMX_MIPI0_I2C1_CLK 106 -#define IMX_MIPI0_PWM0_CLK 107 -#define IMX_MIPI1_PIXEL_CLK 108 -#define IMX_MIPI1_BYPASS_CLK 109 -#define IMX_LVDS1_PIXEL_CLK 110 -#define IMX_LVDS1_BYPASS_CLK 111 -#define IMX_LVDS1_PHY_CLK 112 -#define IMX_MIPI1_I2C0_CLK 113 -#define IMX_MIPI1_I2C1_CLK 114 -#define IMX_MIPI1_PWM0_CLK 115 -#define IMX_MIPI0_DSI_TX_ESC_CLK 116 -#define IMX_MIPI0_DSI_RX_ESC_CLK 117 -#define IMX_MIPI0_DSI_PHY_CLK 118 - -/* IMG SS */ -#define IMX_IMG_AXI_CLK 120 -#define IMX_IMG_IPG_CLK 121 -#define IMX_IMG_PXL_CLK 122 - -/* MIPI-CSI SS */ -#define IMX_CSI0_CORE_CLK 130 -#define IMX_CSI0_ESC_CLK 131 -#define IMX_CSI0_PWM0_CLK 132 -#define IMX_CSI0_I2C0_CLK 133 -#define IMX_CSI1_CORE_CLK 134 -#define IMX_CSI1_ESC_CLK 135 -#define IMX_CSI1_PWM0_CLK 136 -#define IMX_CSI1_I2C0_CLK 137 - -/* PARALLER CSI SS */ -#define IMX_PARALLEL_DPLL_CLK 140 -#define IMX_PARALLEL_PER_DIV_CLK 141 -#define IMX_PARALLEL_MCLK_DIV_CLK 142 - -/* VPU SS */ -#define IMX_VPU_ENC_CLK 150 -#define IMX_VPU_DEC_CLK 151 - -/* GPU SS */ -#define IMX_GPU0_CORE_CLK 160 -#define IMX_GPU0_SHADER_CLK 161 - -/* ADMA SS */ -#define IMX_ADMA_IPG_CLK_ROOT 165 -#define IMX_ADMA_UART0_CLK 170 -#define IMX_ADMA_UART1_CLK 171 -#define IMX_ADMA_UART2_CLK 172 -#define IMX_ADMA_UART3_CLK 173 -#define IMX_ADMA_SPI0_CLK 174 -#define IMX_ADMA_SPI1_CLK 175 -#define IMX_ADMA_SPI2_CLK 176 -#define IMX_ADMA_SPI3_CLK 177 -#define IMX_ADMA_CAN0_CLK 178 -#define IMX_ADMA_CAN1_CLK 179 -#define IMX_ADMA_CAN2_CLK 180 -#define IMX_ADMA_I2C0_CLK 181 -#define IMX_ADMA_I2C1_CLK 182 -#define IMX_ADMA_I2C2_CLK 183 -#define IMX_ADMA_I2C3_CLK 184 -#define IMX_ADMA_FTM0_CLK 185 -#define IMX_ADMA_FTM1_CLK 186 -#define IMX_ADMA_ADC0_CLK 187 -#define IMX_ADMA_PWM_CLK 188 -#define IMX_ADMA_LCD_CLK 189 - -#define IMX_ADMA_AUD_PLL0 191 -#define IMX_ADMA_AUD_PLL1 192 - -#define IMX_ADMA_AUD_PLL_DIV_CLK0_CLK 193 -#define IMX_ADMA_AUD_PLL_DIV_CLK1_CLK 194 -#define IMX_ADMA_AUD_REC_CLK0_CLK 195 -#define IMX_ADMA_AUD_REC_CLK1_CLK 196 - -/* CM40 SS */ -#define IMX_CM40_IPG_CLK 200 -#define IMX_CM40_I2C_DIV 205 - -#define IMX_SCU_CLK_END 220 - #define IMX_ADMA_ACM_AUD_CLK0_SEL 0 #define IMX_ADMA_ACM_AUD_CLK0_CLK 1 #define IMX_ADMA_ACM_AUD_CLK1_SEL 2 -- cgit v1.2.3