From ee9fdb415639032d1bb1b59b83f210958e29764f Mon Sep 17 00:00:00 2001 From: Daniil Titov Date: Wed, 12 Feb 2025 18:04:09 +0100 Subject: dt-bindings: clock: qcom,rpmcc: Add SDM429 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the qcom,rpmcc-sdm429 compatible and add BB_CLK3 clock definition. Signed-off-by: Daniil Titov Signed-off-by: Barnabás Czémán Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250212-sdm429-rpm-v1-1-0a24ac19a478@mainlining.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,rpmcc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 46309c9953b2..1477a75e7f6d 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -170,5 +170,9 @@ #define RPM_SMD_BIMC_FREQ_LOG 124 #define RPM_SMD_LN_BB_CLK_PIN 125 #define RPM_SMD_LN_BB_A_CLK_PIN 126 +#define RPM_SMD_BB_CLK3 127 +#define RPM_SMD_BB_CLK3_A 128 +#define RPM_SMD_BB_CLK3_PIN 129 +#define RPM_SMD_BB_CLK3_A_PIN 130 #endif -- cgit v1.2.3 From 1ae674f0871722215a684b4c8e1e20a7912ec7e4 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Mon, 3 Feb 2025 09:34:24 +0300 Subject: dt-bindings: clock: gcc-sdm660: Add missing SDCC resets Add resets for eMMC/SD card blocks that were missed during initial driver submission. Signed-off-by: Alexey Minnekhanov Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250203063427.358327-2-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-sdm660.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h index df8a6f3d367e..74c22f67da21 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm660.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -153,5 +153,7 @@ #define GCC_USB_30_BCR 7 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 #define GCC_MSS_RESTART 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 #endif -- cgit v1.2.3 From 6c9edce7a0e91c33ac800a83e160da6475c4bdab Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 9 Jan 2025 14:27:44 +0530 Subject: dt-bindings: clock: qcom: Add GPU clocks for QCS8300 The QCS8300 GPU clock controller is a derivative of SA8775P, but has few additional clocks and minor differences. Hence, reuse gpucc bindings of SA8775P and add additional clocks required for QCS8300. Acked-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,qcs8300-gpucc.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,qcs8300-gpucc.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/qcom,qcs8300-gpucc.h b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h new file mode 100644 index 000000000000..afa187467b4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H + +#include "qcom,sa8775p-gpucc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* GPU_CC clocks */ +#define GPU_CC_CX_ACCU_SHIFT_CLK 23 +#define GPU_CC_GX_ACCU_SHIFT_CLK 24 + +#endif -- cgit v1.2.3 From 25abbf6b8b9cbfa8e42c3ab44c642818b3adc7a2 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 9 Jan 2025 14:27:46 +0530 Subject: dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300 The QCS8300 camera clock controller is a derivative of SA8775P, but has an additional clock and minor differences. Hence, reuse the SA8775P camera bindings and add additional clock required for QCS8300. Reviewed-by: Vladimir Zapolskiy Acked-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,qcs8300-camcc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,qcs8300-camcc.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/qcom,qcs8300-camcc.h b/include/dt-bindings/clock/qcom,qcs8300-camcc.h new file mode 100644 index 000000000000..fc535c847859 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-camcc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H +#define _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H + +#include "qcom,sa8775p-camcc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* CAM_CC clocks */ +#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK 86 + +#endif -- cgit v1.2.3 From c240648b78f9cbb76052959c099ea94ab6cba893 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 13 Feb 2025 11:22:47 -0600 Subject: dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset Add the required clock and reset bindings for the LCD TCON. Signed-off-by: Chris Morgan Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250213172248.158447-2-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun50i-h616-ccu.h | 4 ++++ include/dt-bindings/reset/sun50i-h616-ccu.h | 2 ++ 2 files changed, 6 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index ebb146ab7f8c..6889405f9fec 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -113,5 +113,9 @@ #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 #define CLK_BUS_GPADC 129 +#define CLK_TCON_LCD0 130 +#define CLK_BUS_TCON_LCD0 131 +#define CLK_TCON_LCD1 132 +#define CLK_BUS_TCON_LCD1 133 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index ed177c04afdd..81b1eba2a7f7 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -67,5 +67,7 @@ #define RST_BUS_HDCP 58 #define RST_BUS_KEYADC 59 #define RST_BUS_GPADC 60 +#define RST_BUS_TCON_LCD0 61 +#define RST_BUS_TCON_LCD1 62 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ -- cgit v1.2.3 From 52dbf84857f051df38f6de3f0c7b7f4506e7ad25 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:26:18 +0000 Subject: dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for the main and the PRCM R-CCU. The source clock list differs in some annoying details, and folding this into the existing Allwinner CCU clock binding document gets quite unwieldy, so create a new document for these CCUs. Add the new compatible string, along with the required input clock lists. This conditionally describes the input clock lists, to make adding support for the other two CCUs easier. Also add the DT binding headers, listing all the clocks with their ID numbers. Signed-off-by: Andre Przywara Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun55i-a523-ccu.h | 189 ++++++++++++++++++++++++++ include/dt-bindings/clock/sun55i-a523-r-ccu.h | 37 +++++ include/dt-bindings/reset/sun55i-a523-ccu.h | 88 ++++++++++++ include/dt-bindings/reset/sun55i-a523-r-ccu.h | 25 ++++ 4 files changed, 339 insertions(+) create mode 100644 include/dt-bindings/clock/sun55i-a523-ccu.h create mode 100644 include/dt-bindings/clock/sun55i-a523-r-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-r-ccu.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h new file mode 100644 index 000000000000..c8259ac5ada7 --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ + +#define CLK_PLL_DDR0 0 +#define CLK_PLL_PERIPH0_4X 1 +#define CLK_PLL_PERIPH0_2X 2 +#define CLK_PLL_PERIPH0_800M 3 +#define CLK_PLL_PERIPH0_480M 4 +#define CLK_PLL_PERIPH0_600M 5 +#define CLK_PLL_PERIPH0_400M 6 +#define CLK_PLL_PERIPH0_300M 7 +#define CLK_PLL_PERIPH0_200M 8 +#define CLK_PLL_PERIPH0_160M 9 +#define CLK_PLL_PERIPH0_150M 10 +#define CLK_PLL_PERIPH1_4X 11 +#define CLK_PLL_PERIPH1_2X 12 +#define CLK_PLL_PERIPH1_800M 13 +#define CLK_PLL_PERIPH1_480M 14 +#define CLK_PLL_PERIPH1_600M 15 +#define CLK_PLL_PERIPH1_400M 16 +#define CLK_PLL_PERIPH1_300M 17 +#define CLK_PLL_PERIPH1_200M 18 +#define CLK_PLL_PERIPH1_160M 19 +#define CLK_PLL_PERIPH1_150M 20 +#define CLK_PLL_GPU 21 +#define CLK_PLL_VIDEO0_8X 22 +#define CLK_PLL_VIDEO0_4X 23 +#define CLK_PLL_VIDEO0_3X 24 +#define CLK_PLL_VIDEO1_8X 25 +#define CLK_PLL_VIDEO1_4X 26 +#define CLK_PLL_VIDEO1_3X 27 +#define CLK_PLL_VIDEO2_8X 28 +#define CLK_PLL_VIDEO2_4X 29 +#define CLK_PLL_VIDEO2_3X 30 +#define CLK_PLL_VIDEO3_8X 31 +#define CLK_PLL_VIDEO3_4X 32 +#define CLK_PLL_VIDEO3_3X 33 +#define CLK_PLL_VE 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO0_2X 36 +#define CLK_PLL_AUDIO0 37 +#define CLK_PLL_NPU_4X 38 +#define CLK_PLL_NPU_2X 39 +#define CLK_PLL_NPU 40 +#define CLK_AHB 41 +#define CLK_APB0 42 +#define CLK_APB1 43 +#define CLK_MBUS 44 +#define CLK_DE 45 +#define CLK_BUS_DE 46 +#define CLK_DI 47 +#define CLK_BUS_DI 48 +#define CLK_G2D 49 +#define CLK_BUS_G2D 50 +#define CLK_GPU 51 +#define CLK_BUS_GPU 52 +#define CLK_CE 53 +#define CLK_BUS_CE 54 +#define CLK_BUS_CE_SYS 55 +#define CLK_VE 56 +#define CLK_BUS_VE 57 +#define CLK_BUS_DMA 58 +#define CLK_BUS_MSGBOX 59 +#define CLK_BUS_SPINLOCK 60 +#define CLK_HSTIMER0 61 +#define CLK_HSTIMER1 62 +#define CLK_HSTIMER2 63 +#define CLK_HSTIMER3 64 +#define CLK_HSTIMER4 65 +#define CLK_HSTIMER5 66 +#define CLK_BUS_HSTIMER 67 +#define CLK_BUS_DBG 68 +#define CLK_BUS_PWM0 69 +#define CLK_BUS_PWM1 70 +#define CLK_IOMMU 71 +#define CLK_BUS_IOMMU 72 +#define CLK_DRAM 73 +#define CLK_MBUS_DMA 74 +#define CLK_MBUS_VE 75 +#define CLK_MBUS_CE 76 +#define CLK_MBUS_CSI 77 +#define CLK_MBUS_ISP 78 +#define CLK_MBUS_EMAC1 79 +#define CLK_BUS_DRAM 80 +#define CLK_NAND0 81 +#define CLK_NAND1 82 +#define CLK_BUS_NAND 83 +#define CLK_MMC0 84 +#define CLK_MMC1 85 +#define CLK_MMC2 86 +#define CLK_BUS_SYSDAP 87 +#define CLK_BUS_MMC0 88 +#define CLK_BUS_MMC1 89 +#define CLK_BUS_MMC2 90 +#define CLK_BUS_UART0 91 +#define CLK_BUS_UART1 92 +#define CLK_BUS_UART2 93 +#define CLK_BUS_UART3 94 +#define CLK_BUS_UART4 95 +#define CLK_BUS_UART5 96 +#define CLK_BUS_UART6 97 +#define CLK_BUS_UART7 98 +#define CLK_BUS_I2C0 99 +#define CLK_BUS_I2C1 100 +#define CLK_BUS_I2C2 101 +#define CLK_BUS_I2C3 102 +#define CLK_BUS_I2C4 103 +#define CLK_BUS_I2C5 104 +#define CLK_BUS_CAN 105 +#define CLK_SPI0 106 +#define CLK_SPI1 107 +#define CLK_SPI2 108 +#define CLK_SPIFC 109 +#define CLK_BUS_SPI0 110 +#define CLK_BUS_SPI1 111 +#define CLK_BUS_SPI2 112 +#define CLK_BUS_SPIFC 113 +#define CLK_EMAC0_25M 114 +#define CLK_EMAC1_25M 115 +#define CLK_BUS_EMAC0 116 +#define CLK_BUS_EMAC1 117 +#define CLK_IR_RX 118 +#define CLK_BUS_IR_RX 119 +#define CLK_IR_TX 120 +#define CLK_BUS_IR_TX 121 +#define CLK_GPADC0 122 +#define CLK_GPADC1 123 +#define CLK_BUS_GPADC0 124 +#define CLK_BUS_GPADC1 125 +#define CLK_BUS_THS 126 +#define CLK_USB_OHCI0 127 +#define CLK_USB_OHCI1 128 +#define CLK_BUS_OHCI0 129 +#define CLK_BUS_OHCI1 130 +#define CLK_BUS_EHCI0 131 +#define CLK_BUS_EHCI1 132 +#define CLK_BUS_OTG 133 +#define CLK_BUS_LRADC 134 +#define CLK_PCIE_AUX 135 +#define CLK_BUS_DISPLAY0_TOP 136 +#define CLK_BUS_DISPLAY1_TOP 137 +#define CLK_HDMI_24M 138 +#define CLK_HDMI_CEC_32K 139 +#define CLK_HDMI_CEC 140 +#define CLK_BUS_HDMI 141 +#define CLK_MIPI_DSI0 142 +#define CLK_MIPI_DSI1 143 +#define CLK_BUS_MIPI_DSI0 144 +#define CLK_BUS_MIPI_DSI1 145 +#define CLK_TCON_LCD0 146 +#define CLK_TCON_LCD1 147 +#define CLK_TCON_LCD2 148 +#define CLK_COMBOPHY_DSI0 149 +#define CLK_COMBOPHY_DSI1 150 +#define CLK_BUS_TCON_LCD0 151 +#define CLK_BUS_TCON_LCD1 152 +#define CLK_BUS_TCON_LCD2 153 +#define CLK_TCON_TV0 154 +#define CLK_TCON_TV1 155 +#define CLK_BUS_TCON_TV0 156 +#define CLK_BUS_TCON_TV1 157 +#define CLK_EDP 158 +#define CLK_BUS_EDP 159 +#define CLK_LEDC 160 +#define CLK_BUS_LEDC 161 +#define CLK_CSI_TOP 162 +#define CLK_CSI_MCLK0 163 +#define CLK_CSI_MCLK1 164 +#define CLK_CSI_MCLK2 165 +#define CLK_CSI_MCLK3 166 +#define CLK_BUS_CSI 167 +#define CLK_ISP 168 +#define CLK_DSP 169 +#define CLK_FANOUT_24M 170 +#define CLK_FANOUT_12M 171 +#define CLK_FANOUT_16M 172 +#define CLK_FANOUT_25M 173 +#define CLK_FANOUT_27M 174 +#define CLK_FANOUT_PCLK 175 +#define CLK_FANOUT0 176 +#define CLK_FANOUT1 177 +#define CLK_FANOUT2 178 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-r-ccu.h b/include/dt-bindings/clock/sun55i-a523-r-ccu.h new file mode 100644 index 000000000000..365647499b9a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-r-ccu.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_BUS_R_TIMER 6 +#define CLK_BUS_R_TWD 7 +#define CLK_R_PWMCTRL 8 +#define CLK_BUS_R_PWMCTRL 9 +#define CLK_R_SPI 10 +#define CLK_BUS_R_SPI 11 +#define CLK_BUS_R_SPINLOCK 12 +#define CLK_BUS_R_MSGBOX 13 +#define CLK_BUS_R_UART0 14 +#define CLK_BUS_R_UART1 15 +#define CLK_BUS_R_I2C0 16 +#define CLK_BUS_R_I2C1 17 +#define CLK_BUS_R_I2C2 18 +#define CLK_BUS_R_PPU0 19 +#define CLK_BUS_R_PPU1 20 +#define CLK_BUS_R_CPU_BIST 21 +#define CLK_R_IR_RX 22 +#define CLK_BUS_R_IR_RX 23 +#define CLK_BUS_R_DMA 24 +#define CLK_BUS_R_RTC 25 +#define CLK_BUS_R_CPUCFG 26 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-ccu.h b/include/dt-bindings/reset/sun55i-a523-ccu.h new file mode 100644 index 000000000000..70df503f34fe --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-ccu.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_NSI 1 +#define RST_BUS_DE 2 +#define RST_BUS_DI 3 +#define RST_BUS_G2D 4 +#define RST_BUS_SYS 5 +#define RST_BUS_GPU 6 +#define RST_BUS_CE 7 +#define RST_BUS_SYS_CE 8 +#define RST_BUS_VE 9 +#define RST_BUS_DMA 10 +#define RST_BUS_MSGBOX 11 +#define RST_BUS_SPINLOCK 12 +#define RST_BUS_CPUXTIMER 13 +#define RST_BUS_DBG 14 +#define RST_BUS_PWM0 15 +#define RST_BUS_PWM1 16 +#define RST_BUS_DRAM 17 +#define RST_BUS_NAND 18 +#define RST_BUS_MMC0 19 +#define RST_BUS_MMC1 20 +#define RST_BUS_MMC2 21 +#define RST_BUS_SYSDAP 22 +#define RST_BUS_UART0 23 +#define RST_BUS_UART1 24 +#define RST_BUS_UART2 25 +#define RST_BUS_UART3 26 +#define RST_BUS_UART4 27 +#define RST_BUS_UART5 28 +#define RST_BUS_UART6 29 +#define RST_BUS_UART7 30 +#define RST_BUS_I2C0 31 +#define RST_BUS_I2C1 32 +#define RST_BUS_I2C2 33 +#define RST_BUS_I2C3 34 +#define RST_BUS_I2C4 35 +#define RST_BUS_I2C5 36 +#define RST_BUS_CAN 37 +#define RST_BUS_SPI0 38 +#define RST_BUS_SPI1 39 +#define RST_BUS_SPI2 40 +#define RST_BUS_SPIFC 41 +#define RST_BUS_EMAC0 42 +#define RST_BUS_EMAC1 43 +#define RST_BUS_IR_RX 44 +#define RST_BUS_IR_TX 45 +#define RST_BUS_GPADC0 46 +#define RST_BUS_GPADC1 47 +#define RST_BUS_THS 48 +#define RST_USB_PHY0 49 +#define RST_USB_PHY1 50 +#define RST_BUS_OHCI0 51 +#define RST_BUS_OHCI1 52 +#define RST_BUS_EHCI0 53 +#define RST_BUS_EHCI1 54 +#define RST_BUS_OTG 55 +#define RST_BUS_3 56 +#define RST_BUS_LRADC 57 +#define RST_BUS_PCIE_USB3 58 +#define RST_BUS_DISPLAY0_TOP 59 +#define RST_BUS_DISPLAY1_TOP 60 +#define RST_BUS_HDMI_MAIN 61 +#define RST_BUS_HDMI_SUB 62 +#define RST_BUS_MIPI_DSI0 63 +#define RST_BUS_MIPI_DSI1 64 +#define RST_BUS_TCON_LCD0 65 +#define RST_BUS_TCON_LCD1 66 +#define RST_BUS_TCON_LCD2 67 +#define RST_BUS_TCON_TV0 68 +#define RST_BUS_TCON_TV1 69 +#define RST_BUS_LVDS0 70 +#define RST_BUS_LVDS1 71 +#define RST_BUS_EDP 72 +#define RST_BUS_VIDEO_OUT0 73 +#define RST_BUS_VIDEO_OUT1 74 +#define RST_BUS_LEDC 75 +#define RST_BUS_CSI 76 +#define RST_BUS_ISP 77 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h new file mode 100644 index 000000000000..dd6fbb372e19 --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-r-ccu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PWMCTRL 2 +#define RST_BUS_R_SPI 3 +#define RST_BUS_R_SPINLOCK 4 +#define RST_BUS_R_MSGBOX 5 +#define RST_BUS_R_UART0 6 +#define RST_BUS_R_UART1 7 +#define RST_BUS_R_I2C0 8 +#define RST_BUS_R_I2C1 9 +#define RST_BUS_R_I2C2 10 +#define RST_BUS_R_PPU1 11 +#define RST_BUS_R_IR_RX 12 +#define RST_BUS_R_RTC 13 +#define RST_BUS_R_CPUCFG 14 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */ -- cgit v1.2.3 From 07986c5b36c479a2a42067331e0625157dc41afd Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 13 Mar 2025 16:33:54 +0530 Subject: dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX Add the definition for GPLL0_OUT_AUX clock. Acked-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250313110359.242491-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index f238aa4794a8..0e7c319897f3 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -202,4 +202,5 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GPLL0_OUT_AUX 214 #endif -- cgit v1.2.3 From 28300ecedce41dad239e0779d0b640349db33ec6 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 13 Mar 2025 16:33:56 +0530 Subject: dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions Add NSSCC clock and reset definitions for ipq9574. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 +++++++++++++++++++++++++ include/dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 ++++++++++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..21a16dc0e64c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H + +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_CLC_AXI_CLK 4 +#define NSS_CC_CLC_CLK_SRC 5 +#define NSS_CC_CRYPTO_CLK 6 +#define NSS_CC_CRYPTO_CLK_SRC 7 +#define NSS_CC_CRYPTO_PPE_CLK 8 +#define NSS_CC_HAQ_AHB_CLK 9 +#define NSS_CC_HAQ_AXI_CLK 10 +#define NSS_CC_HAQ_CLK_SRC 11 +#define NSS_CC_IMEM_AHB_CLK 12 +#define NSS_CC_IMEM_CLK_SRC 13 +#define NSS_CC_IMEM_QSB_CLK 14 +#define NSS_CC_INT_CFG_CLK_SRC 15 +#define NSS_CC_NSS_CSR_CLK 16 +#define NSS_CC_NSSNOC_CE_APB_CLK 17 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 +#define NSS_CC_NSSNOC_PPE_CLK 27 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 +#define NSS_CC_PORT1_MAC_CLK 33 +#define NSS_CC_PORT1_RX_CLK 34 +#define NSS_CC_PORT1_RX_CLK_SRC 35 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 +#define NSS_CC_PORT1_TX_CLK 37 +#define NSS_CC_PORT1_TX_CLK_SRC 38 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 +#define NSS_CC_PORT2_MAC_CLK 40 +#define NSS_CC_PORT2_RX_CLK 41 +#define NSS_CC_PORT2_RX_CLK_SRC 42 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 +#define NSS_CC_PORT2_TX_CLK 44 +#define NSS_CC_PORT2_TX_CLK_SRC 45 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 +#define NSS_CC_PORT3_MAC_CLK 47 +#define NSS_CC_PORT3_RX_CLK 48 +#define NSS_CC_PORT3_RX_CLK_SRC 49 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 +#define NSS_CC_PORT3_TX_CLK 51 +#define NSS_CC_PORT3_TX_CLK_SRC 52 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 +#define NSS_CC_PORT4_MAC_CLK 54 +#define NSS_CC_PORT4_RX_CLK 55 +#define NSS_CC_PORT4_RX_CLK_SRC 56 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 +#define NSS_CC_PORT4_TX_CLK 58 +#define NSS_CC_PORT4_TX_CLK_SRC 59 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 +#define NSS_CC_PORT5_MAC_CLK 61 +#define NSS_CC_PORT5_RX_CLK 62 +#define NSS_CC_PORT5_RX_CLK_SRC 63 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 +#define NSS_CC_PORT5_TX_CLK 65 +#define NSS_CC_PORT5_TX_CLK_SRC 66 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 +#define NSS_CC_PORT6_MAC_CLK 68 +#define NSS_CC_PORT6_RX_CLK 69 +#define NSS_CC_PORT6_RX_CLK_SRC 70 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 +#define NSS_CC_PORT6_TX_CLK 72 +#define NSS_CC_PORT6_TX_CLK_SRC 73 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 +#define NSS_CC_PPE_CLK_SRC 75 +#define NSS_CC_PPE_EDMA_CFG_CLK 76 +#define NSS_CC_PPE_EDMA_CLK 77 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79 +#define NSS_CC_PPE_SWITCH_CLK 80 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81 +#define NSS_CC_UBI0_CLK_SRC 82 +#define NSS_CC_UBI0_DIV_CLK_SRC 83 +#define NSS_CC_UBI1_CLK_SRC 84 +#define NSS_CC_UBI1_DIV_CLK_SRC 85 +#define NSS_CC_UBI2_CLK_SRC 86 +#define NSS_CC_UBI2_DIV_CLK_SRC 87 +#define NSS_CC_UBI32_AHB0_CLK 88 +#define NSS_CC_UBI32_AHB1_CLK 89 +#define NSS_CC_UBI32_AHB2_CLK 90 +#define NSS_CC_UBI32_AHB3_CLK 91 +#define NSS_CC_UBI32_AXI0_CLK 92 +#define NSS_CC_UBI32_AXI1_CLK 93 +#define NSS_CC_UBI32_AXI2_CLK 94 +#define NSS_CC_UBI32_AXI3_CLK 95 +#define NSS_CC_UBI32_CORE0_CLK 96 +#define NSS_CC_UBI32_CORE1_CLK 97 +#define NSS_CC_UBI32_CORE2_CLK 98 +#define NSS_CC_UBI32_CORE3_CLK 99 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103 +#define NSS_CC_UBI32_NC_AXI0_CLK 104 +#define NSS_CC_UBI32_NC_AXI1_CLK 105 +#define NSS_CC_UBI32_NC_AXI2_CLK 106 +#define NSS_CC_UBI32_NC_AXI3_CLK 107 +#define NSS_CC_UBI32_UTCM0_CLK 108 +#define NSS_CC_UBI32_UTCM1_CLK 109 +#define NSS_CC_UBI32_UTCM2_CLK 110 +#define NSS_CC_UBI32_UTCM3_CLK 111 +#define NSS_CC_UBI3_CLK_SRC 112 +#define NSS_CC_UBI3_DIV_CLK_SRC 113 +#define NSS_CC_UBI_AXI_CLK_SRC 114 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 +#define UBI32_PLL 140 +#define UBI32_PLL_MAIN 141 + +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..7f152e98b99c --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H + +#define EDMA_HW_RESET 0 +#define NSS_CC_CE_BCR 1 +#define NSS_CC_CLC_BCR 2 +#define NSS_CC_EIP197_BCR 3 +#define NSS_CC_HAQ_BCR 4 +#define NSS_CC_IMEM_BCR 5 +#define NSS_CC_MAC_BCR 6 +#define NSS_CC_PPE_BCR 7 +#define NSS_CC_UBI_BCR 8 +#define NSS_CC_UNIPHY_BCR 9 +#define UBI3_CLKRST_CLAMP_ENABLE 10 +#define UBI3_CORE_CLAMP_ENABLE 11 +#define UBI2_CLKRST_CLAMP_ENABLE 12 +#define UBI2_CORE_CLAMP_ENABLE 13 +#define UBI1_CLKRST_CLAMP_ENABLE 14 +#define UBI1_CORE_CLAMP_ENABLE 15 +#define UBI0_CLKRST_CLAMP_ENABLE 16 +#define UBI0_CORE_CLAMP_ENABLE 17 +#define NSSNOC_NSS_CSR_ARES 18 +#define NSS_CSR_ARES 19 +#define PPE_BTQ_ARES 20 +#define PPE_IPE_ARES 21 +#define PPE_ARES 22 +#define PPE_CFG_ARES 23 +#define PPE_EDMA_ARES 24 +#define PPE_EDMA_CFG_ARES 25 +#define CRY_PPE_ARES 26 +#define NSSNOC_PPE_ARES 27 +#define NSSNOC_PPE_CFG_ARES 28 +#define PORT1_MAC_ARES 29 +#define PORT2_MAC_ARES 30 +#define PORT3_MAC_ARES 31 +#define PORT4_MAC_ARES 32 +#define PORT5_MAC_ARES 33 +#define PORT6_MAC_ARES 34 +#define XGMAC0_PTP_REF_ARES 35 +#define XGMAC1_PTP_REF_ARES 36 +#define XGMAC2_PTP_REF_ARES 37 +#define XGMAC3_PTP_REF_ARES 38 +#define XGMAC4_PTP_REF_ARES 39 +#define XGMAC5_PTP_REF_ARES 40 +#define HAQ_AHB_ARES 41 +#define HAQ_AXI_ARES 42 +#define NSSNOC_HAQ_AHB_ARES 43 +#define NSSNOC_HAQ_AXI_ARES 44 +#define CE_APB_ARES 45 +#define CE_AXI_ARES 46 +#define NSSNOC_CE_APB_ARES 47 +#define NSSNOC_CE_AXI_ARES 48 +#define CRYPTO_ARES 49 +#define NSSNOC_CRYPTO_ARES 50 +#define NSSNOC_NC_AXI0_1_ARES 51 +#define UBI0_CORE_ARES 52 +#define UBI1_CORE_ARES 53 +#define UBI2_CORE_ARES 54 +#define UBI3_CORE_ARES 55 +#define NC_AXI0_ARES 56 +#define UTCM0_ARES 57 +#define NC_AXI1_ARES 58 +#define UTCM1_ARES 59 +#define NC_AXI2_ARES 60 +#define UTCM2_ARES 61 +#define NC_AXI3_ARES 62 +#define UTCM3_ARES 63 +#define NSSNOC_NC_AXI0_ARES 64 +#define AHB0_ARES 65 +#define INTR0_AHB_ARES 66 +#define AHB1_ARES 67 +#define INTR1_AHB_ARES 68 +#define AHB2_ARES 69 +#define INTR2_AHB_ARES 70 +#define AHB3_ARES 71 +#define INTR3_AHB_ARES 72 +#define NSSNOC_AHB0_ARES 73 +#define NSSNOC_INT0_AHB_ARES 74 +#define AXI0_ARES 75 +#define AXI1_ARES 76 +#define AXI2_ARES 77 +#define AXI3_ARES 78 +#define NSSNOC_AXI0_ARES 79 +#define IMEM_QSB_ARES 80 +#define NSSNOC_IMEM_QSB_ARES 81 +#define IMEM_AHB_ARES 82 +#define NSSNOC_IMEM_AHB_ARES 83 +#define UNIPHY_PORT1_RX_ARES 84 +#define UNIPHY_PORT1_TX_ARES 85 +#define UNIPHY_PORT2_RX_ARES 86 +#define UNIPHY_PORT2_TX_ARES 87 +#define UNIPHY_PORT3_RX_ARES 88 +#define UNIPHY_PORT3_TX_ARES 89 +#define UNIPHY_PORT4_RX_ARES 90 +#define UNIPHY_PORT4_TX_ARES 91 +#define UNIPHY_PORT5_RX_ARES 92 +#define UNIPHY_PORT5_TX_ARES 93 +#define UNIPHY_PORT6_RX_ARES 94 +#define UNIPHY_PORT6_TX_ARES 95 +#define PORT1_RX_ARES 96 +#define PORT1_TX_ARES 97 +#define PORT2_RX_ARES 98 +#define PORT2_TX_ARES 99 +#define PORT3_RX_ARES 100 +#define PORT3_TX_ARES 101 +#define PORT4_RX_ARES 102 +#define PORT4_TX_ARES 103 +#define PORT5_RX_ARES 104 +#define PORT5_TX_ARES 105 +#define PORT6_RX_ARES 106 +#define PORT6_TX_ARES 107 +#define PPE_FULL_RESET 108 +#define UNIPHY0_SOFT_RESET 109 +#define UNIPHY1_SOFT_RESET 110 +#define UNIPHY2_SOFT_RESET 111 +#define UNIPHY_PORT1_ARES 112 +#define UNIPHY_PORT2_ARES 113 +#define UNIPHY_PORT3_ARES 114 +#define UNIPHY_PORT4_ARES 115 +#define UNIPHY_PORT5_ARES 116 +#define UNIPHY_PORT6_ARES 117 +#define NSSPORT1_RESET 118 +#define NSSPORT2_RESET 119 +#define NSSPORT3_RESET 120 +#define NSSPORT4_RESET 121 +#define NSSPORT5_RESET 122 +#define NSSPORT6_RESET 123 + +#endif -- cgit v1.2.3