From d539efa37f1f789339699c941e72e320d12d5f28 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 3 Oct 2014 16:57:11 +0300 Subject: ARM: OMAP3: clock: add new rate changing logic support for noncore DPLLs Currently, DPLL code hides the re-parenting within its internals, which is wrong. This needs to be exposed to the common clock code via determine_rate and set_rate_and_parent APIs. This patch adds support for these, which will be taken into use in the following patches. Signed-off-by: Tero Kristo Signed-off-by: Paul Walmsley --- include/linux/clk/ti.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/linux/clk') diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index f75acbf70e96..6f9fb77ffdd5 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -254,8 +254,17 @@ extern const struct clk_ops ti_clk_mux_ops; void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); +int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 index); +long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_clk); unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, unsigned long parent_rate); long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, -- cgit v1.2.3 From 83501ff0a5032dfbd63ab1ca9d9d25b97ec49fb9 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 3 Oct 2014 16:57:12 +0300 Subject: ARM: OMAP4: clock: add support for determine_rate for omap4 regm4xen DPLL Similarly to OMAP3 noncore DPLL, the implementation of this DPLL clock type is wrong. This patch adds basic functionality for determine_rate for this clock type which will be taken into use in the patches following later. Signed-off-by: Tero Kristo Signed-off-by: Paul Walmsley --- include/linux/clk/ti.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/clk') diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 6f9fb77ffdd5..abc702a73aca 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -270,6 +270,10 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); +long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_clk); u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, -- cgit v1.2.3 From e3ab6013ab06d3a861ed00c1f8d32aa4e6b66ddd Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 3 Oct 2014 16:57:13 +0300 Subject: ARM: OMAP3: clock: add support for dpll4_set_rate_and_parent Expand the support of omap4 per-dpll to provide set_rate_and_parent. This is required for proper behavior of clk_change_rate with determine_rate support. Signed-off-by: Tero Kristo Signed-off-by: Paul Walmsley --- include/linux/clk/ti.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/clk') diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index abc702a73aca..74e5341463c9 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -291,6 +291,8 @@ int omap2_clk_disable_autoidle_all(void); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); +int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate, u8 index); int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); -- cgit v1.2.3