From 57fe7251f5bfc4332f24479376de48a1e8ca6211 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 31 May 2011 12:02:49 +0300 Subject: MFD: twl4030-codec -> twl4030-audio: Rename the driver Rename the driver, and header file from twl4030-codec to twl4030-audio. To avoid breakage change depending drivers at the same time. Signed-off-by: Peter Ujfalusi CC: Misael Lopez Cruz Acked-by: Samuel Ortiz --- include/linux/mfd/twl4030-audio.h | 272 ++++++++++++++++++++++++++++++++++++++ include/linux/mfd/twl4030-codec.h | 272 -------------------------------------- 2 files changed, 272 insertions(+), 272 deletions(-) create mode 100644 include/linux/mfd/twl4030-audio.h delete mode 100644 include/linux/mfd/twl4030-codec.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl4030-audio.h b/include/linux/mfd/twl4030-audio.h new file mode 100644 index 000000000000..3d22b72df076 --- /dev/null +++ b/include/linux/mfd/twl4030-audio.h @@ -0,0 +1,272 @@ +/* + * MFD driver for twl4030 audio submodule + * + * Author: Peter Ujfalusi + * + * Copyright: (C) 2009 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __TWL4030_CODEC_H__ +#define __TWL4030_CODEC_H__ + +/* Codec registers */ +#define TWL4030_REG_CODEC_MODE 0x01 +#define TWL4030_REG_OPTION 0x02 +#define TWL4030_REG_UNKNOWN 0x03 +#define TWL4030_REG_MICBIAS_CTL 0x04 +#define TWL4030_REG_ANAMICL 0x05 +#define TWL4030_REG_ANAMICR 0x06 +#define TWL4030_REG_AVADC_CTL 0x07 +#define TWL4030_REG_ADCMICSEL 0x08 +#define TWL4030_REG_DIGMIXING 0x09 +#define TWL4030_REG_ATXL1PGA 0x0A +#define TWL4030_REG_ATXR1PGA 0x0B +#define TWL4030_REG_AVTXL2PGA 0x0C +#define TWL4030_REG_AVTXR2PGA 0x0D +#define TWL4030_REG_AUDIO_IF 0x0E +#define TWL4030_REG_VOICE_IF 0x0F +#define TWL4030_REG_ARXR1PGA 0x10 +#define TWL4030_REG_ARXL1PGA 0x11 +#define TWL4030_REG_ARXR2PGA 0x12 +#define TWL4030_REG_ARXL2PGA 0x13 +#define TWL4030_REG_VRXPGA 0x14 +#define TWL4030_REG_VSTPGA 0x15 +#define TWL4030_REG_VRX2ARXPGA 0x16 +#define TWL4030_REG_AVDAC_CTL 0x17 +#define TWL4030_REG_ARX2VTXPGA 0x18 +#define TWL4030_REG_ARXL1_APGA_CTL 0x19 +#define TWL4030_REG_ARXR1_APGA_CTL 0x1A +#define TWL4030_REG_ARXL2_APGA_CTL 0x1B +#define TWL4030_REG_ARXR2_APGA_CTL 0x1C +#define TWL4030_REG_ATX2ARXPGA 0x1D +#define TWL4030_REG_BT_IF 0x1E +#define TWL4030_REG_BTPGA 0x1F +#define TWL4030_REG_BTSTPGA 0x20 +#define TWL4030_REG_EAR_CTL 0x21 +#define TWL4030_REG_HS_SEL 0x22 +#define TWL4030_REG_HS_GAIN_SET 0x23 +#define TWL4030_REG_HS_POPN_SET 0x24 +#define TWL4030_REG_PREDL_CTL 0x25 +#define TWL4030_REG_PREDR_CTL 0x26 +#define TWL4030_REG_PRECKL_CTL 0x27 +#define TWL4030_REG_PRECKR_CTL 0x28 +#define TWL4030_REG_HFL_CTL 0x29 +#define TWL4030_REG_HFR_CTL 0x2A +#define TWL4030_REG_ALC_CTL 0x2B +#define TWL4030_REG_ALC_SET1 0x2C +#define TWL4030_REG_ALC_SET2 0x2D +#define TWL4030_REG_BOOST_CTL 0x2E +#define TWL4030_REG_SOFTVOL_CTL 0x2F +#define TWL4030_REG_DTMF_FREQSEL 0x30 +#define TWL4030_REG_DTMF_TONEXT1H 0x31 +#define TWL4030_REG_DTMF_TONEXT1L 0x32 +#define TWL4030_REG_DTMF_TONEXT2H 0x33 +#define TWL4030_REG_DTMF_TONEXT2L 0x34 +#define TWL4030_REG_DTMF_TONOFF 0x35 +#define TWL4030_REG_DTMF_WANONOFF 0x36 +#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 +#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 +#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 +#define TWL4030_REG_APLL_CTL 0x3A +#define TWL4030_REG_DTMF_CTL 0x3B +#define TWL4030_REG_DTMF_PGA_CTL2 0x3C +#define TWL4030_REG_DTMF_PGA_CTL1 0x3D +#define TWL4030_REG_MISC_SET_1 0x3E +#define TWL4030_REG_PCMBTMUX 0x3F +#define TWL4030_REG_RX_PATH_SEL 0x43 +#define TWL4030_REG_VDL_APGA_CTL 0x44 +#define TWL4030_REG_VIBRA_CTL 0x45 +#define TWL4030_REG_VIBRA_SET 0x46 +#define TWL4030_REG_VIBRA_PWM_SET 0x47 +#define TWL4030_REG_ANAMIC_GAIN 0x48 +#define TWL4030_REG_MISC_SET_2 0x49 + +/* Bitfield Definitions */ + +/* TWL4030_CODEC_MODE (0x01) Fields */ +#define TWL4030_APLL_RATE 0xF0 +#define TWL4030_APLL_RATE_8000 0x00 +#define TWL4030_APLL_RATE_11025 0x10 +#define TWL4030_APLL_RATE_12000 0x20 +#define TWL4030_APLL_RATE_16000 0x40 +#define TWL4030_APLL_RATE_22050 0x50 +#define TWL4030_APLL_RATE_24000 0x60 +#define TWL4030_APLL_RATE_32000 0x80 +#define TWL4030_APLL_RATE_44100 0x90 +#define TWL4030_APLL_RATE_48000 0xA0 +#define TWL4030_APLL_RATE_96000 0xE0 +#define TWL4030_SEL_16K 0x08 +#define TWL4030_CODECPDZ 0x02 +#define TWL4030_OPT_MODE 0x01 +#define TWL4030_OPTION_1 (1 << 0) +#define TWL4030_OPTION_2 (0 << 0) + +/* TWL4030_OPTION (0x02) Fields */ +#define TWL4030_ATXL1_EN (1 << 0) +#define TWL4030_ATXR1_EN (1 << 1) +#define TWL4030_ATXL2_VTXL_EN (1 << 2) +#define TWL4030_ATXR2_VTXR_EN (1 << 3) +#define TWL4030_ARXL1_VRX_EN (1 << 4) +#define TWL4030_ARXR1_EN (1 << 5) +#define TWL4030_ARXL2_EN (1 << 6) +#define TWL4030_ARXR2_EN (1 << 7) + +/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ +#define TWL4030_MICBIAS2_CTL 0x40 +#define TWL4030_MICBIAS1_CTL 0x20 +#define TWL4030_HSMICBIAS_EN 0x04 +#define TWL4030_MICBIAS2_EN 0x02 +#define TWL4030_MICBIAS1_EN 0x01 + +/* ANAMICL (0x05) Fields */ +#define TWL4030_CNCL_OFFSET_START 0x80 +#define TWL4030_OFFSET_CNCL_SEL 0x60 +#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 +#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 +#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 +#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 +#define TWL4030_MICAMPL_EN 0x10 +#define TWL4030_CKMIC_EN 0x08 +#define TWL4030_AUXL_EN 0x04 +#define TWL4030_HSMIC_EN 0x02 +#define TWL4030_MAINMIC_EN 0x01 + +/* ANAMICR (0x06) Fields */ +#define TWL4030_MICAMPR_EN 0x10 +#define TWL4030_AUXR_EN 0x04 +#define TWL4030_SUBMIC_EN 0x01 + +/* AVADC_CTL (0x07) Fields */ +#define TWL4030_ADCL_EN 0x08 +#define TWL4030_AVADC_CLK_PRIORITY 0x04 +#define TWL4030_ADCR_EN 0x02 + +/* TWL4030_REG_ADCMICSEL (0x08) Fields */ +#define TWL4030_DIGMIC1_EN 0x08 +#define TWL4030_TX2IN_SEL 0x04 +#define TWL4030_DIGMIC0_EN 0x02 +#define TWL4030_TX1IN_SEL 0x01 + +/* AUDIO_IF (0x0E) Fields */ +#define TWL4030_AIF_SLAVE_EN 0x80 +#define TWL4030_DATA_WIDTH 0x60 +#define TWL4030_DATA_WIDTH_16S_16W 0x00 +#define TWL4030_DATA_WIDTH_32S_16W 0x40 +#define TWL4030_DATA_WIDTH_32S_24W 0x60 +#define TWL4030_AIF_FORMAT 0x18 +#define TWL4030_AIF_FORMAT_CODEC 0x00 +#define TWL4030_AIF_FORMAT_LEFT 0x08 +#define TWL4030_AIF_FORMAT_RIGHT 0x10 +#define TWL4030_AIF_FORMAT_TDM 0x18 +#define TWL4030_AIF_TRI_EN 0x04 +#define TWL4030_CLK256FS_EN 0x02 +#define TWL4030_AIF_EN 0x01 + +/* VOICE_IF (0x0F) Fields */ +#define TWL4030_VIF_SLAVE_EN 0x80 +#define TWL4030_VIF_DIN_EN 0x40 +#define TWL4030_VIF_DOUT_EN 0x20 +#define TWL4030_VIF_SWAP 0x10 +#define TWL4030_VIF_FORMAT 0x08 +#define TWL4030_VIF_TRI_EN 0x04 +#define TWL4030_VIF_SUB_EN 0x02 +#define TWL4030_VIF_EN 0x01 + +/* EAR_CTL (0x21) */ +#define TWL4030_EAR_GAIN 0x30 + +/* HS_GAIN_SET (0x23) Fields */ +#define TWL4030_HSR_GAIN 0x0C +#define TWL4030_HSR_GAIN_PWR_DOWN 0x00 +#define TWL4030_HSR_GAIN_PLUS_6DB 0x04 +#define TWL4030_HSR_GAIN_0DB 0x08 +#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C +#define TWL4030_HSL_GAIN 0x03 +#define TWL4030_HSL_GAIN_PWR_DOWN 0x00 +#define TWL4030_HSL_GAIN_PLUS_6DB 0x01 +#define TWL4030_HSL_GAIN_0DB 0x02 +#define TWL4030_HSL_GAIN_MINUS_6DB 0x03 + +/* HS_POPN_SET (0x24) Fields */ +#define TWL4030_VMID_EN 0x40 +#define TWL4030_EXTMUTE 0x20 +#define TWL4030_RAMP_DELAY 0x1C +#define TWL4030_RAMP_DELAY_20MS 0x00 +#define TWL4030_RAMP_DELAY_40MS 0x04 +#define TWL4030_RAMP_DELAY_81MS 0x08 +#define TWL4030_RAMP_DELAY_161MS 0x0C +#define TWL4030_RAMP_DELAY_323MS 0x10 +#define TWL4030_RAMP_DELAY_645MS 0x14 +#define TWL4030_RAMP_DELAY_1291MS 0x18 +#define TWL4030_RAMP_DELAY_2581MS 0x1C +#define TWL4030_RAMP_EN 0x02 + +/* PREDL_CTL (0x25) */ +#define TWL4030_PREDL_GAIN 0x30 + +/* PREDR_CTL (0x26) */ +#define TWL4030_PREDR_GAIN 0x30 + +/* PRECKL_CTL (0x27) */ +#define TWL4030_PRECKL_GAIN 0x30 + +/* PRECKR_CTL (0x28) */ +#define TWL4030_PRECKR_GAIN 0x30 + +/* HFL_CTL (0x29, 0x2A) Fields */ +#define TWL4030_HF_CTL_HB_EN 0x04 +#define TWL4030_HF_CTL_LOOP_EN 0x08 +#define TWL4030_HF_CTL_RAMP_EN 0x10 +#define TWL4030_HF_CTL_REF_EN 0x20 + +/* APLL_CTL (0x3A) Fields */ +#define TWL4030_APLL_EN 0x10 +#define TWL4030_APLL_INFREQ 0x0F +#define TWL4030_APLL_INFREQ_19200KHZ 0x05 +#define TWL4030_APLL_INFREQ_26000KHZ 0x06 +#define TWL4030_APLL_INFREQ_38400KHZ 0x0F + +/* REG_MISC_SET_1 (0x3E) Fields */ +#define TWL4030_CLK64_EN 0x80 +#define TWL4030_SCRAMBLE_EN 0x40 +#define TWL4030_FMLOOP_EN 0x20 +#define TWL4030_SMOOTH_ANAVOL_EN 0x02 +#define TWL4030_DIGMIC_LR_SWAP_EN 0x01 + +/* VIBRA_CTL (0x45) */ +#define TWL4030_VIBRA_EN 0x01 +#define TWL4030_VIBRA_DIR 0x02 +#define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2) +#define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2) +#define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2) +#define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2) +#define TWL4030_VIBRA_SEL 0x10 +#define TWL4030_VIBRA_DIR_SEL 0x20 + +/* TWL4030 codec resource IDs */ +enum twl4030_audio_res { + TWL4030_AUDIO_RES_POWER = 0, + TWL4030_AUDIO_RES_APLL, + TWL4030_AUDIO_RES_MAX, +}; + +int twl4030_audio_disable_resource(enum twl4030_audio_res id); +int twl4030_audio_enable_resource(enum twl4030_audio_res id); +unsigned int twl4030_audio_get_mclk(void); + +#endif /* End of __TWL4030_CODEC_H__ */ diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h deleted file mode 100644 index 5cc16bbd1da1..000000000000 --- a/include/linux/mfd/twl4030-codec.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * MFD driver for twl4030 codec submodule - * - * Author: Peter Ujfalusi - * - * Copyright: (C) 2009 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef __TWL4030_CODEC_H__ -#define __TWL4030_CODEC_H__ - -/* Codec registers */ -#define TWL4030_REG_CODEC_MODE 0x01 -#define TWL4030_REG_OPTION 0x02 -#define TWL4030_REG_UNKNOWN 0x03 -#define TWL4030_REG_MICBIAS_CTL 0x04 -#define TWL4030_REG_ANAMICL 0x05 -#define TWL4030_REG_ANAMICR 0x06 -#define TWL4030_REG_AVADC_CTL 0x07 -#define TWL4030_REG_ADCMICSEL 0x08 -#define TWL4030_REG_DIGMIXING 0x09 -#define TWL4030_REG_ATXL1PGA 0x0A -#define TWL4030_REG_ATXR1PGA 0x0B -#define TWL4030_REG_AVTXL2PGA 0x0C -#define TWL4030_REG_AVTXR2PGA 0x0D -#define TWL4030_REG_AUDIO_IF 0x0E -#define TWL4030_REG_VOICE_IF 0x0F -#define TWL4030_REG_ARXR1PGA 0x10 -#define TWL4030_REG_ARXL1PGA 0x11 -#define TWL4030_REG_ARXR2PGA 0x12 -#define TWL4030_REG_ARXL2PGA 0x13 -#define TWL4030_REG_VRXPGA 0x14 -#define TWL4030_REG_VSTPGA 0x15 -#define TWL4030_REG_VRX2ARXPGA 0x16 -#define TWL4030_REG_AVDAC_CTL 0x17 -#define TWL4030_REG_ARX2VTXPGA 0x18 -#define TWL4030_REG_ARXL1_APGA_CTL 0x19 -#define TWL4030_REG_ARXR1_APGA_CTL 0x1A -#define TWL4030_REG_ARXL2_APGA_CTL 0x1B -#define TWL4030_REG_ARXR2_APGA_CTL 0x1C -#define TWL4030_REG_ATX2ARXPGA 0x1D -#define TWL4030_REG_BT_IF 0x1E -#define TWL4030_REG_BTPGA 0x1F -#define TWL4030_REG_BTSTPGA 0x20 -#define TWL4030_REG_EAR_CTL 0x21 -#define TWL4030_REG_HS_SEL 0x22 -#define TWL4030_REG_HS_GAIN_SET 0x23 -#define TWL4030_REG_HS_POPN_SET 0x24 -#define TWL4030_REG_PREDL_CTL 0x25 -#define TWL4030_REG_PREDR_CTL 0x26 -#define TWL4030_REG_PRECKL_CTL 0x27 -#define TWL4030_REG_PRECKR_CTL 0x28 -#define TWL4030_REG_HFL_CTL 0x29 -#define TWL4030_REG_HFR_CTL 0x2A -#define TWL4030_REG_ALC_CTL 0x2B -#define TWL4030_REG_ALC_SET1 0x2C -#define TWL4030_REG_ALC_SET2 0x2D -#define TWL4030_REG_BOOST_CTL 0x2E -#define TWL4030_REG_SOFTVOL_CTL 0x2F -#define TWL4030_REG_DTMF_FREQSEL 0x30 -#define TWL4030_REG_DTMF_TONEXT1H 0x31 -#define TWL4030_REG_DTMF_TONEXT1L 0x32 -#define TWL4030_REG_DTMF_TONEXT2H 0x33 -#define TWL4030_REG_DTMF_TONEXT2L 0x34 -#define TWL4030_REG_DTMF_TONOFF 0x35 -#define TWL4030_REG_DTMF_WANONOFF 0x36 -#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 -#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 -#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 -#define TWL4030_REG_APLL_CTL 0x3A -#define TWL4030_REG_DTMF_CTL 0x3B -#define TWL4030_REG_DTMF_PGA_CTL2 0x3C -#define TWL4030_REG_DTMF_PGA_CTL1 0x3D -#define TWL4030_REG_MISC_SET_1 0x3E -#define TWL4030_REG_PCMBTMUX 0x3F -#define TWL4030_REG_RX_PATH_SEL 0x43 -#define TWL4030_REG_VDL_APGA_CTL 0x44 -#define TWL4030_REG_VIBRA_CTL 0x45 -#define TWL4030_REG_VIBRA_SET 0x46 -#define TWL4030_REG_VIBRA_PWM_SET 0x47 -#define TWL4030_REG_ANAMIC_GAIN 0x48 -#define TWL4030_REG_MISC_SET_2 0x49 - -/* Bitfield Definitions */ - -/* TWL4030_CODEC_MODE (0x01) Fields */ -#define TWL4030_APLL_RATE 0xF0 -#define TWL4030_APLL_RATE_8000 0x00 -#define TWL4030_APLL_RATE_11025 0x10 -#define TWL4030_APLL_RATE_12000 0x20 -#define TWL4030_APLL_RATE_16000 0x40 -#define TWL4030_APLL_RATE_22050 0x50 -#define TWL4030_APLL_RATE_24000 0x60 -#define TWL4030_APLL_RATE_32000 0x80 -#define TWL4030_APLL_RATE_44100 0x90 -#define TWL4030_APLL_RATE_48000 0xA0 -#define TWL4030_APLL_RATE_96000 0xE0 -#define TWL4030_SEL_16K 0x08 -#define TWL4030_CODECPDZ 0x02 -#define TWL4030_OPT_MODE 0x01 -#define TWL4030_OPTION_1 (1 << 0) -#define TWL4030_OPTION_2 (0 << 0) - -/* TWL4030_OPTION (0x02) Fields */ -#define TWL4030_ATXL1_EN (1 << 0) -#define TWL4030_ATXR1_EN (1 << 1) -#define TWL4030_ATXL2_VTXL_EN (1 << 2) -#define TWL4030_ATXR2_VTXR_EN (1 << 3) -#define TWL4030_ARXL1_VRX_EN (1 << 4) -#define TWL4030_ARXR1_EN (1 << 5) -#define TWL4030_ARXL2_EN (1 << 6) -#define TWL4030_ARXR2_EN (1 << 7) - -/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ -#define TWL4030_MICBIAS2_CTL 0x40 -#define TWL4030_MICBIAS1_CTL 0x20 -#define TWL4030_HSMICBIAS_EN 0x04 -#define TWL4030_MICBIAS2_EN 0x02 -#define TWL4030_MICBIAS1_EN 0x01 - -/* ANAMICL (0x05) Fields */ -#define TWL4030_CNCL_OFFSET_START 0x80 -#define TWL4030_OFFSET_CNCL_SEL 0x60 -#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 -#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 -#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 -#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 -#define TWL4030_MICAMPL_EN 0x10 -#define TWL4030_CKMIC_EN 0x08 -#define TWL4030_AUXL_EN 0x04 -#define TWL4030_HSMIC_EN 0x02 -#define TWL4030_MAINMIC_EN 0x01 - -/* ANAMICR (0x06) Fields */ -#define TWL4030_MICAMPR_EN 0x10 -#define TWL4030_AUXR_EN 0x04 -#define TWL4030_SUBMIC_EN 0x01 - -/* AVADC_CTL (0x07) Fields */ -#define TWL4030_ADCL_EN 0x08 -#define TWL4030_AVADC_CLK_PRIORITY 0x04 -#define TWL4030_ADCR_EN 0x02 - -/* TWL4030_REG_ADCMICSEL (0x08) Fields */ -#define TWL4030_DIGMIC1_EN 0x08 -#define TWL4030_TX2IN_SEL 0x04 -#define TWL4030_DIGMIC0_EN 0x02 -#define TWL4030_TX1IN_SEL 0x01 - -/* AUDIO_IF (0x0E) Fields */ -#define TWL4030_AIF_SLAVE_EN 0x80 -#define TWL4030_DATA_WIDTH 0x60 -#define TWL4030_DATA_WIDTH_16S_16W 0x00 -#define TWL4030_DATA_WIDTH_32S_16W 0x40 -#define TWL4030_DATA_WIDTH_32S_24W 0x60 -#define TWL4030_AIF_FORMAT 0x18 -#define TWL4030_AIF_FORMAT_CODEC 0x00 -#define TWL4030_AIF_FORMAT_LEFT 0x08 -#define TWL4030_AIF_FORMAT_RIGHT 0x10 -#define TWL4030_AIF_FORMAT_TDM 0x18 -#define TWL4030_AIF_TRI_EN 0x04 -#define TWL4030_CLK256FS_EN 0x02 -#define TWL4030_AIF_EN 0x01 - -/* VOICE_IF (0x0F) Fields */ -#define TWL4030_VIF_SLAVE_EN 0x80 -#define TWL4030_VIF_DIN_EN 0x40 -#define TWL4030_VIF_DOUT_EN 0x20 -#define TWL4030_VIF_SWAP 0x10 -#define TWL4030_VIF_FORMAT 0x08 -#define TWL4030_VIF_TRI_EN 0x04 -#define TWL4030_VIF_SUB_EN 0x02 -#define TWL4030_VIF_EN 0x01 - -/* EAR_CTL (0x21) */ -#define TWL4030_EAR_GAIN 0x30 - -/* HS_GAIN_SET (0x23) Fields */ -#define TWL4030_HSR_GAIN 0x0C -#define TWL4030_HSR_GAIN_PWR_DOWN 0x00 -#define TWL4030_HSR_GAIN_PLUS_6DB 0x04 -#define TWL4030_HSR_GAIN_0DB 0x08 -#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C -#define TWL4030_HSL_GAIN 0x03 -#define TWL4030_HSL_GAIN_PWR_DOWN 0x00 -#define TWL4030_HSL_GAIN_PLUS_6DB 0x01 -#define TWL4030_HSL_GAIN_0DB 0x02 -#define TWL4030_HSL_GAIN_MINUS_6DB 0x03 - -/* HS_POPN_SET (0x24) Fields */ -#define TWL4030_VMID_EN 0x40 -#define TWL4030_EXTMUTE 0x20 -#define TWL4030_RAMP_DELAY 0x1C -#define TWL4030_RAMP_DELAY_20MS 0x00 -#define TWL4030_RAMP_DELAY_40MS 0x04 -#define TWL4030_RAMP_DELAY_81MS 0x08 -#define TWL4030_RAMP_DELAY_161MS 0x0C -#define TWL4030_RAMP_DELAY_323MS 0x10 -#define TWL4030_RAMP_DELAY_645MS 0x14 -#define TWL4030_RAMP_DELAY_1291MS 0x18 -#define TWL4030_RAMP_DELAY_2581MS 0x1C -#define TWL4030_RAMP_EN 0x02 - -/* PREDL_CTL (0x25) */ -#define TWL4030_PREDL_GAIN 0x30 - -/* PREDR_CTL (0x26) */ -#define TWL4030_PREDR_GAIN 0x30 - -/* PRECKL_CTL (0x27) */ -#define TWL4030_PRECKL_GAIN 0x30 - -/* PRECKR_CTL (0x28) */ -#define TWL4030_PRECKR_GAIN 0x30 - -/* HFL_CTL (0x29, 0x2A) Fields */ -#define TWL4030_HF_CTL_HB_EN 0x04 -#define TWL4030_HF_CTL_LOOP_EN 0x08 -#define TWL4030_HF_CTL_RAMP_EN 0x10 -#define TWL4030_HF_CTL_REF_EN 0x20 - -/* APLL_CTL (0x3A) Fields */ -#define TWL4030_APLL_EN 0x10 -#define TWL4030_APLL_INFREQ 0x0F -#define TWL4030_APLL_INFREQ_19200KHZ 0x05 -#define TWL4030_APLL_INFREQ_26000KHZ 0x06 -#define TWL4030_APLL_INFREQ_38400KHZ 0x0F - -/* REG_MISC_SET_1 (0x3E) Fields */ -#define TWL4030_CLK64_EN 0x80 -#define TWL4030_SCRAMBLE_EN 0x40 -#define TWL4030_FMLOOP_EN 0x20 -#define TWL4030_SMOOTH_ANAVOL_EN 0x02 -#define TWL4030_DIGMIC_LR_SWAP_EN 0x01 - -/* VIBRA_CTL (0x45) */ -#define TWL4030_VIBRA_EN 0x01 -#define TWL4030_VIBRA_DIR 0x02 -#define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2) -#define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2) -#define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2) -#define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2) -#define TWL4030_VIBRA_SEL 0x10 -#define TWL4030_VIBRA_DIR_SEL 0x20 - -/* TWL4030 codec resource IDs */ -enum twl4030_codec_res { - TWL4030_CODEC_RES_POWER = 0, - TWL4030_CODEC_RES_APLL, - TWL4030_CODEC_RES_MAX, -}; - -int twl4030_codec_disable_resource(enum twl4030_codec_res id); -int twl4030_codec_enable_resource(enum twl4030_codec_res id); -unsigned int twl4030_codec_get_mclk(void); - -#endif /* End of __TWL4030_CODEC_H__ */ -- cgit v1.2.3 From f19b2823f82499c60ec15d5fe8783193d77e3043 Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Wed, 27 Apr 2011 02:14:07 -0500 Subject: mfd: twl6040: Add initial support TWL6040 IC provides analog high-end audio codec functions for handset applications. It contains several audio analog inputs and outputs as well as vibrator support. It's connected to the host processor via PDM interface for audio data communication. The audio modules are controlled by internal registers that can be accessed by I2C and PDM interface. TWL6040 MFD will be registered as a child of TWL-CORE, and will have two children of its own: twl6040-codec and twl6040-vibra. This driver is based on TWL4030 and WM8350 MFD drivers. Signed-off-by: Misael Lopez Cruz Signed-off-by: Peter Ujfalusi Acked-by: Samuel Ortiz --- include/linux/mfd/twl6040.h | 255 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 255 insertions(+) create mode 100644 include/linux/mfd/twl6040.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h new file mode 100644 index 000000000000..c3c1de53dcfe --- /dev/null +++ b/include/linux/mfd/twl6040.h @@ -0,0 +1,255 @@ +/* + * MFD driver for twl6040 + * + * Authors: Jorge Eduardo Candelaria + * Misael Lopez Cruz + * + * Copyright: (C) 2011 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __TWL6040_CODEC_H__ +#define __TWL6040_CODEC_H__ + +#include +#include + +#define TWL6040_REG_ASICID 0x01 +#define TWL6040_REG_ASICREV 0x02 +#define TWL6040_REG_INTID 0x03 +#define TWL6040_REG_INTMR 0x04 +#define TWL6040_REG_NCPCTL 0x05 +#define TWL6040_REG_LDOCTL 0x06 +#define TWL6040_REG_HPPLLCTL 0x07 +#define TWL6040_REG_LPPLLCTL 0x08 +#define TWL6040_REG_LPPLLDIV 0x09 +#define TWL6040_REG_AMICBCTL 0x0A +#define TWL6040_REG_DMICBCTL 0x0B +#define TWL6040_REG_MICLCTL 0x0C +#define TWL6040_REG_MICRCTL 0x0D +#define TWL6040_REG_MICGAIN 0x0E +#define TWL6040_REG_LINEGAIN 0x0F +#define TWL6040_REG_HSLCTL 0x10 +#define TWL6040_REG_HSRCTL 0x11 +#define TWL6040_REG_HSGAIN 0x12 +#define TWL6040_REG_EARCTL 0x13 +#define TWL6040_REG_HFLCTL 0x14 +#define TWL6040_REG_HFLGAIN 0x15 +#define TWL6040_REG_HFRCTL 0x16 +#define TWL6040_REG_HFRGAIN 0x17 +#define TWL6040_REG_VIBCTLL 0x18 +#define TWL6040_REG_VIBDATL 0x19 +#define TWL6040_REG_VIBCTLR 0x1A +#define TWL6040_REG_VIBDATR 0x1B +#define TWL6040_REG_HKCTL1 0x1C +#define TWL6040_REG_HKCTL2 0x1D +#define TWL6040_REG_GPOCTL 0x1E +#define TWL6040_REG_ALB 0x1F +#define TWL6040_REG_DLB 0x20 +#define TWL6040_REG_TRIM1 0x28 +#define TWL6040_REG_TRIM2 0x29 +#define TWL6040_REG_TRIM3 0x2A +#define TWL6040_REG_HSOTRIM 0x2B +#define TWL6040_REG_HFOTRIM 0x2C +#define TWL6040_REG_ACCCTL 0x2D +#define TWL6040_REG_STATUS 0x2E + +#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1) + +#define TWL6040_VIOREGNUM 18 +#define TWL6040_VDDREGNUM 21 + +/* INTID (0x03) fields */ + +#define TWL6040_THINT 0x01 +#define TWL6040_PLUGINT 0x02 +#define TWL6040_UNPLUGINT 0x04 +#define TWL6040_HOOKINT 0x08 +#define TWL6040_HFINT 0x10 +#define TWL6040_VIBINT 0x20 +#define TWL6040_READYINT 0x40 + +/* INTMR (0x04) fields */ + +#define TWL6040_THMSK 0x01 +#define TWL6040_PLUGMSK 0x02 +#define TWL6040_HOOKMSK 0x08 +#define TWL6040_HFMSK 0x10 +#define TWL6040_VIBMSK 0x20 +#define TWL6040_READYMSK 0x40 +#define TWL6040_ALLINT_MSK 0x7B + +/* NCPCTL (0x05) fields */ + +#define TWL6040_NCPENA 0x01 +#define TWL6040_NCPOPEN 0x40 + +/* LDOCTL (0x06) fields */ + +#define TWL6040_LSLDOENA 0x01 +#define TWL6040_HSLDOENA 0x04 +#define TWL6040_REFENA 0x40 +#define TWL6040_OSCENA 0x80 + +/* HPPLLCTL (0x07) fields */ + +#define TWL6040_HPLLENA 0x01 +#define TWL6040_HPLLRST 0x02 +#define TWL6040_HPLLBP 0x04 +#define TWL6040_HPLLSQRENA 0x08 +#define TWL6040_MCLK_12000KHZ (0 << 5) +#define TWL6040_MCLK_19200KHZ (1 << 5) +#define TWL6040_MCLK_26000KHZ (2 << 5) +#define TWL6040_MCLK_38400KHZ (3 << 5) +#define TWL6040_MCLK_MSK 0x60 + +/* LPPLLCTL (0x08) fields */ + +#define TWL6040_LPLLENA 0x01 +#define TWL6040_LPLLRST 0x02 +#define TWL6040_LPLLSEL 0x04 +#define TWL6040_LPLLFIN 0x08 +#define TWL6040_HPLLSEL 0x10 + +/* HSLCTL (0x10) fields */ + +#define TWL6040_HSDACMODEL 0x02 +#define TWL6040_HSDRVMODEL 0x08 + +/* HSRCTL (0x11) fields */ + +#define TWL6040_HSDACMODER 0x02 +#define TWL6040_HSDRVMODER 0x08 + +/* VIBCTLL (0x18) fields */ + +#define TWL6040_VIBENAL 0x01 +#define TWL6040_VIBCTRLL 0x04 +#define TWL6040_VIBCTRLLP 0x08 +#define TWL6040_VIBCTRLLN 0x10 + +/* VIBDATL (0x19) fields */ + +#define TWL6040_VIBDAT_MAX 0x64 + +/* VIBCTLR (0x1A) fields */ + +#define TWL6040_VIBENAR 0x01 +#define TWL6040_VIBCTRLR 0x04 +#define TWL6040_VIBCTRLRP 0x08 +#define TWL6040_VIBCTRLRN 0x10 + +/* GPOCTL (0x1E) fields */ + +#define TWL6040_GPO1 0x01 +#define TWL6040_GPO2 0x02 +#define TWL6040_GPO3 0x03 + +/* ACCCTL (0x2D) fields */ + +#define TWL6040_I2CSEL 0x01 +#define TWL6040_RESETSPLIT 0x04 +#define TWL6040_INTCLRMODE 0x08 + +#define TWL6040_SYSCLK_SEL_LPPLL 1 +#define TWL6040_SYSCLK_SEL_HPPLL 2 + +/* STATUS (0x2E) fields */ + +#define TWL6040_PLUGCOMP 0x02 +#define TWL6040_VIBLOCDET 0x10 +#define TWL6040_VIBROCDET 0x20 +#define TWL6040_TSHUTDET 0x40 + +#define TWL6040_CELLS 2 + +#define TWL6040_REV_ES1_0 0x00 +#define TWL6040_REV_ES1_1 0x01 +#define TWL6040_REV_ES1_2 0x02 + +#define TWL6040_IRQ_TH 0 +#define TWL6040_IRQ_PLUG 1 +#define TWL6040_IRQ_HOOK 2 +#define TWL6040_IRQ_HF 3 +#define TWL6040_IRQ_VIB 4 +#define TWL6040_IRQ_READY 5 + +enum twl6040_pll_id { + TWL6040_NOPLL_ID, + TWL6040_LPPLL_ID, + TWL6040_HPPLL_ID, +}; + +struct twl6040 { + struct device *dev; + struct mutex mutex; + struct mutex io_mutex; + struct mutex irq_mutex; + struct mfd_cell cells[TWL6040_CELLS]; + struct completion ready; + + int audpwron; + int power_count; + int rev; + + enum twl6040_pll_id pll; + unsigned int sysclk; + + unsigned int irq; + unsigned int irq_base; + u8 irq_masks_cur; + u8 irq_masks_cache; +}; + +static inline int twl6040_request_irq(struct twl6040 *twl6040, int irq, + irq_handler_t handler, + unsigned long irqflags, + const char *name, + void *data) +{ + if (!twl6040->irq_base) + return -EINVAL; + + return request_threaded_irq(twl6040->irq_base + irq, NULL, handler, + irqflags, name, data); +} + +static inline void twl6040_free_irq(struct twl6040 *twl6040, int irq, + void *data) +{ + if (!twl6040->irq_base) + return; + + free_irq(twl6040->irq_base + irq, data); +} + +int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg); +int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, + u8 val); +int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, + u8 mask); +int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, + u8 mask); +int twl6040_power(struct twl6040 *twl6040, int on); +int twl6040_set_pll(struct twl6040 *twl6040, enum twl6040_pll_id id, + unsigned int freq_in, unsigned int freq_out); +enum twl6040_pll_id twl6040_get_pll(struct twl6040 *twl6040); +unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); +int twl6040_irq_init(struct twl6040 *twl6040); +void twl6040_irq_exit(struct twl6040 *twl6040); + +#endif /* End of __TWL6040_CODEC_H__ */ -- cgit v1.2.3 From 1b7c4725e2e926eaeb8657ac22992ec27fe03135 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 4 Jul 2011 20:16:23 +0300 Subject: MFD: twl6040: Remove wrapper for threaded irq request Remove the twl6040_request_irq/free_irq inline functions, and use direct calls instead in the core driver to register the threaded irq. Signed-off-by: Peter Ujfalusi Reviewed-by: Felipe Balbi Acked-by: Samuel Ortiz --- include/linux/mfd/twl6040.h | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index c3c1de53dcfe..df890a247c36 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -215,28 +215,6 @@ struct twl6040 { u8 irq_masks_cache; }; -static inline int twl6040_request_irq(struct twl6040 *twl6040, int irq, - irq_handler_t handler, - unsigned long irqflags, - const char *name, - void *data) -{ - if (!twl6040->irq_base) - return -EINVAL; - - return request_threaded_irq(twl6040->irq_base + irq, NULL, handler, - irqflags, name, data); -} - -static inline void twl6040_free_irq(struct twl6040 *twl6040, int irq, - void *data) -{ - if (!twl6040->irq_base) - return; - - free_irq(twl6040->irq_base + irq, data); -} - int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg); int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val); -- cgit v1.2.3 From cfb7a33bea259d2d72a64adcb3de28532170dc25 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 4 Jul 2011 10:28:28 +0300 Subject: MFD: twl6040: Remove enum for PLL tracking There is no need to have two different types for tracking the selected PLL. Use only the defines, when dealing with the PLLs. Signed-off-by: Peter Ujfalusi Acked-by: Samuel Ortiz --- include/linux/mfd/twl6040.h | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index df890a247c36..4c806f6d663e 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -165,9 +165,6 @@ #define TWL6040_RESETSPLIT 0x04 #define TWL6040_INTCLRMODE 0x08 -#define TWL6040_SYSCLK_SEL_LPPLL 1 -#define TWL6040_SYSCLK_SEL_HPPLL 2 - /* STATUS (0x2E) fields */ #define TWL6040_PLUGCOMP 0x02 @@ -188,11 +185,9 @@ #define TWL6040_IRQ_VIB 4 #define TWL6040_IRQ_READY 5 -enum twl6040_pll_id { - TWL6040_NOPLL_ID, - TWL6040_LPPLL_ID, - TWL6040_HPPLL_ID, -}; +/* PLL selection */ +#define TWL6040_SYSCLK_SEL_LPPLL 0 +#define TWL6040_SYSCLK_SEL_HPPLL 1 struct twl6040 { struct device *dev; @@ -206,7 +201,7 @@ struct twl6040 { int power_count; int rev; - enum twl6040_pll_id pll; + int pll; unsigned int sysclk; unsigned int irq; @@ -223,9 +218,9 @@ int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask); int twl6040_power(struct twl6040 *twl6040, int on); -int twl6040_set_pll(struct twl6040 *twl6040, enum twl6040_pll_id id, +int twl6040_set_pll(struct twl6040 *twl6040, int pll_id, unsigned int freq_in, unsigned int freq_out); -enum twl6040_pll_id twl6040_get_pll(struct twl6040 *twl6040); +int twl6040_get_pll(struct twl6040 *twl6040); unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); int twl6040_irq_init(struct twl6040 *twl6040); void twl6040_irq_exit(struct twl6040 *twl6040); -- cgit v1.2.3 From 149c077b4bd746eca2eeb241e55456eb4882b259 Mon Sep 17 00:00:00 2001 From: Donggeun Kim Date: Wed, 22 Jun 2011 19:40:06 +0900 Subject: power_supply: Add charger driver for MAX8997/8966 MAX8997/8966 chip is a multi-function device which includes PMIC, RTC, Fuel Gauge, MUIC, Haptic, Flash control, and Battery charging control. The driver for it is located at drivers/mfd. This patch supports battery charging control of MAX8997/8966 chip and provides power supply class information to userspace. Signed-off-by: Donggeun Kim Signed-off-by: MyungJoo Ham Signed-off-by: KyungMin Park Acked-by: Samuel Ortiz Signed-off-by: Anton Vorontsov --- include/linux/mfd/max8997.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h index 60931d089422..0bbd13dbe336 100644 --- a/include/linux/mfd/max8997.h +++ b/include/linux/mfd/max8997.h @@ -107,11 +107,16 @@ struct max8997_platform_data { unsigned int buck5_voltage[8]; bool buck5_gpiodvs; + /* ---- Charger control ---- */ + /* eoc stands for 'end of charge' */ + int eoc_mA; /* 50 ~ 200mA by 10mA step */ + /* charge Full Timeout */ + int timeout; /* 0 (no timeout), 5, 6, 7 hours */ + /* MUIC: Not implemented */ /* HAPTIC: Not implemented */ /* RTC: Not implemented */ /* Flash: Not implemented */ - /* Charger control: Not implemented */ }; #endif /* __LINUX_MFD_MAX8998_H */ -- cgit v1.2.3 From bb4ce9708785f40849f1a64931e6cc3b26171201 Mon Sep 17 00:00:00 2001 From: Donggeun Kim Date: Fri, 24 Jun 2011 19:04:18 +0900 Subject: power_supply: Add charger driver for MAX8998/LP3974 This patch supports power supply APIs for MAX8998/LP3974. Signed-off-by: Donggeun Kim Signed-off-by: MyungJoo Ham Signed-off-by: KyungMin Park Acked-by: Samuel Ortiz Signed-off-by: Anton Vorontsov --- include/linux/mfd/max8998.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h index 61daa167b576..f4f0dfa4698a 100644 --- a/include/linux/mfd/max8998.h +++ b/include/linux/mfd/max8998.h @@ -87,6 +87,15 @@ struct max8998_regulator_data { * @wakeup: Allow to wake up from suspend * @rtc_delay: LP3974 RTC chip bug that requires delay after a register * write before reading it. + * @eoc: End of Charge Level in percent: 10% ~ 45% by 5% step + * If it equals 0, leave it unchanged. + * Otherwise, it is a invalid value. + * @restart: Restart Level in mV: 100, 150, 200, and -1 for disable. + * If it equals 0, leave it unchanged. + * Otherwise, it is a invalid value. + * @timeout: Full Timeout in hours: 5, 6, 7, and -1 for disable. + * If it equals 0, leave it unchanged. + * Otherwise, leave it unchanged. */ struct max8998_platform_data { struct max8998_regulator_data *regulators; @@ -107,6 +116,9 @@ struct max8998_platform_data { int buck2_default_idx; bool wakeup; bool rtc_delay; + int eoc; + int restart; + int timeout; }; #endif /* __LINUX_MFD_MAX8998_H */ -- cgit v1.2.3 From 973ed3af1a570612771ed10dec6506c757767668 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 21 Jun 2011 08:00:10 +0900 Subject: mmc: sdhi: Add write16_hook Some controllers require waiting for the bus to become idle before writing to some registers. I have implemented this by adding a hook to sd_ctrl_write16() and implementing a hook for SDHI which waits for the bus to become idle. Cc: Guennadi Liakhovetski Cc: Magnus Damm Signed-off-by: Simon Horman Signed-off-by: Chris Ball --- include/linux/mfd/tmio.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 5a90266c3a5a..0dc98044d8b7 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -68,6 +68,11 @@ * controller and report the event to the driver. */ #define TMIO_MMC_HAS_COLD_CD (1 << 3) +/* + * Some controllers require waiting for the SD bus to become + * idle before writing to some registers. + */ +#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4) int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); @@ -80,6 +85,8 @@ struct tmio_mmc_dma { int alignment_shift; }; +struct tmio_mmc_host; + /* * data for the MMC controller */ @@ -94,6 +101,7 @@ struct tmio_mmc_data { void (*set_pwr)(struct platform_device *host, int state); void (*set_clk_div)(struct platform_device *host, int state); int (*get_cd)(struct platform_device *host); + int (*write16_hook)(struct tmio_mmc_host *host, int addr); }; static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata) -- cgit v1.2.3 From 497888cf69bf607ac1fe061a6437e0a670b0022f Mon Sep 17 00:00:00 2001 From: Phil Carmody Date: Thu, 14 Jul 2011 15:07:13 +0300 Subject: treewide: fix potentially dangerous trailing ';' in #defined values/expressions All these are instances of #define NAME value; or #define NAME(params_opt) value; These of course fail to build when used in contexts like if(foo $OP NAME) while(bar $OP NAME) and may silently generate the wrong code in contexts such as foo = NAME + 1; /* foo = value; + 1; */ bar = NAME - 1; /* bar = value; - 1; */ baz = NAME & quux; /* baz = value; & quux; */ Reported on comp.lang.c, Message-ID: Initial analysis of the dangers provided by Keith Thompson in that thread. There are many more instances of more complicated macros having unnecessary trailing semicolons, but this pile seems to be all of the cases of simple values suffering from the problem. (Thus things that are likely to be found in one of the contexts above, more complicated ones aren't.) Signed-off-by: Phil Carmody Signed-off-by: Jiri Kosina --- include/linux/mfd/tps65910.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 8bb85b930c07..73572c65d04f 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -269,7 +269,7 @@ #define LDO1_SEL_MASK 0xFC #define LDO3_SEL_MASK 0x7C #define LDO_MIN_VOLT 1000 -#define LDO_MAX_VOLT 3300; +#define LDO_MAX_VOLT 3300 /*Register VDIG1 (0x80) register.RegisterDescription */ -- cgit v1.2.3 From 9a9a54ad7aa2c7420c96c6fd33538f55d81775cb Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Mon, 25 Jul 2011 17:13:33 -0700 Subject: drivers/rtc: add support for Qualcomm PMIC8xxx RTC Add support for PMIC8xxx based RTC. PMIC8xxx is Qualcomm's power management IC that internally houses an RTC module. This driver communicates with the PMIC module over SSBI bus. [akpm@linux-foundation.org: cosmetic tweaks] Acked-by: Wan ZongShun Reviewed-by: Stephen Boyd Signed-off-by: Anirudh Ghayal Signed-off-by: Ashay Jaiswal Cc: Samuel Ortiz Cc: Wan ZongShun Cc: Alessandro Zummo Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/mfd/pm8xxx/rtc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/linux/mfd/pm8xxx/rtc.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/pm8xxx/rtc.h b/include/linux/mfd/pm8xxx/rtc.h new file mode 100644 index 000000000000..14f1983eaecc --- /dev/null +++ b/include/linux/mfd/pm8xxx/rtc.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RTC_PM8XXX_H__ +#define __RTC_PM8XXX_H__ + +#define PM8XXX_RTC_DEV_NAME "rtc-pm8xxx" +/** + * struct pm8xxx_rtc_pdata - RTC driver platform data + * @rtc_write_enable: variable stating RTC write capability + */ +struct pm8xxx_rtc_platform_data { + bool rtc_write_enable; +}; + +#endif /* __RTC_PM8XXX_H__ */ -- cgit v1.2.3 From ca7a71824ac957b1b9d3322656c05aad38d7275c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jun 2011 19:18:47 +0100 Subject: mfd: Fix bus lock interaction for WM831x IRQ set_type() operation The WM831x IRQ set_type() operation is doing a direct register write when called but since set_type() is called with the bus lock held this isn't legal and could cause deadlocks in the IRQ core. Fix this by posting the updates into an array and syncing in the bus_sync_unlock() callback. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 0d515ee1c247..ebead1c401aa 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -237,6 +237,7 @@ struct regulator_dev; #define WM831X_NUM_IRQ_REGS 5 +#define WM831X_NUM_GPIO_REGS 16 enum wm831x_parent { WM8310 = 0x8310, @@ -272,6 +273,9 @@ struct wm831x { int num_gpio; + /* Used by the interrupt controller code to post writes */ + int gpio_update[WM831X_NUM_GPIO_REGS]; + struct mutex auxadc_lock; struct completion auxadc_done; -- cgit v1.2.3 From 266a5e02fe2690637b2318c9fc5c3513937128f4 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jun 2011 19:18:49 +0100 Subject: mfd: Allow touchscreen to be disabled on wm831x devices Allow platform data to flag the touchscreen as disabled so that if the touch driver is built in we don't end up causing lots of work by spuriously detecting touchscreen activity on systems where it isn't in use. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/pdata.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h index ff42d700293f..0ba24599fe51 100644 --- a/include/linux/mfd/wm831x/pdata.h +++ b/include/linux/mfd/wm831x/pdata.h @@ -120,6 +120,9 @@ struct wm831x_pdata { /** Put the /IRQ line into CMOS mode */ bool irq_cmos; + /** Disable the touchscreen */ + bool disable_touch; + int irq_base; int gpio_base; int gpio_defaults[WM831X_GPIO_NUM]; -- cgit v1.2.3 From 5c05a8d1f0105ada3cb04be5b70686fc6b272619 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jun 2011 19:18:51 +0100 Subject: mfd: Support dynamic allocation of IRQ range for wm831x Use irq_allocate_desc() to get the IRQ range, which turns into a noop on non-sparse systems. Since all existing users are non-sparse there should be no compatibility issues. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index ebead1c401aa..9564cf315276 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -262,7 +262,7 @@ struct wm831x { int irq; /* Our chip IRQ */ struct mutex irq_lock; - unsigned int irq_base; + int irq_base; int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ -- cgit v1.2.3 From c1a82780b41e78f31636c49279ce940afe60a453 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jun 2011 19:18:52 +0100 Subject: mfd: Read wm831x AUXADC conversion results before acknowledging interrupt Ensure that there's no possibility of loosing an AUXADC interrupt by reading the conversion result in the IRQ handler when using interrupts. Otherwise it's possible that under very heavy load a new conversion could be initiated before the acknowledgement for a previous interrupt has happened. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 9564cf315276..592e4fd6ab3f 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -278,6 +278,7 @@ struct wm831x { struct mutex auxadc_lock; struct completion auxadc_done; + u16 auxadc_data; /* The WM831x has a security key blocking access to certain * registers. The mutex is taken by the accessors for locking -- cgit v1.2.3 From 78bb3688ea1830672b8095fb6388593f582cd591 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 7 Jun 2011 11:47:28 +0100 Subject: mfd: Support multiple active WM831x AUXADC conversions The WM831x AUXADC hardware can schedule multiple conversions at once, allowing higher performance when more than one source is in use as we can have the hardware start new conversions without having to wait for a register write. Take advantage of this in the interrupt driven case, maintaining a list of callers that are waiting for AUXADC conversions and completing them all simultaneously. The external interface of the AUXADC is not changed so there will be limited use of the feature immediately. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 592e4fd6ab3f..9fa14cdc1590 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -17,6 +17,7 @@ #include #include +#include /* * Register values. @@ -249,6 +250,12 @@ enum wm831x_parent { WM8326 = 0x8326, }; +struct wm831x; +enum wm831x_auxadc; + +typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x, + enum wm831x_auxadc input); + struct wm831x { struct mutex io_lock; @@ -277,8 +284,9 @@ struct wm831x { int gpio_update[WM831X_NUM_GPIO_REGS]; struct mutex auxadc_lock; - struct completion auxadc_done; - u16 auxadc_data; + struct list_head auxadc_pending; + u16 auxadc_active; + wm831x_auxadc_read_fn auxadc_read; /* The WM831x has a security key blocking access to certain * registers. The mutex is taken by the accessors for locking @@ -305,5 +313,6 @@ void wm831x_device_exit(struct wm831x *wm831x); int wm831x_device_suspend(struct wm831x *wm831x); int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); +void wm831x_auxadc_init(struct wm831x *wm831x); #endif -- cgit v1.2.3 From 36e52873c6393b569f2befcdd1847929211892b8 Mon Sep 17 00:00:00 2001 From: Margarita Olaya Date: Thu, 9 Jun 2011 14:50:00 -0500 Subject: mfd: tps65912: Add new mfd device The tps65912 chip is a power management IC. It contains the following components: - Regulators - GPIO controller The core driver is registered as a platform driver, it provides communication through I2C and SPI interfaces. Signed-off-by: Margarita Olaya Cabrera Acked-by: Samuel Ortiz Acked-by: Liam Girdwood Signed-off-by: Samuel Ortiz --- include/linux/mfd/tps65912.h | 321 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 321 insertions(+) create mode 100644 include/linux/mfd/tps65912.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h new file mode 100644 index 000000000000..48d3b53316a9 --- /dev/null +++ b/include/linux/mfd/tps65912.h @@ -0,0 +1,321 @@ +/* + * tps65912.h -- TI TPS6591x + * + * Copyright 2011 Texas Instruments Inc. + * + * Author: Margarita Olaya + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_TPS65912_H +#define __LINUX_MFD_TPS65912_H + +/* TPS regulator type list */ +#define REGULATOR_LDO 0 +#define REGULATOR_DCDC 1 + +/* + * List of registers for TPS65912 + */ + +#define TPS65912_DCDC1_CTRL 0x00 +#define TPS65912_DCDC2_CTRL 0x01 +#define TPS65912_DCDC3_CTRL 0x02 +#define TPS65912_DCDC4_CTRL 0x03 +#define TPS65912_DCDC1_OP 0x04 +#define TPS65912_DCDC1_AVS 0x05 +#define TPS65912_DCDC1_LIMIT 0x06 +#define TPS65912_DCDC2_OP 0x07 +#define TPS65912_DCDC2_AVS 0x08 +#define TPS65912_DCDC2_LIMIT 0x09 +#define TPS65912_DCDC3_OP 0x0A +#define TPS65912_DCDC3_AVS 0x0B +#define TPS65912_DCDC3_LIMIT 0x0C +#define TPS65912_DCDC4_OP 0x0D +#define TPS65912_DCDC4_AVS 0x0E +#define TPS65912_DCDC4_LIMIT 0x0F +#define TPS65912_LDO1_OP 0x10 +#define TPS65912_LDO1_AVS 0x11 +#define TPS65912_LDO1_LIMIT 0x12 +#define TPS65912_LDO2_OP 0x13 +#define TPS65912_LDO2_AVS 0x14 +#define TPS65912_LDO2_LIMIT 0x15 +#define TPS65912_LDO3_OP 0x16 +#define TPS65912_LDO3_AVS 0x17 +#define TPS65912_LDO3_LIMIT 0x18 +#define TPS65912_LDO4_OP 0x19 +#define TPS65912_LDO4_AVS 0x1A +#define TPS65912_LDO4_LIMIT 0x1B +#define TPS65912_LDO5 0x1C +#define TPS65912_LDO6 0x1D +#define TPS65912_LDO7 0x1E +#define TPS65912_LDO8 0x1F +#define TPS65912_LDO9 0x20 +#define TPS65912_LDO10 0x21 +#define TPS65912_THRM 0x22 +#define TPS65912_CLK32OUT 0x23 +#define TPS65912_DEVCTRL 0x24 +#define TPS65912_DEVCTRL2 0x25 +#define TPS65912_I2C_SPI_CFG 0x26 +#define TPS65912_KEEP_ON 0x27 +#define TPS65912_KEEP_ON2 0x28 +#define TPS65912_SET_OFF1 0x29 +#define TPS65912_SET_OFF2 0x2A +#define TPS65912_DEF_VOLT 0x2B +#define TPS65912_DEF_VOLT_MAPPING 0x2C +#define TPS65912_DISCHARGE 0x2D +#define TPS65912_DISCHARGE2 0x2E +#define TPS65912_EN1_SET1 0x2F +#define TPS65912_EN1_SET2 0x30 +#define TPS65912_EN2_SET1 0x31 +#define TPS65912_EN2_SET2 0x32 +#define TPS65912_EN3_SET1 0x33 +#define TPS65912_EN3_SET2 0x34 +#define TPS65912_EN4_SET1 0x35 +#define TPS65912_EN4_SET2 0x36 +#define TPS65912_PGOOD 0x37 +#define TPS65912_PGOOD2 0x38 +#define TPS65912_INT_STS 0x39 +#define TPS65912_INT_MSK 0x3A +#define TPS65912_INT_STS2 0x3B +#define TPS65912_INT_MSK2 0x3C +#define TPS65912_INT_STS3 0x3D +#define TPS65912_INT_MSK3 0x3E +#define TPS65912_INT_STS4 0x3F +#define TPS65912_INT_MSK4 0x40 +#define TPS65912_GPIO1 0x41 +#define TPS65912_GPIO2 0x42 +#define TPS65912_GPIO3 0x43 +#define TPS65912_GPIO4 0x44 +#define TPS65912_GPIO5 0x45 +#define TPS65912_VMON 0x46 +#define TPS65912_LEDA_CTRL1 0x47 +#define TPS65912_LEDA_CTRL2 0x48 +#define TPS65912_LEDA_CTRL3 0x49 +#define TPS65912_LEDA_CTRL4 0x4A +#define TPS65912_LEDA_CTRL5 0x4B +#define TPS65912_LEDA_CTRL6 0x4C +#define TPS65912_LEDA_CTRL7 0x4D +#define TPS65912_LEDA_CTRL8 0x4E +#define TPS65912_LEDB_CTRL1 0x4F +#define TPS65912_LEDB_CTRL2 0x50 +#define TPS65912_LEDB_CTRL3 0x51 +#define TPS65912_LEDB_CTRL4 0x52 +#define TPS65912_LEDB_CTRL5 0x53 +#define TPS65912_LEDB_CTRL6 0x54 +#define TPS65912_LEDB_CTRL7 0x55 +#define TPS65912_LEDB_CTRL8 0x56 +#define TPS65912_LEDC_CTRL1 0x57 +#define TPS65912_LEDC_CTRL2 0x58 +#define TPS65912_LEDC_CTRL3 0x59 +#define TPS65912_LEDC_CTRL4 0x5A +#define TPS65912_LEDC_CTRL5 0x5B +#define TPS65912_LEDC_CTRL6 0x5C +#define TPS65912_LEDC_CTRL7 0x5D +#define TPS65912_LEDC_CTRL8 0x5E +#define TPS65912_LED_RAMP_UP_TIME 0x5F +#define TPS65912_LED_RAMP_DOWN_TIME 0x60 +#define TPS65912_LED_SEQ_EN 0x61 +#define TPS65912_LOADSWITCH 0x62 +#define TPS65912_SPARE 0x63 +#define TPS65912_VERNUM 0x64 +#define TPS6591X_MAX_REGISTER 0x64 + +/* IRQ Definitions */ +#define TPS65912_IRQ_PWRHOLD_F 0 +#define TPS65912_IRQ_VMON 1 +#define TPS65912_IRQ_PWRON 2 +#define TPS65912_IRQ_PWRON_LP 3 +#define TPS65912_IRQ_PWRHOLD_R 4 +#define TPS65912_IRQ_HOTDIE 5 +#define TPS65912_IRQ_GPIO1_R 6 +#define TPS65912_IRQ_GPIO1_F 7 +#define TPS65912_IRQ_GPIO2_R 8 +#define TPS65912_IRQ_GPIO2_F 9 +#define TPS65912_IRQ_GPIO3_R 10 +#define TPS65912_IRQ_GPIO3_F 11 +#define TPS65912_IRQ_GPIO4_R 12 +#define TPS65912_IRQ_GPIO4_F 13 +#define TPS65912_IRQ_GPIO5_R 14 +#define TPS65912_IRQ_GPIO5_F 15 +#define TPS65912_IRQ_PGOOD_DCDC1 16 +#define TPS65912_IRQ_PGOOD_DCDC2 17 +#define TPS65912_IRQ_PGOOD_DCDC3 18 +#define TPS65912_IRQ_PGOOD_DCDC4 19 +#define TPS65912_IRQ_PGOOD_LDO1 20 +#define TPS65912_IRQ_PGOOD_LDO2 21 +#define TPS65912_IRQ_PGOOD_LDO3 22 +#define TPS65912_IRQ_PGOOD_LDO4 23 +#define TPS65912_IRQ_PGOOD_LDO5 24 +#define TPS65912_IRQ_PGOOD_LDO6 25 +#define TPS65912_IRQ_PGOOD_LDO7 26 +#define TPS65912_IRQ_PGOOD_LD08 27 +#define TPS65912_IRQ_PGOOD_LDO9 28 +#define TPS65912_IRQ_PGOOD_LDO10 29 + +#define TPS65912_NUM_IRQ 30 + +/* GPIO 1 and 2 Register Definitions */ +#define GPIO_SLEEP_MASK 0x80 +#define GPIO_SLEEP_SHIFT 7 +#define GPIO_DEB_MASK 0x10 +#define GPIO_DEB_SHIFT 4 +#define GPIO_CFG_MASK 0x04 +#define GPIO_CFG_SHIFT 2 +#define GPIO_STS_MASK 0x02 +#define GPIO_STS_SHIFT 1 +#define GPIO_SET_MASK 0x01 +#define GPIO_SET_SHIFT 0 + +/* GPIO 3 Register Definitions */ +#define GPIO3_SLEEP_MASK 0x80 +#define GPIO3_SLEEP_SHIFT 7 +#define GPIO3_SEL_MASK 0x40 +#define GPIO3_SEL_SHIFT 6 +#define GPIO3_ODEN_MASK 0x20 +#define GPIO3_ODEN_SHIFT 5 +#define GPIO3_DEB_MASK 0x10 +#define GPIO3_DEB_SHIFT 4 +#define GPIO3_PDEN_MASK 0x08 +#define GPIO3_PDEN_SHIFT 3 +#define GPIO3_CFG_MASK 0x04 +#define GPIO3_CFG_SHIFT 2 +#define GPIO3_STS_MASK 0x02 +#define GPIO3_STS_SHIFT 1 +#define GPIO3_SET_MASK 0x01 +#define GPIO3_SET_SHIFT 0 + +/* GPIO 4 Register Definitions */ +#define GPIO4_SLEEP_MASK 0x80 +#define GPIO4_SLEEP_SHIFT 7 +#define GPIO4_SEL_MASK 0x40 +#define GPIO4_SEL_SHIFT 6 +#define GPIO4_ODEN_MASK 0x20 +#define GPIO4_ODEN_SHIFT 5 +#define GPIO4_DEB_MASK 0x10 +#define GPIO4_DEB_SHIFT 4 +#define GPIO4_PDEN_MASK 0x08 +#define GPIO4_PDEN_SHIFT 3 +#define GPIO4_CFG_MASK 0x04 +#define GPIO4_CFG_SHIFT 2 +#define GPIO4_STS_MASK 0x02 +#define GPIO4_STS_SHIFT 1 +#define GPIO4_SET_MASK 0x01 +#define GPIO4_SET_SHIFT 0 + +/* Register THERM (0x80) register.RegisterDescription */ +#define THERM_THERM_HD_MASK 0x20 +#define THERM_THERM_HD_SHIFT 5 +#define THERM_THERM_TS_MASK 0x10 +#define THERM_THERM_TS_SHIFT 4 +#define THERM_THERM_HDSEL_MASK 0x0C +#define THERM_THERM_HDSEL_SHIFT 2 +#define THERM_RSVD1_MASK 0x02 +#define THERM_RSVD1_SHIFT 1 +#define THERM_THERM_STATE_MASK 0x01 +#define THERM_THERM_STATE_SHIFT 0 + +/* Register DCDCCTRL1 register.RegisterDescription */ +#define DCDCCTRL_VCON_ENABLE_MASK 0x80 +#define DCDCCTRL_VCON_ENABLE_SHIFT 7 +#define DCDCCTRL_VCON_RANGE1_MASK 0x40 +#define DCDCCTRL_VCON_RANGE1_SHIFT 6 +#define DCDCCTRL_VCON_RANGE0_MASK 0x20 +#define DCDCCTRL_VCON_RANGE0_SHIFT 5 +#define DCDCCTRL_TSTEP2_MASK 0x10 +#define DCDCCTRL_TSTEP2_SHIFT 4 +#define DCDCCTRL_TSTEP1_MASK 0x08 +#define DCDCCTRL_TSTEP1_SHIFT 3 +#define DCDCCTRL_TSTEP0_MASK 0x04 +#define DCDCCTRL_TSTEP0_SHIFT 2 +#define DCDCCTRL_DCDC1_MODE_MASK 0x02 +#define DCDCCTRL_DCDC1_MODE_SHIFT 1 + +/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */ +#define DCDCCTRL_TSTEP2_MASK 0x10 +#define DCDCCTRL_TSTEP2_SHIFT 4 +#define DCDCCTRL_TSTEP1_MASK 0x08 +#define DCDCCTRL_TSTEP1_SHIFT 3 +#define DCDCCTRL_TSTEP0_MASK 0x04 +#define DCDCCTRL_TSTEP0_SHIFT 2 +#define DCDCCTRL_DCDC_MODE_MASK 0x02 +#define DCDCCTRL_DCDC_MODE_SHIFT 1 +#define DCDCCTRL_RSVD0_MASK 0x01 +#define DCDCCTRL_RSVD0_SHIFT 0 + +/* Register DCDCCTRL4 register.RegisterDescription */ +#define DCDCCTRL_RAMP_TIME_MASK 0x01 +#define DCDCCTRL_RAMP_TIME_SHIFT 0 + +/* Register DCDCx_AVS */ +#define DCDC_AVS_ENABLE_MASK 0x80 +#define DCDC_AVS_ENABLE_SHIFT 7 +#define DCDC_AVS_ECO_MASK 0x40 +#define DCDC_AVS_ECO_SHIFT 6 + +/* Register DCDCx_LIMIT */ +#define DCDC_LIMIT_RANGE_MASK 0xC0 +#define DCDC_LIMIT_RANGE_SHIFT 6 +#define DCDC_LIMIT_MAX_SEL_MASK 0x3F +#define DCDC_LIMIT_MAX_SEL_SHIFT 0 + +/** + * struct tps65912_board + * Board platform dat may be used to initialize regulators. + */ +struct tps65912_board { + int is_dcdc1_avs; + int is_dcdc2_avs; + int is_dcdc3_avs; + int is_dcdc4_avs; + struct regulator_init_data *tps65912_pmic_init_data; +}; + +/** + * struct tps65912 - tps65912 sub-driver chip access routines + */ + +struct tps65912 { + struct device *dev; + /* for read/write acces */ + struct mutex io_mutex; + + /* For device IO interfaces: I2C or SPI */ + void *control_data; + + int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest); + int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src); + + /* Client devices */ + struct tps65912_pmic *pmic; + + /* GPIO Handling */ + struct gpio_chip gpio; + + /* IRQ Handling */ + struct mutex irq_lock; + int chip_irq; + int irq_base; + int irq_num; + u32 irq_mask; +}; + +struct tps65912_platform_data { + int irq_base; +}; + +unsigned int tps_chip(void); + +int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask); +int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask); +int tps65912_reg_read(struct tps65912 *tps65912, u8 reg); +int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val); +int tps65912_device_init(struct tps65912 *tps65912); +void tps65912_device_exit(struct tps65912 *tps65912); + +#endif /* __LINUX_MFD_TPS65912_H */ -- cgit v1.2.3 From d49a0f3f14a763242b71244019d7881ee06e0658 Mon Sep 17 00:00:00 2001 From: Margarita Olaya Date: Thu, 9 Jun 2011 14:50:13 -0500 Subject: tps65912: irq: add interrupt controller This module controls the interrupt handling for the tps65912. The interrupt sources can be the following: - GPIO - PWRON signal - PWRHOLD signal - Temperature detection Signed-off-by: Margarita Olaya Cabrera Acked-by: Samuel Ortiz Acked-by: Liam Girdwood Signed-off-by: Samuel Ortiz --- include/linux/mfd/tps65912.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h index 48d3b53316a9..be60fb23b583 100644 --- a/include/linux/mfd/tps65912.h +++ b/include/linux/mfd/tps65912.h @@ -273,6 +273,8 @@ struct tps65912_board { int is_dcdc2_avs; int is_dcdc3_avs; int is_dcdc4_avs; + int irq; + int irq_base; struct regulator_init_data *tps65912_pmic_init_data; }; @@ -306,6 +308,7 @@ struct tps65912 { }; struct tps65912_platform_data { + int irq; int irq_base; }; @@ -317,5 +320,7 @@ int tps65912_reg_read(struct tps65912 *tps65912, u8 reg); int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val); int tps65912_device_init(struct tps65912 *tps65912); void tps65912_device_exit(struct tps65912 *tps65912); +int tps65912_irq_init(struct tps65912 *tps65912, int irq, + struct tps65912_platform_data *pdata); #endif /* __LINUX_MFD_TPS65912_H */ -- cgit v1.2.3 From 668a6cc710ee054af2b059d27bbec746ead0fbca Mon Sep 17 00:00:00 2001 From: Margarita Olaya Date: Thu, 9 Jun 2011 14:50:19 -0500 Subject: tps65912: gpio: add gpio driver TPS65912 has five GPIOs that can be configured for different purposes. Signed-off-by: Margarita Olaya Cabrera Acked-by: Grant Likely Acked-by: Liam Girdwood Signed-off-by: Samuel Ortiz --- include/linux/mfd/tps65912.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h index be60fb23b583..aaceab402ec5 100644 --- a/include/linux/mfd/tps65912.h +++ b/include/linux/mfd/tps65912.h @@ -275,6 +275,7 @@ struct tps65912_board { int is_dcdc4_avs; int irq; int irq_base; + int gpio_base; struct regulator_init_data *tps65912_pmic_init_data; }; -- cgit v1.2.3 From 0a1b089738cf2165ee8678e2483fce3c40389d4a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Jun 2011 23:57:57 +0200 Subject: mfd: Clean-up ab8500 register file This adds a previously undefined test register and removed a number of double-defined accessory detect registers (they are already defined higher up in the file. Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/ab8500.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h index b31843075198..838c6b487cc5 100644 --- a/include/linux/mfd/ab8500.h +++ b/include/linux/mfd/ab8500.h @@ -28,6 +28,7 @@ #define AB8500_INTERRUPT 0xE #define AB8500_RTC 0xF #define AB8500_MISC 0x10 +#define AB8500_DEVELOPMENT 0x11 #define AB8500_DEBUG 0x12 #define AB8500_PROD_TEST 0x13 #define AB8500_OTP_EMUL 0x15 @@ -74,13 +75,6 @@ #define AB8500_INT_ACC_DETECT_21DB_F 37 #define AB8500_INT_ACC_DETECT_21DB_R 38 #define AB8500_INT_GP_SW_ADC_CONV_END 39 -#define AB8500_INT_ACC_DETECT_1DB_F 33 -#define AB8500_INT_ACC_DETECT_1DB_R 34 -#define AB8500_INT_ACC_DETECT_22DB_F 35 -#define AB8500_INT_ACC_DETECT_22DB_R 36 -#define AB8500_INT_ACC_DETECT_21DB_F 37 -#define AB8500_INT_ACC_DETECT_21DB_R 38 -#define AB8500_INT_GP_SW_ADC_CONV_END 39 #define AB8500_INT_GPIO6R 40 #define AB8500_INT_GPIO7R 41 #define AB8500_INT_GPIO8R 42 -- cgit v1.2.3 From ec2328c30bf09fe31e77889090eeb1a965325f53 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 20 Jun 2011 11:47:55 +0100 Subject: mfd: Implement tps65910 IRQ cleanup The tps65910_irq_exit() cleanup function was generating a warning from sparse due to the lack of a prototype. This wasn't causing GCC warnings as the driver wasn't cleaning up its IRQs on exit at all so there was no use of an unprototyped function. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/tps65910.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 73572c65d04f..82b4c8801a4f 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -791,6 +791,7 @@ int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); int tps65910_irq_init(struct tps65910 *tps65910, int irq, struct tps65910_platform_data *pdata); +int tps65910_irq_exit(struct tps65910 *tps65910); static inline int tps65910_chip_id(struct tps65910 *tps65910) { -- cgit v1.2.3 From c7e1da477293b4b5e0bef3639b3734e28d5d55f7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 21 Jun 2011 11:12:23 +0100 Subject: mfd: Add WM831x clock control register definitions Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 101 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 9fa14cdc1590..8dda8ded5cda 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -235,6 +235,107 @@ #define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */ #define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */ +/* + * R16528 (0x4090) - Clock Control 1 + */ +#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */ +#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */ +#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */ +#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */ +#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */ +#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */ +#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */ +#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */ +#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */ +#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */ +#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */ +#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */ +#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */ +#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */ +#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */ +#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */ +#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */ +#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */ + +/* + * R16529 (0x4091) - Clock Control 2 + */ +#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */ +#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */ +#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */ +#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */ +#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */ +#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */ +#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */ +#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */ +#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */ +#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */ +#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */ +#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */ +#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */ +#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */ +#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */ +#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */ +#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */ +#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */ +#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */ + +/* + * R16530 (0x4092) - FLL Control 1 + */ +#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */ +#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */ +#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */ +#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */ +#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ +#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ +#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ +#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ +#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */ +#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */ +#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */ +#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */ + +/* + * R16531 (0x4093) - FLL Control 2 + */ +#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ +#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ +#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ +#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ +#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ +#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ +#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ +#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ +#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ + +/* + * R16532 (0x4094) - FLL Control 3 + */ +#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ +#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ +#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ + +/* + * R16533 (0x4095) - FLL Control 4 + */ +#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ +#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ +#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ +#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ +#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ +#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ + +/* + * R16534 (0x4096) - FLL Control 5 + */ +#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ +#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ +#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ +#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */ +#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */ +#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */ + struct regulator_dev; #define WM831X_NUM_IRQ_REGS 5 -- cgit v1.2.3 From 4dcaa6b6df354fa44b3072bed3cb13aad7e5fbd4 Mon Sep 17 00:00:00 2001 From: Om Prakash Date: Mon, 27 Jun 2011 09:54:22 +0200 Subject: mfd: Fix missing stmpe kerneldoc Generating kerneldoc for STMPE result in warnings, so fix this by adding missing documentation. Signed-off-by: Om Prakash Reviewed-by: Rabin Vincent Reviewed-by: Jonas Aberg Reviewed-by: Srinidhi Kasagar Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/stmpe.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index e762c270d8d4..be1af7c42e57 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -57,6 +57,7 @@ struct stmpe_variant_info; * @irq_lock: IRQ bus lock * @dev: device, mostly for dev_dbg() * @i2c: i2c client + * @partnum: part number * @variant: the detected STMPE model number * @regs: list of addresses of registers which are at different addresses on * different variants. Indexed by one of STMPE_IDX_*. @@ -121,6 +122,8 @@ struct stmpe_keypad_platform_data { * @norequest_mask: bitmask specifying which GPIOs should _not_ be * requestable due to different usage (e.g. touch, keypad) * STMPE_GPIO_NOREQ_* macros can be used here. + * @setup: board specific setup callback. + * @remove: board specific remove callback */ struct stmpe_gpio_platform_data { int gpio_base; -- cgit v1.2.3 From 09d6292befba8c6319d9471803149573ea6ed170 Mon Sep 17 00:00:00 2001 From: Jin Park Date: Mon, 4 Jul 2011 19:48:12 +0200 Subject: mfd: Add AAT2870 mfd driver Add mfd core driver for AnalogicTech AAT2870. The AAT2870 is communication through I2C and contains backlight and regulator components. Signed-off-by: Jin Park Signed-off-by: Samuel Ortiz --- include/linux/mfd/aat2870.h | 181 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) create mode 100644 include/linux/mfd/aat2870.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/aat2870.h b/include/linux/mfd/aat2870.h new file mode 100644 index 000000000000..89212df05622 --- /dev/null +++ b/include/linux/mfd/aat2870.h @@ -0,0 +1,181 @@ +/* + * linux/include/linux/mfd/aat2870.h + * + * Copyright (c) 2011, NVIDIA Corporation. + * Author: Jin Park + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#ifndef __LINUX_MFD_AAT2870_H +#define __LINUX_MFD_AAT2870_H + +#include +#include + +/* Register offsets */ +#define AAT2870_BL_CH_EN 0x00 +#define AAT2870_BLM 0x01 +#define AAT2870_BLS 0x02 +#define AAT2870_BL1 0x03 +#define AAT2870_BL2 0x04 +#define AAT2870_BL3 0x05 +#define AAT2870_BL4 0x06 +#define AAT2870_BL5 0x07 +#define AAT2870_BL6 0x08 +#define AAT2870_BL7 0x09 +#define AAT2870_BL8 0x0A +#define AAT2870_FLR 0x0B +#define AAT2870_FM 0x0C +#define AAT2870_FS 0x0D +#define AAT2870_ALS_CFG0 0x0E +#define AAT2870_ALS_CFG1 0x0F +#define AAT2870_ALS_CFG2 0x10 +#define AAT2870_AMB 0x11 +#define AAT2870_ALS0 0x12 +#define AAT2870_ALS1 0x13 +#define AAT2870_ALS2 0x14 +#define AAT2870_ALS3 0x15 +#define AAT2870_ALS4 0x16 +#define AAT2870_ALS5 0x17 +#define AAT2870_ALS6 0x18 +#define AAT2870_ALS7 0x19 +#define AAT2870_ALS8 0x1A +#define AAT2870_ALS9 0x1B +#define AAT2870_ALSA 0x1C +#define AAT2870_ALSB 0x1D +#define AAT2870_ALSC 0x1E +#define AAT2870_ALSD 0x1F +#define AAT2870_ALSE 0x20 +#define AAT2870_ALSF 0x21 +#define AAT2870_SUB_SET 0x22 +#define AAT2870_SUB_CTRL 0x23 +#define AAT2870_LDO_AB 0x24 +#define AAT2870_LDO_CD 0x25 +#define AAT2870_LDO_EN 0x26 +#define AAT2870_REG_NUM 0x27 + +/* Device IDs */ +enum aat2870_id { + AAT2870_ID_BL, + AAT2870_ID_LDOA, + AAT2870_ID_LDOB, + AAT2870_ID_LDOC, + AAT2870_ID_LDOD +}; + +/* Backlight channels */ +#define AAT2870_BL_CH1 0x01 +#define AAT2870_BL_CH2 0x02 +#define AAT2870_BL_CH3 0x04 +#define AAT2870_BL_CH4 0x08 +#define AAT2870_BL_CH5 0x10 +#define AAT2870_BL_CH6 0x20 +#define AAT2870_BL_CH7 0x40 +#define AAT2870_BL_CH8 0x80 +#define AAT2870_BL_CH_ALL 0xFF + +/* Backlight current magnitude (mA) */ +enum aat2870_current { + AAT2870_CURRENT_0_45, + AAT2870_CURRENT_0_90, + AAT2870_CURRENT_1_80, + AAT2870_CURRENT_2_70, + AAT2870_CURRENT_3_60, + AAT2870_CURRENT_4_50, + AAT2870_CURRENT_5_40, + AAT2870_CURRENT_6_30, + AAT2870_CURRENT_7_20, + AAT2870_CURRENT_8_10, + AAT2870_CURRENT_9_00, + AAT2870_CURRENT_9_90, + AAT2870_CURRENT_10_8, + AAT2870_CURRENT_11_7, + AAT2870_CURRENT_12_6, + AAT2870_CURRENT_13_5, + AAT2870_CURRENT_14_4, + AAT2870_CURRENT_15_3, + AAT2870_CURRENT_16_2, + AAT2870_CURRENT_17_1, + AAT2870_CURRENT_18_0, + AAT2870_CURRENT_18_9, + AAT2870_CURRENT_19_8, + AAT2870_CURRENT_20_7, + AAT2870_CURRENT_21_6, + AAT2870_CURRENT_22_5, + AAT2870_CURRENT_23_4, + AAT2870_CURRENT_24_3, + AAT2870_CURRENT_25_2, + AAT2870_CURRENT_26_1, + AAT2870_CURRENT_27_0, + AAT2870_CURRENT_27_9 +}; + +struct aat2870_register { + bool readable; + bool writeable; + u8 value; +}; + +struct aat2870_data { + struct device *dev; + struct i2c_client *client; + + struct mutex io_lock; + struct aat2870_register *reg_cache; /* register cache */ + int en_pin; /* enable GPIO pin (if < 0, ignore this value) */ + bool is_enable; + + /* init and uninit for platform specified */ + int (*init)(struct aat2870_data *aat2870); + void (*uninit)(struct aat2870_data *aat2870); + + /* i2c io funcntions */ + int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val); + int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val); + int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val); + + /* for debugfs */ + struct dentry *dentry_root; + struct dentry *dentry_reg; +}; + +struct aat2870_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct aat2870_platform_data { + int en_pin; /* enable GPIO pin (if < 0, ignore this value) */ + + struct aat2870_subdev_info *subdevs; + int num_subdevs; + + /* init and uninit for platform specified */ + int (*init)(struct aat2870_data *aat2870); + void (*uninit)(struct aat2870_data *aat2870); +}; + +struct aat2870_bl_platform_data { + /* backlight channels, default is AAT2870_BL_CH_ALL */ + int channels; + /* backlight current magnitude, default is AAT2870_CURRENT_27_9 */ + int max_current; + /* maximum brightness, default is 255 */ + int max_brightness; +}; + +#endif /* __LINUX_MFD_AAT2870_H */ -- cgit v1.2.3 From 5d6f921b42749d1a70441685b7a4f2801e12ebfb Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Wed, 3 Aug 2011 16:21:17 -0700 Subject: drivers/video/backlight/aat2870_bl.c: fix setting max_current - Current implementation tests wrong value for setting aat2870_bl->max_current. - In the current implementation, we cannot differentiate between 2 cases: a) if pdata->max_current is not set , or b) pdata->max_current is set to AAT2870_CURRENT_0_45 (which is also 0). Fix it by setting AAT2870_CURRENT_0_45 to be 1 and adjust the equation in aat2870_brightness() accordingly. Signed-off-by: Axel Lin Cc: Richard Purdie Cc: Samuel Ortiz Tested-by: Jin Park Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/mfd/aat2870.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/aat2870.h b/include/linux/mfd/aat2870.h index 89212df05622..f7316c29bdec 100644 --- a/include/linux/mfd/aat2870.h +++ b/include/linux/mfd/aat2870.h @@ -89,7 +89,7 @@ enum aat2870_id { /* Backlight current magnitude (mA) */ enum aat2870_current { - AAT2870_CURRENT_0_45, + AAT2870_CURRENT_0_45 = 1, AAT2870_CURRENT_0_90, AAT2870_CURRENT_1_80, AAT2870_CURRENT_2_70, -- cgit v1.2.3