From 8dc7ab65bd15e3c774f60ca073158bcb9a26ee5b Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 2 Feb 2026 10:05:25 +0200 Subject: usb: phy: tegra: parametrize HSIC PTS value The parallel transceiver select used in HSIC mode differs on Tegra20, where it uses the UTMI value (0), whereas Tegra30+ uses a dedicated HSIC value. Reflect this in the SoC config. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Link: https://patch.msgid.link/20260202080526.23487-4-clamor95@gmail.com Signed-off-by: Greg Kroah-Hartman --- include/linux/usb/tegra_usb_phy.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/usb') diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h index 91420df25627..7209b7731c29 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -26,6 +26,7 @@ struct gpio_desc; * uhsic_registers_offset: for Tegra30+ where HSIC registers were offset * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS driver + * uhsic_pts_value: parallel transceiver select enumeration value */ struct tegra_phy_soc_config { @@ -36,6 +37,7 @@ struct tegra_phy_soc_config { bool requires_pmc_ao_power_up; u32 uhsic_registers_offset; u32 uhsic_tx_rtune; + u32 uhsic_pts_value; }; struct tegra_utmip_config { -- cgit v1.2.3