From 5267cf02c7794953d89e9593a0d497bf43e3790d Mon Sep 17 00:00:00 2001 From: Bjarke Istrup Pedersen Date: Wed, 22 Jan 2014 09:16:58 +0000 Subject: hv: Add hyperv.h to uapi headers This patch adds the hyperv.h header to the uapi folder, and adds it to the Kbuild file. Doing this enables compiling userspace Hyper-V tools using the installed headers. Version 2: Split UAPI parts into new header, instead of duplicating. Signed-off-by: Bjarke Istrup Pedersen Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 321 +------------------------------------------------ 1 file changed, 2 insertions(+), 319 deletions(-) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 15da677478dd..167ef47e3d6e 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -25,325 +25,9 @@ #ifndef _HYPERV_H #define _HYPERV_H -#include - -/* - * Framework version for util services. - */ -#define UTIL_FW_MINOR 0 - -#define UTIL_WS2K8_FW_MAJOR 1 -#define UTIL_WS2K8_FW_VERSION (UTIL_WS2K8_FW_MAJOR << 16 | UTIL_FW_MINOR) - -#define UTIL_FW_MAJOR 3 -#define UTIL_FW_VERSION (UTIL_FW_MAJOR << 16 | UTIL_FW_MINOR) - - -/* - * Implementation of host controlled snapshot of the guest. - */ - -#define VSS_OP_REGISTER 128 - -enum hv_vss_op { - VSS_OP_CREATE = 0, - VSS_OP_DELETE, - VSS_OP_HOT_BACKUP, - VSS_OP_GET_DM_INFO, - VSS_OP_BU_COMPLETE, - /* - * Following operations are only supported with IC version >= 5.0 - */ - VSS_OP_FREEZE, /* Freeze the file systems in the VM */ - VSS_OP_THAW, /* Unfreeze the file systems */ - VSS_OP_AUTO_RECOVER, - VSS_OP_COUNT /* Number of operations, must be last */ -}; - - -/* - * Header for all VSS messages. - */ -struct hv_vss_hdr { - __u8 operation; - __u8 reserved[7]; -} __attribute__((packed)); - - -/* - * Flag values for the hv_vss_check_feature. Linux supports only - * one value. - */ -#define VSS_HBU_NO_AUTO_RECOVERY 0x00000005 - -struct hv_vss_check_feature { - __u32 flags; -} __attribute__((packed)); - -struct hv_vss_check_dm_info { - __u32 flags; -} __attribute__((packed)); - -struct hv_vss_msg { - union { - struct hv_vss_hdr vss_hdr; - int error; - }; - union { - struct hv_vss_check_feature vss_cf; - struct hv_vss_check_dm_info dm_info; - }; -} __attribute__((packed)); - -/* - * An implementation of HyperV key value pair (KVP) functionality for Linux. - * - * - * Copyright (C) 2010, Novell, Inc. - * Author : K. Y. Srinivasan - * - */ - -/* - * Maximum value size - used for both key names and value data, and includes - * any applicable NULL terminators. - * - * Note: This limit is somewhat arbitrary, but falls easily within what is - * supported for all native guests (back to Win 2000) and what is reasonable - * for the IC KVP exchange functionality. Note that Windows Me/98/95 are - * limited to 255 character key names. - * - * MSDN recommends not storing data values larger than 2048 bytes in the - * registry. - * - * Note: This value is used in defining the KVP exchange message - this value - * cannot be modified without affecting the message size and compatibility. - */ - -/* - * bytes, including any null terminators - */ -#define HV_KVP_EXCHANGE_MAX_VALUE_SIZE (2048) - - -/* - * Maximum key size - the registry limit for the length of an entry name - * is 256 characters, including the null terminator - */ - -#define HV_KVP_EXCHANGE_MAX_KEY_SIZE (512) +#include -/* - * In Linux, we implement the KVP functionality in two components: - * 1) The kernel component which is packaged as part of the hv_utils driver - * is responsible for communicating with the host and responsible for - * implementing the host/guest protocol. 2) A user level daemon that is - * responsible for data gathering. - * - * Host/Guest Protocol: The host iterates over an index and expects the guest - * to assign a key name to the index and also return the value corresponding to - * the key. The host will have atmost one KVP transaction outstanding at any - * given point in time. The host side iteration stops when the guest returns - * an error. Microsoft has specified the following mapping of key names to - * host specified index: - * - * Index Key Name - * 0 FullyQualifiedDomainName - * 1 IntegrationServicesVersion - * 2 NetworkAddressIPv4 - * 3 NetworkAddressIPv6 - * 4 OSBuildNumber - * 5 OSName - * 6 OSMajorVersion - * 7 OSMinorVersion - * 8 OSVersion - * 9 ProcessorArchitecture - * - * The Windows host expects the Key Name and Key Value to be encoded in utf16. - * - * Guest Kernel/KVP Daemon Protocol: As noted earlier, we implement all of the - * data gathering functionality in a user mode daemon. The user level daemon - * is also responsible for binding the key name to the index as well. The - * kernel and user-level daemon communicate using a connector channel. - * - * The user mode component first registers with the - * the kernel component. Subsequently, the kernel component requests, data - * for the specified keys. In response to this message the user mode component - * fills in the value corresponding to the specified key. We overload the - * sequence field in the cn_msg header to define our KVP message types. - * - * - * The kernel component simply acts as a conduit for communication between the - * Windows host and the user-level daemon. The kernel component passes up the - * index received from the Host to the user-level daemon. If the index is - * valid (supported), the corresponding key as well as its - * value (both are strings) is returned. If the index is invalid - * (not supported), a NULL key string is returned. - */ - - -/* - * Registry value types. - */ - -#define REG_SZ 1 -#define REG_U32 4 -#define REG_U64 8 - -/* - * As we look at expanding the KVP functionality to include - * IP injection functionality, we need to maintain binary - * compatibility with older daemons. - * - * The KVP opcodes are defined by the host and it was unfortunate - * that I chose to treat the registration operation as part of the - * KVP operations defined by the host. - * Here is the level of compatibility - * (between the user level daemon and the kernel KVP driver) that we - * will implement: - * - * An older daemon will always be supported on a newer driver. - * A given user level daemon will require a minimal version of the - * kernel driver. - * If we cannot handle the version differences, we will fail gracefully - * (this can happen when we have a user level daemon that is more - * advanced than the KVP driver. - * - * We will use values used in this handshake for determining if we have - * workable user level daemon and the kernel driver. We begin by taking the - * registration opcode out of the KVP opcode namespace. We will however, - * maintain compatibility with the existing user-level daemon code. - */ - -/* - * Daemon code not supporting IP injection (legacy daemon). - */ - -#define KVP_OP_REGISTER 4 - -/* - * Daemon code supporting IP injection. - * The KVP opcode field is used to communicate the - * registration information; so define a namespace that - * will be distinct from the host defined KVP opcode. - */ - -#define KVP_OP_REGISTER1 100 - -enum hv_kvp_exchg_op { - KVP_OP_GET = 0, - KVP_OP_SET, - KVP_OP_DELETE, - KVP_OP_ENUMERATE, - KVP_OP_GET_IP_INFO, - KVP_OP_SET_IP_INFO, - KVP_OP_COUNT /* Number of operations, must be last. */ -}; - -enum hv_kvp_exchg_pool { - KVP_POOL_EXTERNAL = 0, - KVP_POOL_GUEST, - KVP_POOL_AUTO, - KVP_POOL_AUTO_EXTERNAL, - KVP_POOL_AUTO_INTERNAL, - KVP_POOL_COUNT /* Number of pools, must be last. */ -}; - -/* - * Some Hyper-V status codes. - */ - -#define HV_S_OK 0x00000000 -#define HV_E_FAIL 0x80004005 -#define HV_S_CONT 0x80070103 -#define HV_ERROR_NOT_SUPPORTED 0x80070032 -#define HV_ERROR_MACHINE_LOCKED 0x800704F7 -#define HV_ERROR_DEVICE_NOT_CONNECTED 0x8007048F -#define HV_INVALIDARG 0x80070057 -#define HV_GUID_NOTFOUND 0x80041002 - -#define ADDR_FAMILY_NONE 0x00 -#define ADDR_FAMILY_IPV4 0x01 -#define ADDR_FAMILY_IPV6 0x02 - -#define MAX_ADAPTER_ID_SIZE 128 -#define MAX_IP_ADDR_SIZE 1024 -#define MAX_GATEWAY_SIZE 512 - - -struct hv_kvp_ipaddr_value { - __u16 adapter_id[MAX_ADAPTER_ID_SIZE]; - __u8 addr_family; - __u8 dhcp_enabled; - __u16 ip_addr[MAX_IP_ADDR_SIZE]; - __u16 sub_net[MAX_IP_ADDR_SIZE]; - __u16 gate_way[MAX_GATEWAY_SIZE]; - __u16 dns_addr[MAX_IP_ADDR_SIZE]; -} __attribute__((packed)); - - -struct hv_kvp_hdr { - __u8 operation; - __u8 pool; - __u16 pad; -} __attribute__((packed)); - -struct hv_kvp_exchg_msg_value { - __u32 value_type; - __u32 key_size; - __u32 value_size; - __u8 key[HV_KVP_EXCHANGE_MAX_KEY_SIZE]; - union { - __u8 value[HV_KVP_EXCHANGE_MAX_VALUE_SIZE]; - __u32 value_u32; - __u64 value_u64; - }; -} __attribute__((packed)); - -struct hv_kvp_msg_enumerate { - __u32 index; - struct hv_kvp_exchg_msg_value data; -} __attribute__((packed)); - -struct hv_kvp_msg_get { - struct hv_kvp_exchg_msg_value data; -}; - -struct hv_kvp_msg_set { - struct hv_kvp_exchg_msg_value data; -}; - -struct hv_kvp_msg_delete { - __u32 key_size; - __u8 key[HV_KVP_EXCHANGE_MAX_KEY_SIZE]; -}; - -struct hv_kvp_register { - __u8 version[HV_KVP_EXCHANGE_MAX_KEY_SIZE]; -}; - -struct hv_kvp_msg { - union { - struct hv_kvp_hdr kvp_hdr; - int error; - }; - union { - struct hv_kvp_msg_get kvp_get; - struct hv_kvp_msg_set kvp_set; - struct hv_kvp_msg_delete kvp_delete; - struct hv_kvp_msg_enumerate kvp_enum_data; - struct hv_kvp_ipaddr_value kvp_ip_val; - struct hv_kvp_register kvp_register; - } body; -} __attribute__((packed)); - -struct hv_kvp_ip_msg { - __u8 operation; - __u8 pool; - struct hv_kvp_ipaddr_value kvp_ip_val; -} __attribute__((packed)); - -#ifdef __KERNEL__ +#include #include #include #include @@ -1465,5 +1149,4 @@ void hv_vss_onchannelcallback(void *); extern __u32 vmbus_proto_version; -#endif /* __KERNEL__ */ #endif /* _HYPERV_H */ -- cgit v1.2.3 From 90f3453585479d5beb75058da46eb573ced0e6ac Mon Sep 17 00:00:00 2001 From: "K. Y. Srinivasan" Date: Wed, 29 Jan 2014 18:14:39 -0800 Subject: Drivers: hv: vmbus: Extract the mmio information from DSDT On Gen2 firmware, Hyper-V does not emulate the PCI bus. However, the MMIO information is packaged up in DSDT. Extract this information and export it for use by the synthetic framebuffer driver. This is the only driver that needs this currently. In this version of the patch mmio, I have updated the hyperv header file (linux/hyperv.h) with mmio definitions. Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 167ef47e3d6e..6b862dadbb7a 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -1143,6 +1143,9 @@ int hv_vss_init(struct hv_util_service *); void hv_vss_deinit(void); void hv_vss_onchannelcallback(void *); +extern u64 hyperv_mmio_start; +extern u64 hyperv_mmio_size; + /* * Negotiated version with the Host. */ -- cgit v1.2.3 From 011a7c3cc3aa60c7ea6bb49d847e80a299ba7b36 Mon Sep 17 00:00:00 2001 From: "K. Y. Srinivasan" Date: Sat, 1 Feb 2014 19:02:20 -0800 Subject: Drivers: hv: vmbus: Cleanup the packet send path The current channel code is using scatterlist abstraction to pass data to the ringbuffer API on the send path. This causes unnecessary translations between virtual and physical addresses. Fix this. Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 6b862dadbb7a..9b07e1f070ac 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -802,7 +802,7 @@ extern int vmbus_open(struct vmbus_channel *channel, extern void vmbus_close(struct vmbus_channel *channel); extern int vmbus_sendpacket(struct vmbus_channel *channel, - const void *buffer, + void *buffer, u32 bufferLen, u64 requestid, enum vmbus_packet_type type, -- cgit v1.2.3 From 8a7206a89f85c8439561b0eff85bb9440a2e97a9 Mon Sep 17 00:00:00 2001 From: "K. Y. Srinivasan" Date: Mon, 3 Feb 2014 12:42:45 -0800 Subject: Drivers: hv: vmbus: Support per-channel driver state As we implement Virtual Receive Side Scaling on the networking side (the VRSS patches are currently under review), it will be useful to have per-channel state that vmbus drivers can manage. Add support for managing per-channel state. Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 9b07e1f070ac..d47bab9e7a18 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -727,6 +727,10 @@ struct vmbus_channel { * This will be NULL for the primary channel. */ struct vmbus_channel *primary_channel; + /* + * Support per-channel state for use by vmbus drivers. + */ + void *per_channel_state; }; static inline void set_channel_read_state(struct vmbus_channel *c, bool state) @@ -734,6 +738,16 @@ static inline void set_channel_read_state(struct vmbus_channel *c, bool state) c->batched_reading = state; } +static inline void set_per_channel_state(struct vmbus_channel *c, void *s) +{ + c->per_channel_state = s; +} + +static inline void *get_per_channel_state(struct vmbus_channel *c) +{ + return c->per_channel_state; +} + void vmbus_onmessage(void *context); int vmbus_request_offers(void); -- cgit v1.2.3 From ac8f73305eea8a12fdcb6090417eb93a74efbcbd Mon Sep 17 00:00:00 2001 From: David Fries Date: Wed, 15 Jan 2014 22:29:19 -0600 Subject: connector: add portid to unicast in addition to broadcasting This allows replying only to the requestor portid while still supporting broadcasting. Pass 0 to portid for the previous behavior. Signed-off-by: David Fries Acked-by: Evgeniy Polyakov Signed-off-by: Greg Kroah-Hartman --- include/linux/connector.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/connector.h b/include/linux/connector.h index b2b5a41b6a24..be9c4747d511 100644 --- a/include/linux/connector.h +++ b/include/linux/connector.h @@ -71,7 +71,7 @@ struct cn_dev { int cn_add_callback(struct cb_id *id, const char *name, void (*callback)(struct cn_msg *, struct netlink_skb_parms *)); void cn_del_callback(struct cb_id *); -int cn_netlink_send(struct cn_msg *, u32, gfp_t); +int cn_netlink_send(struct cn_msg *msg, u32 portid, u32 group, gfp_t gfp_mask); int cn_queue_add_callback(struct cn_queue_dev *dev, const char *name, struct cb_id *id, -- cgit v1.2.3 From 5a86bf343976b9c8ab2f240bc866451fa67e5573 Mon Sep 17 00:00:00 2001 From: Kenneth Heitke Date: Wed, 12 Feb 2014 13:44:22 -0600 Subject: spmi: Linux driver framework for SPMI System Power Management Interface (SPMI) is a specification developed by the MIPI (Mobile Industry Process Interface) Alliance optimized for the real time control of Power Management ICs (PMIC). SPMI is a two-wire serial interface that supports up to 4 master devices and up to 16 logical slaves. The framework supports message APIs, multiple busses (1 controller per bus) and multiple clients/slave devices per controller. Signed-off-by: Kenneth Heitke Signed-off-by: Michael Bohan Signed-off-by: Josh Cartwright Signed-off-by: Greg Kroah-Hartman --- include/linux/mod_devicetable.h | 8 ++ include/linux/spmi.h | 191 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 199 insertions(+) create mode 100644 include/linux/spmi.h (limited to 'include/linux') diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 45e921401b06..677e474fc273 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -432,6 +432,14 @@ struct spi_device_id { kernel_ulong_t driver_data; /* Data private to the driver */ }; +#define SPMI_NAME_SIZE 32 +#define SPMI_MODULE_PREFIX "spmi:" + +struct spmi_device_id { + char name[SPMI_NAME_SIZE]; + kernel_ulong_t driver_data; /* Data private to the driver */ +}; + /* dmi */ enum dmi_field { DMI_NONE, diff --git a/include/linux/spmi.h b/include/linux/spmi.h new file mode 100644 index 000000000000..91f5eab9e428 --- /dev/null +++ b/include/linux/spmi.h @@ -0,0 +1,191 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _LINUX_SPMI_H +#define _LINUX_SPMI_H + +#include +#include +#include + +/* Maximum slave identifier */ +#define SPMI_MAX_SLAVE_ID 16 + +/* SPMI Commands */ +#define SPMI_CMD_EXT_WRITE 0x00 +#define SPMI_CMD_RESET 0x10 +#define SPMI_CMD_SLEEP 0x11 +#define SPMI_CMD_SHUTDOWN 0x12 +#define SPMI_CMD_WAKEUP 0x13 +#define SPMI_CMD_AUTHENTICATE 0x14 +#define SPMI_CMD_MSTR_READ 0x15 +#define SPMI_CMD_MSTR_WRITE 0x16 +#define SPMI_CMD_TRANSFER_BUS_OWNERSHIP 0x1A +#define SPMI_CMD_DDB_MASTER_READ 0x1B +#define SPMI_CMD_DDB_SLAVE_READ 0x1C +#define SPMI_CMD_EXT_READ 0x20 +#define SPMI_CMD_EXT_WRITEL 0x30 +#define SPMI_CMD_EXT_READL 0x38 +#define SPMI_CMD_WRITE 0x40 +#define SPMI_CMD_READ 0x60 +#define SPMI_CMD_ZERO_WRITE 0x80 + +/** + * struct spmi_device - Basic representation of an SPMI device + * @dev: Driver model representation of the device. + * @ctrl: SPMI controller managing the bus hosting this device. + * @usid: This devices' Unique Slave IDentifier. + */ +struct spmi_device { + struct device dev; + struct spmi_controller *ctrl; + u8 usid; +}; + +static inline struct spmi_device *to_spmi_device(struct device *d) +{ + return container_of(d, struct spmi_device, dev); +} + +static inline void *spmi_device_get_drvdata(const struct spmi_device *sdev) +{ + return dev_get_drvdata(&sdev->dev); +} + +static inline void spmi_device_set_drvdata(struct spmi_device *sdev, void *data) +{ + dev_set_drvdata(&sdev->dev, data); +} + +struct spmi_device *spmi_device_alloc(struct spmi_controller *ctrl); + +static inline void spmi_device_put(struct spmi_device *sdev) +{ + if (sdev) + put_device(&sdev->dev); +} + +int spmi_device_add(struct spmi_device *sdev); + +void spmi_device_remove(struct spmi_device *sdev); + +/** + * struct spmi_controller - interface to the SPMI master controller + * @dev: Driver model representation of the device. + * @nr: board-specific number identifier for this controller/bus + * @cmd: sends a non-data command sequence on the SPMI bus. + * @read_cmd: sends a register read command sequence on the SPMI bus. + * @write_cmd: sends a register write command sequence on the SPMI bus. + */ +struct spmi_controller { + struct device dev; + unsigned int nr; + int (*cmd)(struct spmi_controller *ctrl, u8 opcode, u8 sid); + int (*read_cmd)(struct spmi_controller *ctrl, u8 opcode, + u8 sid, u16 addr, u8 *buf, size_t len); + int (*write_cmd)(struct spmi_controller *ctrl, u8 opcode, + u8 sid, u16 addr, const u8 *buf, size_t len); +}; + +static inline struct spmi_controller *to_spmi_controller(struct device *d) +{ + return container_of(d, struct spmi_controller, dev); +} + +static inline +void *spmi_controller_get_drvdata(const struct spmi_controller *ctrl) +{ + return dev_get_drvdata(&ctrl->dev); +} + +static inline void spmi_controller_set_drvdata(struct spmi_controller *ctrl, + void *data) +{ + dev_set_drvdata(&ctrl->dev, data); +} + +struct spmi_controller *spmi_controller_alloc(struct device *parent, + size_t size); + +/** + * spmi_controller_put() - decrement controller refcount + * @ctrl SPMI controller. + */ +static inline void spmi_controller_put(struct spmi_controller *ctrl) +{ + if (ctrl) + put_device(&ctrl->dev); +} + +int spmi_controller_add(struct spmi_controller *ctrl); +void spmi_controller_remove(struct spmi_controller *ctrl); + +/** + * struct spmi_driver - SPMI slave device driver + * @driver: SPMI device drivers should initialize name and owner field of + * this structure. + * @probe: binds this driver to a SPMI device. + * @remove: unbinds this driver from the SPMI device. + * @shutdown: standard shutdown callback used during powerdown/halt. + * @suspend: standard suspend callback used during system suspend. + * @resume: standard resume callback used during system resume. + * + * If PM runtime support is desired for a slave, a device driver can call + * pm_runtime_put() from their probe() routine (and a balancing + * pm_runtime_get() in remove()). PM runtime support for a slave is + * implemented by issuing a SLEEP command to the slave on runtime_suspend(), + * transitioning the slave into the SLEEP state. On runtime_resume(), a WAKEUP + * command is sent to the slave to bring it back to ACTIVE. + */ +struct spmi_driver { + struct device_driver driver; + int (*probe)(struct spmi_device *sdev); + void (*remove)(struct spmi_device *sdev); +}; + +static inline struct spmi_driver *to_spmi_driver(struct device_driver *d) +{ + return container_of(d, struct spmi_driver, driver); +} + +int spmi_driver_register(struct spmi_driver *sdrv); + +/** + * spmi_driver_unregister() - unregister an SPMI client driver + * @sdrv: the driver to unregister + */ +static inline void spmi_driver_unregister(struct spmi_driver *sdrv) +{ + if (sdrv) + driver_unregister(&sdrv->driver); +} + +#define module_spmi_driver(__spmi_driver) \ + module_driver(__spmi_driver, spmi_driver_register, \ + spmi_driver_unregister) + +int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf); +int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf, + size_t len); +int spmi_ext_register_readl(struct spmi_device *sdev, u16 addr, u8 *buf, + size_t len); +int spmi_register_write(struct spmi_device *sdev, u8 addr, u8 data); +int spmi_register_zero_write(struct spmi_device *sdev, u8 data); +int spmi_ext_register_write(struct spmi_device *sdev, u8 addr, + const u8 *buf, size_t len); +int spmi_ext_register_writel(struct spmi_device *sdev, u16 addr, + const u8 *buf, size_t len); +int spmi_command_reset(struct spmi_device *sdev); +int spmi_command_sleep(struct spmi_device *sdev); +int spmi_command_wakeup(struct spmi_device *sdev); +int spmi_command_shutdown(struct spmi_device *sdev); + +#endif -- cgit v1.2.3 From c9afbb05a9ffbef0976242ab1135af6814ccff0f Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 12 Feb 2014 13:44:27 -0600 Subject: regmap: spmi: support base and extended register spaces SPMI states that a slave may contain two register spaces, the Base register space is a 5-bit byte-addressable space accessed via the Register Read/Write and Register Zero Write command sequences, and the Extended register space: a 16-bit byte-addressable space accessed via the Extended Read/Write and Extended Read/Write Long command sequences. Provide support for accessing both of these spaces, taking advantage of the more bandwidth-efficient commands ('Register 0 Write' vs 'Register Write', and 'Extended Register Read/Write' vs 'Extended Register Read/Write Long') when possible. Signed-off-by: Josh Cartwright Acked-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- include/linux/regmap.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 4149f1a9b003..8cc73ac6f888 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -321,8 +321,10 @@ struct regmap *regmap_init_i2c(struct i2c_client *i2c, const struct regmap_config *config); struct regmap *regmap_init_spi(struct spi_device *dev, const struct regmap_config *config); -struct regmap *regmap_init_spmi(struct spmi_device *dev, - const struct regmap_config *config); +struct regmap *regmap_init_spmi_base(struct spmi_device *dev, + const struct regmap_config *config); +struct regmap *regmap_init_spmi_ext(struct spmi_device *dev, + const struct regmap_config *config); struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id, void __iomem *regs, const struct regmap_config *config); @@ -335,8 +337,10 @@ struct regmap *devm_regmap_init_i2c(struct i2c_client *i2c, const struct regmap_config *config); struct regmap *devm_regmap_init_spi(struct spi_device *dev, const struct regmap_config *config); -struct regmap *devm_regmap_init_spmi(struct spmi_device *dev, - const struct regmap_config *config); +struct regmap *devm_regmap_init_spmi_base(struct spmi_device *dev, + const struct regmap_config *config); +struct regmap *devm_regmap_init_spmi_ext(struct spmi_device *dev, + const struct regmap_config *config); struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id, void __iomem *regs, const struct regmap_config *config); -- cgit v1.2.3 From 01325476d6e46185031be4a9bc6443832dbc807c Mon Sep 17 00:00:00 2001 From: "K. Y. Srinivasan" Date: Sun, 16 Feb 2014 11:34:30 -0800 Subject: Drivers: hv: Implement the file copy service Implement the file copy service for Linux guests on Hyper-V. This permits the host to copy a file (over VMBUS) into the guest. This facility is part of "guest integration services" supported on the Windows platform. Here is a link that provides additional details on this functionality: http://technet.microsoft.com/en-us/library/dn464282.aspx In V1 version of the patch I have addressed comments from Olaf Hering and Dan Carpenter In V2 version of this patch I did some minor cleanup (making some globals static). In V4 version of the patch I have addressed all of Olaf's most recent set of comments/concerns. In V5 version of the patch I had addressed Greg's most recent comments. I would like to thank Greg for suggesting that I use misc device; it has significantly simplified the code. In V6 version of the patch I have cleaned up error message based on Olaf's comments. I have also rebased the patch based on the current tip. In this version of the patch, I have addressed the latest comments from Greg. Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index fb66fba368d7..62ea1a06836a 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -1049,6 +1048,17 @@ void vmbus_driver_unregister(struct hv_driver *hv_driver); 0xB7, 0x6B, 0x6F, 0xD0, 0xBE, 0x52, 0x8C, 0xDA \ } +/* + * Guest File Copy Service + * {34D14BE3-DEE4-41c8-9AE7-6B174977C192} + */ + +#define HV_FCOPY_GUID \ + .guid = { \ + 0xE3, 0x4B, 0xD1, 0x34, 0xE4, 0xDE, 0xC8, 0x41, \ + 0x9A, 0xE7, 0x6B, 0x17, 0x49, 0x77, 0xC1, 0x92 \ + } + /* * Common header for Hyper-V ICs */ -- cgit v1.2.3 From 3503958cb0a5f183ddbdafe0f352607920cd8668 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Tue, 18 Feb 2014 02:27:24 -0300 Subject: misc: add comment on unused minors Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman --- include/linux/miscdevice.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h index 3737f7218f51..2cf1547096d9 100644 --- a/include/linux/miscdevice.h +++ b/include/linux/miscdevice.h @@ -11,23 +11,23 @@ */ #define PSMOUSE_MINOR 1 -#define MS_BUSMOUSE_MINOR 2 -#define ATIXL_BUSMOUSE_MINOR 3 +#define MS_BUSMOUSE_MINOR 2 /* unused */ +#define ATIXL_BUSMOUSE_MINOR 3 /* unused */ /*#define AMIGAMOUSE_MINOR 4 FIXME OBSOLETE */ -#define ATARIMOUSE_MINOR 5 -#define SUN_MOUSE_MINOR 6 -#define APOLLO_MOUSE_MINOR 7 -#define PC110PAD_MINOR 9 +#define ATARIMOUSE_MINOR 5 /* unused */ +#define SUN_MOUSE_MINOR 6 /* unused */ +#define APOLLO_MOUSE_MINOR 7 /* unused */ +#define PC110PAD_MINOR 9 /* unused */ /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ #define WATCHDOG_MINOR 130 /* Watchdog timer */ #define TEMP_MINOR 131 /* Temperature Sensor */ #define RTC_MINOR 135 #define EFI_RTC_MINOR 136 /* EFI Time services */ #define SUN_OPENPROM_MINOR 139 -#define DMAPI_MINOR 140 /* DMAPI */ +#define DMAPI_MINOR 140 /* unused */ #define NVRAM_MINOR 144 #define SGI_MMTIMER 153 -#define STORE_QUEUE_MINOR 155 +#define STORE_QUEUE_MINOR 155 /* unused */ #define I2O_MINOR 166 #define MICROCODE_MINOR 184 #define VFIO_MINOR 196 -- cgit v1.2.3 From d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 17 Jan 2014 11:15:16 +0530 Subject: driver/memory:Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/memory and fix the header file includes. Also remove module_platform_driver() and instead call platform_driver_register() from subsys_initcall() to make sure this module has been loaded before MTD partition parsing starts. Signed-off-by: Prabhakar Kushwaha Acked-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- include/linux/fsl_ifc.h | 838 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 838 insertions(+) create mode 100644 include/linux/fsl_ifc.h (limited to 'include/linux') diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h new file mode 100644 index 000000000000..f49ddb1b2273 --- /dev/null +++ b/include/linux/fsl_ifc.h @@ -0,0 +1,838 @@ +/* Freescale Integrated Flash Controller + * + * Copyright 2011 Freescale Semiconductor, Inc + * + * Author: Dipen Dudhat + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_FSL_IFC_H +#define __ASM_FSL_IFC_H + +#include +#include +#include + +#include +#include + +#define FSL_IFC_BANK_COUNT 4 + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +#define CSOR_NAND_ECC_MODE_MASK 0x30000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ERAID_SHIFT 20 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 +#define IFC_CM_ERATTR0_ESRCID_SHIFT 8 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Chip Select Register (NAND_CSEL) + */ +#define IFC_NAND_CSEL 0x0C000000 +#define IFC_NAND_CSEL_SHIFT 26 +#define IFC_NAND_CSEL_CS0 0x00000000 +#define IFC_NAND_CSEL_CS1 0x04000000 +#define IFC_NAND_CSEL_CS2 0x08000000 +#define IFC_NAND_CSEL_CS3 0x0C000000 + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + __be32 ncfgr; + u32 res1[0x4]; + __be32 nand_fcr0; + __be32 nand_fcr1; + u32 res2[0x8]; + __be32 row0; + u32 res3; + __be32 col0; + u32 res4; + __be32 row1; + u32 res5; + __be32 col1; + u32 res6; + __be32 row2; + u32 res7; + __be32 col2; + u32 res8; + __be32 row3; + u32 res9; + __be32 col3; + u32 res10[0x24]; + __be32 nand_fbcr; + u32 res11; + __be32 nand_fir0; + __be32 nand_fir1; + __be32 nand_fir2; + u32 res12[0x10]; + __be32 nand_csel; + u32 res13; + __be32 nandseq_strt; + u32 res14; + __be32 nand_evter_stat; + u32 res15; + __be32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + __be32 nand_evter_en; + u32 res17[0x2]; + __be32 nand_evter_intr_en; + u32 res18[0x2]; + __be32 nand_erattr0; + __be32 nand_erattr1; + u32 res19[0x10]; + __be32 nand_fsr; + u32 res20; + __be32 nand_eccstat[4]; + u32 res21[0x20]; + __be32 nanndcr; + u32 res22[0x2]; + __be32 nand_autoboot_trgr; + u32 res23; + __be32 nand_mdr; + u32 res24[0x5C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + __be32 nor_evter_stat; + u32 res1[0x2]; + __be32 nor_evter_en; + u32 res2[0x2]; + __be32 nor_evter_intr_en; + u32 res3[0x2]; + __be32 nor_erattr0; + __be32 nor_erattr1; + __be32 nor_erattr2; + u32 res4[0x4]; + __be32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + __be32 gpcm_evter_stat; + u32 res1[0x2]; + __be32 gpcm_evter_en; + u32 res2[0x2]; + __be32 gpcm_evter_intr_en; + u32 res3[0x2]; + __be32 gpcm_erattr0; + __be32 gpcm_erattr1; + __be32 gpcm_erattr2; + __be32 gpcm_stat; + u32 res4[0x1F3]; +}; + +/* + * IFC Controller Registers + */ +struct fsl_ifc_regs { + __be32 ifc_rev; + u32 res1[0x2]; + struct { + __be32 cspr_ext; + __be32 cspr; + u32 res2; + } cspr_cs[FSL_IFC_BANK_COUNT]; + u32 res3[0x19]; + struct { + __be32 amask; + u32 res4[0x2]; + } amask_cs[FSL_IFC_BANK_COUNT]; + u32 res5[0x17]; + struct { + __be32 csor_ext; + __be32 csor; + u32 res6; + } csor_cs[FSL_IFC_BANK_COUNT]; + u32 res7[0x19]; + struct { + __be32 ftim[4]; + u32 res8[0x8]; + } ftim_cs[FSL_IFC_BANK_COUNT]; + u32 res9[0x60]; + __be32 rb_stat; + u32 res10[0x2]; + __be32 ifc_gcr; + u32 res11[0x2]; + __be32 cm_evter_stat; + u32 res12[0x2]; + __be32 cm_evter_en; + u32 res13[0x2]; + __be32 cm_evter_intr_en; + u32 res14[0x2]; + __be32 cm_erattr0; + __be32 cm_erattr1; + u32 res15[0x2]; + __be32 ifc_ccr; + __be32 ifc_csr; + u32 res16[0x2EB]; + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +extern unsigned int convert_ifc_address(phys_addr_t addr_base); +extern int fsl_ifc_find(phys_addr_t addr_base); + +/* overview of the fsl ifc controller */ + +struct fsl_ifc_ctrl { + /* device info */ + struct device *dev; + struct fsl_ifc_regs __iomem *regs; + int irq; + int nand_irq; + spinlock_t lock; + void *nand; + + u32 nand_stat; + wait_queue_head_t nand_wait; +}; + +extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; + + +#endif /* __ASM_FSL_IFC_H */ -- cgit v1.2.3 From 90eedf0cbe4ba2a316633d6547d331c8b30517e7 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 24 Feb 2014 14:17:09 +0100 Subject: vmbus: use resource for hyperv mmio region Use a resource for the hyperv mmio region instead of start/size variables. Register the region properly so it shows up in /proc/iomem. Signed-off-by: Gerd Hoffmann Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 62ea1a06836a..330ec44de575 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -1167,8 +1167,7 @@ int hv_vss_init(struct hv_util_service *); void hv_vss_deinit(void); void hv_vss_onchannelcallback(void *); -extern u64 hyperv_mmio_start; -extern u64 hyperv_mmio_size; +extern struct resource hyperv_mmio; /* * Negotiated version with the Host. -- cgit v1.2.3 From 2e70efd9afab7a512b6e2e164bf5c25fd3ce6aae Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sat, 22 Feb 2014 09:11:24 +0100 Subject: FMC: show_sdb_tree: dump synthesis/commit ID info This completes the show_sdb_tree functionality, with the new informative fields. The output for a verbose module is now like this (long lines are unavoidable): SDB: 00000651:e6a542c9 WB4-Crossbar-GSI SDB: 0000ce42:00000601 WB-DMA.Control (00001000-0000103f) SDB: 0000ce42:779c5443 WB-OneWire-Master (00001100-000011ff) SDB: 0000ce42:00000603 WB-SPEC-CSR (00001200-0000121f) SDB: 0000ce42:00000013 WB-VIC-Int.Control (00001300-000013ff) SDB: 0000ce42:d5735ab4 WB-DMA.EIC (00001400-0000140f) SDB: 00000651:eef0b198 WB4-Bridge-GSI (bridge: 00002000) SDB: 00000651:e6a542c9 WB4-Crossbar-GSI SDB: 0000ce42:123c5443 WB-I2C-Master (00003000-000030ff) SDB: 0000ce42:e503947e WB-SPI.Control (00003100-0000311f) SDB: 0000ce42:123c5443 WB-I2C-Master (00003200-000032ff) SDB: 0000ce42:00000608 WB-FMC-ADC-Core (00003300-0000337f) SDB: 0000ce42:779c5443 WB-OneWire-Master (00003400-000034ff) SDB: 0000ce42:26ec6086 WB-FMC-ADC.EIC (00003500-0000350f) SDB: 0000ce42:00000604 WB-Timetag-Core (00003600-0000367f) SDB: Synthesis repository: git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git SDB: Bitstream 'spec_top_fmc_adcmc-projects/fmc-adc-100m14b4cha.git' \ synthesized 20140116 by mcattin (ISE version 133), commit f0a539dffe6d Signed-off-by: Tomasz Wlostowski Acked-by: Alessandro Rubini Acked-by: Juan David Gonzalez Cobas Signed-off-by: Greg Kroah-Hartman --- include/linux/fmc-sdb.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux') diff --git a/include/linux/fmc-sdb.h b/include/linux/fmc-sdb.h index 1974317a9b3d..599bd6bab56d 100644 --- a/include/linux/fmc-sdb.h +++ b/include/linux/fmc-sdb.h @@ -14,6 +14,8 @@ union sdb_record { struct sdb_bridge bridge; struct sdb_integration integr; struct sdb_empty empty; + struct sdb_synthesis synthesis; + struct sdb_repo_url repo_url; }; struct fmc_device; -- cgit v1.2.3 From 3764e82e5150d87b205c10cd78a9c9ab86fbfa51 Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Wed, 26 Feb 2014 17:29:05 +0100 Subject: drivers: Introduce MEN Chameleon Bus The MCB (MEN Chameleon Bus) is a Bus specific to MEN Mikroelektronik FPGA based devices. It is used to identify MCB based IP-Cores within an FPGA and provide the necessary framework for instantiating drivers for these devices. Signed-off-by: Johannes Thumshirn Signed-off-by: Greg Kroah-Hartman --- include/linux/mcb.h | 119 ++++++++++++++++++++++++++++++++++++++++ include/linux/mod_devicetable.h | 5 ++ 2 files changed, 124 insertions(+) create mode 100644 include/linux/mcb.h (limited to 'include/linux') diff --git a/include/linux/mcb.h b/include/linux/mcb.h new file mode 100644 index 000000000000..2db284d14064 --- /dev/null +++ b/include/linux/mcb.h @@ -0,0 +1,119 @@ +/* + * MEN Chameleon Bus. + * + * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de) + * Author: Johannes Thumshirn + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; version 2 of the License. + */ +#ifndef _LINUX_MCB_H +#define _LINUX_MCB_H + +#include +#include +#include + +struct mcb_driver; + +/** + * struct mcb_bus - MEN Chameleon Bus + * + * @dev: pointer to carrier device + * @children: the child busses + * @bus_nr: mcb bus number + */ +struct mcb_bus { + struct list_head children; + struct device dev; + int bus_nr; +}; +#define to_mcb_bus(b) container_of((b), struct mcb_bus, dev) + +/** + * struct mcb_device - MEN Chameleon Bus device + * + * @bus_list: internal list handling for bus code + * @dev: device in kernel representation + * @bus: mcb bus the device is plugged to + * @subordinate: subordinate MCBus in case of bridge + * @is_added: flag to check if device is added to bus + * @driver: associated mcb_driver + * @id: mcb device id + * @inst: instance in Chameleon table + * @group: group in Chameleon table + * @var: variant in Chameleon table + * @bar: BAR in Chameleon table + * @rev: revision in Chameleon table + * @irq: IRQ resource + * @memory: memory resource + */ +struct mcb_device { + struct list_head bus_list; + struct device dev; + struct mcb_bus *bus; + struct mcb_bus *subordinate; + bool is_added; + struct mcb_driver *driver; + u16 id; + int inst; + int group; + int var; + int bar; + int rev; + struct resource irq; + struct resource mem; +}; +#define to_mcb_device(x) container_of((x), struct mcb_device, dev) + +/** + * struct mcb_driver - MEN Chameleon Bus device driver + * + * @driver: device_driver + * @id_table: mcb id table + * @probe: probe callback + * @remove: remove callback + * @shutdown: shutdown callback + */ +struct mcb_driver { + struct device_driver driver; + const struct mcb_device_id *id_table; + int (*probe)(struct mcb_device *mdev, const struct mcb_device_id *id); + void (*remove)(struct mcb_device *mdev); + void (*shutdown)(struct mcb_device *mdev); +}; +#define to_mcb_driver(x) container_of((x), struct mcb_driver, driver) + +static inline void *mcb_get_drvdata(struct mcb_device *dev) +{ + return dev_get_drvdata(&dev->dev); +} + +static inline void mcb_set_drvdata(struct mcb_device *dev, void *data) +{ + dev_set_drvdata(&dev->dev, data); +} + +extern int __must_check __mcb_register_driver(struct mcb_driver *drv, + struct module *owner, + const char *mod_name); +#define mcb_register_driver(driver) \ + __mcb_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) +extern void mcb_unregister_driver(struct mcb_driver *driver); +#define module_mcb_driver(__mcb_driver) \ + module_driver(__mcb_driver, mcb_register_driver, mcb_unregister_driver); +extern void mcb_bus_add_devices(const struct mcb_bus *bus); +extern int mcb_device_register(struct mcb_bus *bus, struct mcb_device *dev); +extern struct mcb_bus *mcb_alloc_bus(void); +extern struct mcb_bus *mcb_bus_get(struct mcb_bus *bus); +extern void mcb_bus_put(struct mcb_bus *bus); +extern struct mcb_device *mcb_alloc_dev(struct mcb_bus *bus); +extern void mcb_free_dev(struct mcb_device *dev); +extern void mcb_release_bus(struct mcb_bus *bus); +extern struct resource *mcb_request_mem(struct mcb_device *dev, + const char *name); +extern void mcb_release_mem(struct resource *mem); +extern int mcb_get_irq(struct mcb_device *dev); + +#endif /* _LINUX_MCB_H */ diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 677e474fc273..50f67eff27ef 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -607,4 +607,9 @@ struct rio_device_id { __u16 asm_did, asm_vid; }; +struct mcb_device_id { + __u16 device; + kernel_ulong_t driver_data; +}; + #endif /* LINUX_MOD_DEVICETABLE_H */ -- cgit v1.2.3 From 7e5ec36834a5752304dc0751dfab42ba6ad64a85 Mon Sep 17 00:00:00 2001 From: "K. Y. Srinivasan" Date: Fri, 7 Mar 2014 00:10:34 -0800 Subject: Drivers: hv: vmbus: Increase the limit on the number of pfns we can handle Increase the number of PFNs we can handle in a single vmbus packet. Some network packets may have more PFNs than the current limit we have. This is not a bug and this patch can be applied to the *next tree. Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- include/linux/hyperv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 330ec44de575..ab7359fde987 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -37,7 +37,7 @@ #include -#define MAX_PAGE_BUFFER_COUNT 19 +#define MAX_PAGE_BUFFER_COUNT 32 #define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */ #pragma pack(push, 1) -- cgit v1.2.3 From 1ad94ffef22c0a6e2ee6ba90a800c32fd29ffa1f Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Tue, 18 Mar 2014 19:55:46 +0900 Subject: extcon: Move OF helper function to extcon core and change function name This patch move simply OF helper function to extcon core and change function name as following: - of_extcon_get_extcon_dev() -> extcon_get_edev_by_phandle() Signed-off-by: Chanwoo Choi Acked-by: Felipe Balbi --- include/linux/extcon.h | 12 ++++++++++++ include/linux/extcon/of_extcon.h | 31 ------------------------------- 2 files changed, 12 insertions(+), 31 deletions(-) delete mode 100644 include/linux/extcon/of_extcon.h (limited to 'include/linux') diff --git a/include/linux/extcon.h b/include/linux/extcon.h index 21c59af1150b..f488145bb2d4 100644 --- a/include/linux/extcon.h +++ b/include/linux/extcon.h @@ -240,6 +240,12 @@ extern int extcon_register_notifier(struct extcon_dev *edev, struct notifier_block *nb); extern int extcon_unregister_notifier(struct extcon_dev *edev, struct notifier_block *nb); + +/* + * Following API get the extcon device from devicetree. + * This function use phandle of devicetree to get extcon device directly. + */ +extern struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index); #else /* CONFIG_EXTCON */ static inline int extcon_dev_register(struct extcon_dev *edev) { @@ -324,5 +330,11 @@ static inline int extcon_unregister_interest(struct extcon_specific_cable_nb { return 0; } + +static inline struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, + int index) +{ + return ERR_PTR(-ENODEV); +} #endif /* CONFIG_EXTCON */ #endif /* __LINUX_EXTCON_H__ */ diff --git a/include/linux/extcon/of_extcon.h b/include/linux/extcon/of_extcon.h deleted file mode 100644 index 0ebfeff1b55d..000000000000 --- a/include/linux/extcon/of_extcon.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * OF helpers for External connector (extcon) framework - * - * Copyright (C) 2013 Texas Instruments, Inc. - * Kishon Vijay Abraham I - * - * Copyright (C) 2013 Samsung Electronics - * Chanwoo Choi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __LINUX_OF_EXTCON_H -#define __LINUX_OF_EXTCON_H - -#include - -#if IS_ENABLED(CONFIG_OF_EXTCON) -extern struct extcon_dev - *of_extcon_get_extcon_dev(struct device *dev, int index); -#else -static inline struct extcon_dev - *of_extcon_get_extcon_dev(struct device *dev, int index) -{ - return ERR_PTR(-ENOSYS); -} -#endif /* CONFIG_OF_EXTCON */ -#endif /* __LINUX_OF_EXTCON_H */ -- cgit v1.2.3