From fc0b2acc754a183aa79e2abb8bca8fd915832694 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Tue, 30 May 2017 17:31:21 +0300 Subject: spi: pxa2xx: Add support for Intel Cannonlake Intel Cannonlake LPSS SPI has up to four chip selects per port like in Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type LPSS_CNL_SSP and configuration that enable runtime chip select detection and use the same FIFO thresholds than in Sunrisepoint. Patch adds support for both Cannonlake SoC and PCH. Signed-off-by: Jarkko Nikula Signed-off-by: Mark Brown --- include/linux/pxa2xx_ssp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index a0522328d7aa..8461b18e4608 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -196,6 +196,7 @@ enum pxa_ssp_type { LPSS_BSW_SSP, LPSS_SPT_SSP, LPSS_BXT_SSP, + LPSS_CNL_SSP, }; struct ssp_device { -- cgit v1.2.3