From d9bb3fb12685209765fd838bec69d701d7b479e5 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Fri, 4 Apr 2014 17:23:43 -0700 Subject: tty: xuartps: Rebrand driver as Cadence UART Zynq's UART is Cadence IP. Make this visible in the prompt in kconfig and additional comments in the driver. This also renames functions and symbols, as far as possible without breaking user space API, to reflect the Cadence origin. This is achieved through simple search and replace: - s/XUARTPS/CDNS_UART/g - s/xuartps/cdns_uart/g The only exceptions are PORT_XUARTPS and the driver name, which stay as is, due to their exposure to user space. As well as the - no legacy - compatibility string 'xlnx,xuartps' Signed-off-by: Soren Brinkmann Tested-by: Michal Simek Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/serial_core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/uapi/linux/serial_core.h') diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index b47dba2c1e6f..22aaf8ed7735 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -211,7 +211,7 @@ /* VIA VT8500 SoC */ #define PORT_VT8500 97 -/* Xilinx PSS UART */ +/* Cadence (Xilinx Zynq) UART */ #define PORT_XUARTPS 98 /* Atheros AR933X SoC */ -- cgit v1.2.3 From e264ebf4c81ac733642ed03ee3f0e26914ed3714 Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Thu, 17 Apr 2014 15:47:58 +0200 Subject: tty: serial: Add driver for MEN's 16z135 High Speed UART. Add driver for MEN's 16z135 High Speed UART. The 16z135 is a memory mapped UART Core on an MCB FPGA and has 1024 byte deep FIFO buffers for the RX and TX path. It also has configurable FIFO fill level IRQs and data copied to and from the hardware has to be acknowledged. Signed-off-by: Johannes Thumshirn Reviewed-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/serial_core.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/uapi/linux/serial_core.h') diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 22aaf8ed7735..6e293622851a 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -238,4 +238,7 @@ /* Tilera TILE-Gx UART */ #define PORT_TILEGX 106 +/* MEN 16z135 UART */ +#define PORT_MEN_Z135 107 + #endif /* _UAPILINUX_SERIAL_CORE_H */ -- cgit v1.2.3 From dfeae619d781dee61666d5551b93ba3be755a86b Mon Sep 17 00:00:00 2001 From: Jon Ringle Date: Thu, 24 Apr 2014 20:56:06 -0400 Subject: serial: sc16is7xx The SC16IS7xx is a slave I2C-bus/SPI interface to a single-channel high performance UART. The SC16IS7xx's internal register set is backward-compatible with the widely used and widely popular 16C450. The SC16IS7xx also provides additional advanced features such as auto hardware and software flow control, automatic RS-485 support, and software reset. Signed-off-by: Jon Ringle Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/serial_core.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/uapi/linux/serial_core.h') diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 6e293622851a..5820269aa132 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -241,4 +241,7 @@ /* MEN 16z135 UART */ #define PORT_MEN_Z135 107 +/* SC16IS74xx */ +#define PORT_SC16IS7XX 108 + #endif /* _UAPILINUX_SERIAL_CORE_H */ -- cgit v1.2.3