From b5e10df665e756c2c68442177e460d90bb9cf979 Mon Sep 17 00:00:00 2001 From: Robert Reif Date: Sun, 11 May 2008 15:47:05 -0700 Subject: sparc32: Fix build. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix sparc32 build error due to undefined bool type. CC [M] fs/ocfs2/dlm/userdlm.o In file included from include/asm/sigcontext.h:6, from include/asm/signal.h:5, from include/linux/signal.h:4, from fs/ocfs2/dlm/userdlm.c:30: include/asm/ptrace.h:42: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘pt_regs_is_syscall’ include/asm/ptrace.h:47: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘pt_regs_clear_syscall’ make[3]: *** [fs/ocfs2/dlm/userdlm.o] Error 1 make[2]: *** [fs/ocfs2/dlm] Error 2 make[1]: *** [fs/ocfs2] Error 2 make: *** [fs] Error 2 Signed-off-by: Robert Reif Signed-off-by: David S. Miller --- include/asm-sparc/ptrace.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-sparc/ptrace.h b/include/asm-sparc/ptrace.h index 6b5e6ce5043c..0afb867d6c1b 100644 --- a/include/asm-sparc/ptrace.h +++ b/include/asm-sparc/ptrace.h @@ -10,6 +10,8 @@ #ifndef __ASSEMBLY__ +#include + struct pt_regs { unsigned long psr; unsigned long pc; -- cgit v1.2.3 From 4951704b4e23d71b99ac933d8e6993bc6225ac13 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 12 May 2008 03:29:11 -0700 Subject: syncppp: Fix crashes. The syncppp layer wants a mid-level netdev private pointer. It was using netdev->priv but that only worked by accident, and thus this scheme was broken when the device private allocation strategy changed. Add a proper mid-layer private pointer for uses like this, update syncppp and all users, and remove the HDLC_PPP broken tag from drivers/net/wan/Kconfig Signed-off-by: David S. Miller --- include/linux/netdevice.h | 3 +++ include/net/syncppp.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 7c1d4466583b..746901774d49 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -715,6 +715,9 @@ struct net_device struct net *nd_net; #endif + /* mid-layer private */ + void *ml_priv; + /* bridge stuff */ struct net_bridge_port *br_port; /* macvlan */ diff --git a/include/net/syncppp.h b/include/net/syncppp.h index 877efa434700..e43f4070d892 100644 --- a/include/net/syncppp.h +++ b/include/net/syncppp.h @@ -59,7 +59,7 @@ struct ppp_device static inline struct sppp *sppp_of(struct net_device *dev) { - struct ppp_device **ppp = dev->priv; + struct ppp_device **ppp = dev->ml_priv; BUG_ON((*ppp)->dev != dev); return &(*ppp)->sppp; } -- cgit v1.2.3 From 0d4b6b901c3d41beb0e1620316aee0aa234edf7f Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 12 May 2008 22:57:51 +1000 Subject: [POWERPC] ppc: More compile fixes This fixes a few more miscellaneous compile problems with ARCH=ppc. 1. Don't compile devres.c on ARCH=ppc, it doesn't have ioremap_flags. 2. Include in setup.c for the __DO_IRQ_CANON definition. 3. Include in residual.c for the definition of create_proc_read_entry. 4. Fix xchg_ptr to be a static inline to eliminate a compiler warning. Signed-off-by: Paul Mackerras --- include/asm-ppc/system.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index 0593cb889d45..70ebd333c55b 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -178,7 +178,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size } -extern inline void * xchg_ptr(void * m, void * val) +static inline void * xchg_ptr(void * m, void * val) { return (void *) xchg_u32(m, (unsigned long) val); } -- cgit v1.2.3 From 1928cc84a0a937ce7042d9235996ab380f36f18a Mon Sep 17 00:00:00 2001 From: "Kevin D. Kissell" Date: Wed, 16 Apr 2008 15:32:22 +0200 Subject: [MIPS] MT: Functional fixes and a little reformatting of APRP support Signed-off-by: Kevin D. Kissell Signed-off-by: Ralf Baechle --- include/asm-mips/rtlx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h index 65778c890a62..20b666022dcb 100644 --- a/include/asm-mips/rtlx.h +++ b/include/asm-mips/rtlx.h @@ -29,13 +29,13 @@ extern unsigned int rtlx_read_poll(int index, int can_sleep); extern unsigned int rtlx_write_poll(int index); enum rtlx_state { - RTLX_STATE_UNUSED, + RTLX_STATE_UNUSED = 0, RTLX_STATE_INITIALISED, RTLX_STATE_REMOTE_READY, RTLX_STATE_OPENED }; -#define RTLX_BUFFER_SIZE 1024 +#define RTLX_BUFFER_SIZE 2048 /* each channel supports read and write. linux (vpe0) reads lx_buffer and writes rt_buffer -- cgit v1.2.3 From ad1d77a38575644b112340fd9115ac21dd533166 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 1 May 2008 15:28:53 +0100 Subject: [MIPS] Add empty argument parenthesis to GCC_IMM_ASM This is to clarify that GCC_IMM_ASM does not take an argument as the context of the macro's invocation seems to imply. As suggested by Maciej W. Rozycki (macro@linux-mips.org). Signed-off-by: Ralf Baechle --- include/asm-mips/compiler.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h index aa6b876bbd78..71f5c5cfc58a 100644 --- a/include/asm-mips/compiler.h +++ b/include/asm-mips/compiler.h @@ -9,10 +9,10 @@ #define _ASM_COMPILER_H #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) -#define GCC_IMM_ASM "n" +#define GCC_IMM_ASM() "n" #define GCC_REG_ACCUM "$0" #else -#define GCC_IMM_ASM "rn" +#define GCC_IMM_ASM() "rn" #define GCC_REG_ACCUM "accum" #endif -- cgit v1.2.3 From ff6814d53016081947ff4021e00db3f806a561c9 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:18:35 +0400 Subject: [MIPS] Alchemy common headers style cleanup Fix several errors and warnings given by checkpatch.pl: - space after opening and before closing parentheses; - opening brace following 'struct' not on the same line; - leading spaces instead of tabs; - use of C99 // comments; - macros with complex values not enclosed in parentheses; - missing space between the type and asterisk in a variable declaration; - space between asterisk and function name; - including instead of and instead of ; - use of '__inline__' instead of 'inline'; - space between function name and opening parenthesis; - line over 80 characters. In addition to these changes, also do the following: - remove needless parentheses; - insert spaces between operator and its operands; - replace spaces after the macro name with tabs in the #define directives and after the type in the structure field declarations; - remove excess tabs after the macro name in the #define directives and in the 'extern' variable declarations; - remove excess spaces between # and define for the SSI_*_MASK macros to align with other such macros; - put '||' operator on the same line with its first operand; - properly indent multi-line function prototypes; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line and/or adding space/asterisk on their left side; - make two-line comments that only have one line of text one-line; - convert the large multi-line comment in au1xxx_ide.h into several one-liners, replace spaces with tabs there; - fix typos/errors, capitalize acronyms, etc. in the comments; - insert missing and remove excess new lines; - update MontaVista copyright; - remove Pete Popov's and Steve Longerbeam's old email addresses... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1000.h | 1644 +++++++++++++-------------- include/asm-mips/mach-au1x00/au1000_dma.h | 179 +-- include/asm-mips/mach-au1x00/au1000_gpio.h | 18 +- include/asm-mips/mach-au1x00/au1550_spi.h | 2 +- include/asm-mips/mach-au1x00/au1xxx.h | 4 +- include/asm-mips/mach-au1x00/au1xxx_dbdma.h | 155 ++- include/asm-mips/mach-au1x00/au1xxx_ide.h | 251 ++-- include/asm-mips/mach-au1x00/au1xxx_psc.h | 131 +-- 8 files changed, 1175 insertions(+), 1209 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index a05555165d05..363a14ee0ae5 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -40,8 +40,8 @@ #include #include -#include -#include +#include +#include /* cpu pipeline flush */ void static inline au_sync(void) @@ -63,32 +63,32 @@ void static inline au_sync_delay(int ms) void static inline au_writeb(u8 val, unsigned long reg) { - *(volatile u8 *)(reg) = val; + *(volatile u8 *)reg = val; } void static inline au_writew(u16 val, unsigned long reg) { - *(volatile u16 *)(reg) = val; + *(volatile u16 *)reg = val; } void static inline au_writel(u32 val, unsigned long reg) { - *(volatile u32 *)(reg) = val; + *(volatile u32 *)reg = val; } static inline u8 au_readb(unsigned long reg) { - return (*(volatile u8 *)reg); + return *(volatile u8 *)reg; } static inline u16 au_readw(unsigned long reg) { - return (*(volatile u16 *)reg); + return *(volatile u16 *)reg; } static inline u32 au_readl(unsigned long reg) { - return (*(volatile u32 *)reg); + return *(volatile u32 *)reg; } @@ -117,76 +117,77 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ /* - * SDRAM Register Offsets + * SDRAM register offsets */ -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) -#define MEM_SDMODE0 (0x0000) -#define MEM_SDMODE1 (0x0004) -#define MEM_SDMODE2 (0x0008) -#define MEM_SDADDR0 (0x000C) -#define MEM_SDADDR1 (0x0010) -#define MEM_SDADDR2 (0x0014) -#define MEM_SDREFCFG (0x0018) -#define MEM_SDPRECMD (0x001C) -#define MEM_SDAUTOREF (0x0020) -#define MEM_SDWRMD0 (0x0024) -#define MEM_SDWRMD1 (0x0028) -#define MEM_SDWRMD2 (0x002C) -#define MEM_SDSLEEP (0x0030) -#define MEM_SDSMCKE (0x0034) +#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ + defined(CONFIG_SOC_AU1100) +#define MEM_SDMODE0 0x0000 +#define MEM_SDMODE1 0x0004 +#define MEM_SDMODE2 0x0008 +#define MEM_SDADDR0 0x000C +#define MEM_SDADDR1 0x0010 +#define MEM_SDADDR2 0x0014 +#define MEM_SDREFCFG 0x0018 +#define MEM_SDPRECMD 0x001C +#define MEM_SDAUTOREF 0x0020 +#define MEM_SDWRMD0 0x0024 +#define MEM_SDWRMD1 0x0028 +#define MEM_SDWRMD2 0x002C +#define MEM_SDSLEEP 0x0030 +#define MEM_SDSMCKE 0x0034 /* * MEM_SDMODE register content definitions */ -#define MEM_SDMODE_F (1<<22) -#define MEM_SDMODE_SR (1<<21) -#define MEM_SDMODE_BS (1<<20) -#define MEM_SDMODE_RS (3<<18) -#define MEM_SDMODE_CS (7<<15) -#define MEM_SDMODE_TRAS (15<<11) -#define MEM_SDMODE_TMRD (3<<9) -#define MEM_SDMODE_TWR (3<<7) -#define MEM_SDMODE_TRP (3<<5) -#define MEM_SDMODE_TRCD (3<<3) -#define MEM_SDMODE_TCL (7<<0) - -#define MEM_SDMODE_BS_2Bank (0<<20) -#define MEM_SDMODE_BS_4Bank (1<<20) -#define MEM_SDMODE_RS_11Row (0<<18) -#define MEM_SDMODE_RS_12Row (1<<18) -#define MEM_SDMODE_RS_13Row (2<<18) -#define MEM_SDMODE_RS_N(N) ((N)<<18) -#define MEM_SDMODE_CS_7Col (0<<15) -#define MEM_SDMODE_CS_8Col (1<<15) -#define MEM_SDMODE_CS_9Col (2<<15) -#define MEM_SDMODE_CS_10Col (3<<15) -#define MEM_SDMODE_CS_11Col (4<<15) -#define MEM_SDMODE_CS_N(N) ((N)<<15) -#define MEM_SDMODE_TRAS_N(N) ((N)<<11) -#define MEM_SDMODE_TMRD_N(N) ((N)<<9) -#define MEM_SDMODE_TWR_N(N) ((N)<<7) -#define MEM_SDMODE_TRP_N(N) ((N)<<5) -#define MEM_SDMODE_TRCD_N(N) ((N)<<3) -#define MEM_SDMODE_TCL_N(N) ((N)<<0) +#define MEM_SDMODE_F (1 << 22) +#define MEM_SDMODE_SR (1 << 21) +#define MEM_SDMODE_BS (1 << 20) +#define MEM_SDMODE_RS (3 << 18) +#define MEM_SDMODE_CS (7 << 15) +#define MEM_SDMODE_TRAS (15 << 11) +#define MEM_SDMODE_TMRD (3 << 9) +#define MEM_SDMODE_TWR (3 << 7) +#define MEM_SDMODE_TRP (3 << 5) +#define MEM_SDMODE_TRCD (3 << 3) +#define MEM_SDMODE_TCL (7 << 0) + +#define MEM_SDMODE_BS_2Bank (0 << 20) +#define MEM_SDMODE_BS_4Bank (1 << 20) +#define MEM_SDMODE_RS_11Row (0 << 18) +#define MEM_SDMODE_RS_12Row (1 << 18) +#define MEM_SDMODE_RS_13Row (2 << 18) +#define MEM_SDMODE_RS_N(N) ((N) << 18) +#define MEM_SDMODE_CS_7Col (0 << 15) +#define MEM_SDMODE_CS_8Col (1 << 15) +#define MEM_SDMODE_CS_9Col (2 << 15) +#define MEM_SDMODE_CS_10Col (3 << 15) +#define MEM_SDMODE_CS_11Col (4 << 15) +#define MEM_SDMODE_CS_N(N) ((N) << 15) +#define MEM_SDMODE_TRAS_N(N) ((N) << 11) +#define MEM_SDMODE_TMRD_N(N) ((N) << 9) +#define MEM_SDMODE_TWR_N(N) ((N) << 7) +#define MEM_SDMODE_TRP_N(N) ((N) << 5) +#define MEM_SDMODE_TRCD_N(N) ((N) << 3) +#define MEM_SDMODE_TCL_N(N) ((N) << 0) /* * MEM_SDADDR register contents definitions */ -#define MEM_SDADDR_E (1<<20) -#define MEM_SDADDR_CSBA (0x03FF<<10) -#define MEM_SDADDR_CSMASK (0x03FF<<0) -#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) -#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) +#define MEM_SDADDR_E (1 << 20) +#define MEM_SDADDR_CSBA (0x03FF << 10) +#define MEM_SDADDR_CSMASK (0x03FF << 0) +#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) /* * MEM_SDREFCFG register content definitions */ -#define MEM_SDREFCFG_TRC (15<<28) -#define MEM_SDREFCFG_TRPM (3<<26) -#define MEM_SDREFCFG_E (1<<25) -#define MEM_SDREFCFG_RE (0x1ffffff<<0) -#define MEM_SDREFCFG_TRC_N(N) ((N)<>2)&0x3) -#define MAC_TX_BUFF0_LEN 0x8 -#define MAC_TX_BUFF1_STATUS 0x10 -#define MAC_TX_BUFF1_ADDR 0x14 -#define MAC_TX_BUFF1_LEN 0x18 -#define MAC_TX_BUFF2_STATUS 0x20 -#define MAC_TX_BUFF2_ADDR 0x24 -#define MAC_TX_BUFF2_LEN 0x28 -#define MAC_TX_BUFF3_STATUS 0x30 -#define MAC_TX_BUFF3_ADDR 0x34 -#define MAC_TX_BUFF3_LEN 0x38 - -#define MAC0_RX_DMA_ADDR 0xB4004100 -#define MAC1_RX_DMA_ADDR 0xB4004300 +#define MAC_TX_BUFF0_STATUS 0x0 +# define TX_FRAME_ABORTED (1 << 0) +# define TX_JAB_TIMEOUT (1 << 1) +# define TX_NO_CARRIER (1 << 2) +# define TX_LOSS_CARRIER (1 << 3) +# define TX_EXC_DEF (1 << 4) +# define TX_LATE_COLL_ABORT (1 << 5) +# define TX_EXC_COLL (1 << 6) +# define TX_UNDERRUN (1 << 7) +# define TX_DEFERRED (1 << 8) +# define TX_LATE_COLL (1 << 9) +# define TX_COLL_CNT_MASK (0xF << 10) +# define TX_PKT_RETRY (1 << 31) +#define MAC_TX_BUFF0_ADDR 0x4 +# define TX_DMA_ENABLE (1 << 0) +# define TX_T_DONE (1 << 1) +# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) +#define MAC_TX_BUFF0_LEN 0x8 +#define MAC_TX_BUFF1_STATUS 0x10 +#define MAC_TX_BUFF1_ADDR 0x14 +#define MAC_TX_BUFF1_LEN 0x18 +#define MAC_TX_BUFF2_STATUS 0x20 +#define MAC_TX_BUFF2_ADDR 0x24 +#define MAC_TX_BUFF2_LEN 0x28 +#define MAC_TX_BUFF3_STATUS 0x30 +#define MAC_TX_BUFF3_ADDR 0x34 +#define MAC_TX_BUFF3_LEN 0x38 + +#define MAC0_RX_DMA_ADDR 0xB4004100 +#define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ -#define MAC_RX_BUFF0_STATUS 0x0 -# define RX_FRAME_LEN_MASK 0x3fff -# define RX_WDOG_TIMER (1<<14) -# define RX_RUNT (1<<15) -# define RX_OVERLEN (1<<16) -# define RX_COLL (1<<17) -# define RX_ETHER (1<<18) -# define RX_MII_ERROR (1<<19) -# define RX_DRIBBLING (1<<20) -# define RX_CRC_ERROR (1<<21) -# define RX_VLAN1 (1<<22) -# define RX_VLAN2 (1<<23) -# define RX_LEN_ERROR (1<<24) -# define RX_CNTRL_FRAME (1<<25) -# define RX_U_CNTRL_FRAME (1<<26) -# define RX_MCAST_FRAME (1<<27) -# define RX_BCAST_FRAME (1<<28) -# define RX_FILTER_FAIL (1<<29) -# define RX_PACKET_FILTER (1<<30) -# define RX_MISSED_FRAME (1<<31) +#define MAC_RX_BUFF0_STATUS 0x0 +# define RX_FRAME_LEN_MASK 0x3fff +# define RX_WDOG_TIMER (1 << 14) +# define RX_RUNT (1 << 15) +# define RX_OVERLEN (1 << 16) +# define RX_COLL (1 << 17) +# define RX_ETHER (1 << 18) +# define RX_MII_ERROR (1 << 19) +# define RX_DRIBBLING (1 << 20) +# define RX_CRC_ERROR (1 << 21) +# define RX_VLAN1 (1 << 22) +# define RX_VLAN2 (1 << 23) +# define RX_LEN_ERROR (1 << 24) +# define RX_CNTRL_FRAME (1 << 25) +# define RX_U_CNTRL_FRAME (1 << 26) +# define RX_MCAST_FRAME (1 << 27) +# define RX_BCAST_FRAME (1 << 28) +# define RX_FILTER_FAIL (1 << 29) +# define RX_PACKET_FILTER (1 << 30) +# define RX_MISSED_FRAME (1 << 31) # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ - RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ - RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) -#define MAC_RX_BUFF0_ADDR 0x4 -# define RX_DMA_ENABLE (1<<0) -# define RX_T_DONE (1<<1) -# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) -# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) -#define MAC_RX_BUFF1_STATUS 0x10 -#define MAC_RX_BUFF1_ADDR 0x14 -#define MAC_RX_BUFF2_STATUS 0x20 -#define MAC_RX_BUFF2_ADDR 0x24 -#define MAC_RX_BUFF3_STATUS 0x30 -#define MAC_RX_BUFF3_ADDR 0x34 - + RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ + RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) +#define MAC_RX_BUFF0_ADDR 0x4 +# define RX_DMA_ENABLE (1 << 0) +# define RX_T_DONE (1 << 1) +# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) +# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) +#define MAC_RX_BUFF1_STATUS 0x10 +#define MAC_RX_BUFF1_ADDR 0x14 +#define MAC_RX_BUFF2_STATUS 0x20 +#define MAC_RX_BUFF2_ADDR 0x24 +#define MAC_RX_BUFF3_STATUS 0x30 +#define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ -#define UART_BASE UART0_ADDR +#define UART_BASE UART0_ADDR #ifdef CONFIG_SOC_AU1200 -#define UART_DEBUG_BASE UART1_ADDR +#define UART_DEBUG_BASE UART1_ADDR #else -#define UART_DEBUG_BASE UART3_ADDR +#define UART_DEBUG_BASE UART3_ADDR #endif #define UART_RX 0 /* Receive buffer */ @@ -1294,341 +1293,337 @@ enum soc_au1200_ints { #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ - - /* SSIO */ -#define SSI0_STATUS 0xB1600000 -# define SSI_STATUS_BF (1<<4) -# define SSI_STATUS_OF (1<<3) -# define SSI_STATUS_UF (1<<2) -# define SSI_STATUS_D (1<<1) -# define SSI_STATUS_B (1<<0) -#define SSI0_INT 0xB1600004 -# define SSI_INT_OI (1<<3) -# define SSI_INT_UI (1<<2) -# define SSI_INT_DI (1<<1) -#define SSI0_INT_ENABLE 0xB1600008 -# define SSI_INTE_OIE (1<<3) -# define SSI_INTE_UIE (1<<2) -# define SSI_INTE_DIE (1<<1) -#define SSI0_CONFIG 0xB1600020 -# define SSI_CONFIG_AO (1<<24) -# define SSI_CONFIG_DO (1<<23) -# define SSI_CONFIG_ALEN_BIT 20 -# define SSI_CONFIG_ALEN_MASK (0x7<<20) -# define SSI_CONFIG_DLEN_BIT 16 -# define SSI_CONFIG_DLEN_MASK (0x7<<16) -# define SSI_CONFIG_DD (1<<11) -# define SSI_CONFIG_AD (1<<10) -# define SSI_CONFIG_BM_BIT 8 -# define SSI_CONFIG_BM_MASK (0x3<<8) -# define SSI_CONFIG_CE (1<<7) -# define SSI_CONFIG_DP (1<<6) -# define SSI_CONFIG_DL (1<<5) -# define SSI_CONFIG_EP (1<<4) -#define SSI0_ADATA 0xB1600024 -# define SSI_AD_D (1<<24) -# define SSI_AD_ADDR_BIT 16 -# define SSI_AD_ADDR_MASK (0xff<<16) -# define SSI_AD_DATA_BIT 0 -# define SSI_AD_DATA_MASK (0xfff<<0) -#define SSI0_CLKDIV 0xB1600028 -#define SSI0_CONTROL 0xB1600100 -# define SSI_CONTROL_CD (1<<1) -# define SSI_CONTROL_E (1<<0) +#define SSI0_STATUS 0xB1600000 +# define SSI_STATUS_BF (1 << 4) +# define SSI_STATUS_OF (1 << 3) +# define SSI_STATUS_UF (1 << 2) +# define SSI_STATUS_D (1 << 1) +# define SSI_STATUS_B (1 << 0) +#define SSI0_INT 0xB1600004 +# define SSI_INT_OI (1 << 3) +# define SSI_INT_UI (1 << 2) +# define SSI_INT_DI (1 << 1) +#define SSI0_INT_ENABLE 0xB1600008 +# define SSI_INTE_OIE (1 << 3) +# define SSI_INTE_UIE (1 << 2) +# define SSI_INTE_DIE (1 << 1) +#define SSI0_CONFIG 0xB1600020 +# define SSI_CONFIG_AO (1 << 24) +# define SSI_CONFIG_DO (1 << 23) +# define SSI_CONFIG_ALEN_BIT 20 +# define SSI_CONFIG_ALEN_MASK (0x7 << 20) +# define SSI_CONFIG_DLEN_BIT 16 +# define SSI_CONFIG_DLEN_MASK (0x7 << 16) +# define SSI_CONFIG_DD (1 << 11) +# define SSI_CONFIG_AD (1 << 10) +# define SSI_CONFIG_BM_BIT 8 +# define SSI_CONFIG_BM_MASK (0x3 << 8) +# define SSI_CONFIG_CE (1 << 7) +# define SSI_CONFIG_DP (1 << 6) +# define SSI_CONFIG_DL (1 << 5) +# define SSI_CONFIG_EP (1 << 4) +#define SSI0_ADATA 0xB1600024 +# define SSI_AD_D (1 << 24) +# define SSI_AD_ADDR_BIT 16 +# define SSI_AD_ADDR_MASK (0xff << 16) +# define SSI_AD_DATA_BIT 0 +# define SSI_AD_DATA_MASK (0xfff << 0) +#define SSI0_CLKDIV 0xB1600028 +#define SSI0_CONTROL 0xB1600100 +# define SSI_CONTROL_CD (1 << 1) +# define SSI_CONTROL_E (1 << 0) /* SSI1 */ -#define SSI1_STATUS 0xB1680000 -#define SSI1_INT 0xB1680004 -#define SSI1_INT_ENABLE 0xB1680008 -#define SSI1_CONFIG 0xB1680020 -#define SSI1_ADATA 0xB1680024 -#define SSI1_CLKDIV 0xB1680028 -#define SSI1_ENABLE 0xB1680100 +#define SSI1_STATUS 0xB1680000 +#define SSI1_INT 0xB1680004 +#define SSI1_INT_ENABLE 0xB1680008 +#define SSI1_CONFIG 0xB1680020 +#define SSI1_ADATA 0xB1680024 +#define SSI1_CLKDIV 0xB1680028 +#define SSI1_ENABLE 0xB1680100 /* * Register content definitions */ -#define SSI_STATUS_BF (1<<4) -#define SSI_STATUS_OF (1<<3) -#define SSI_STATUS_UF (1<<2) -#define SSI_STATUS_D (1<<1) -#define SSI_STATUS_B (1<<0) +#define SSI_STATUS_BF (1 << 4) +#define SSI_STATUS_OF (1 << 3) +#define SSI_STATUS_UF (1 << 2) +#define SSI_STATUS_D (1 << 1) +#define SSI_STATUS_B (1 << 0) /* SSI_INT */ -#define SSI_INT_OI (1<<3) -#define SSI_INT_UI (1<<2) -#define SSI_INT_DI (1<<1) +#define SSI_INT_OI (1 << 3) +#define SSI_INT_UI (1 << 2) +#define SSI_INT_DI (1 << 1) /* SSI_INTEN */ -#define SSI_INTEN_OIE (1<<3) -#define SSI_INTEN_UIE (1<<2) -#define SSI_INTEN_DIE (1<<1) - -#define SSI_CONFIG_AO (1<<24) -#define SSI_CONFIG_DO (1<<23) -#define SSI_CONFIG_ALEN (7<<20) -#define SSI_CONFIG_DLEN (15<<16) -#define SSI_CONFIG_DD (1<<11) -#define SSI_CONFIG_AD (1<<10) -#define SSI_CONFIG_BM (3<<8) -#define SSI_CONFIG_CE (1<<7) -#define SSI_CONFIG_DP (1<<6) -#define SSI_CONFIG_DL (1<<5) -#define SSI_CONFIG_EP (1<<4) -#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) -#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) -#define SSI_CONFIG_BM_HI (0<<8) -#define SSI_CONFIG_BM_LO (1<<8) -#define SSI_CONFIG_BM_CY (2<<8) - -#define SSI_ADATA_D (1<<24) -#define SSI_ADATA_ADDR (0xFF<<16) -#define SSI_ADATA_DATA (0x0FFF) -#define SSI_ADATA_ADDR_N(N) (N<<16) - -#define SSI_ENABLE_CD (1<<1) -#define SSI_ENABLE_E (1<<0) - +#define SSI_INTEN_OIE (1 << 3) +#define SSI_INTEN_UIE (1 << 2) +#define SSI_INTEN_DIE (1 << 1) + +#define SSI_CONFIG_AO (1 << 24) +#define SSI_CONFIG_DO (1 << 23) +#define SSI_CONFIG_ALEN (7 << 20) +#define SSI_CONFIG_DLEN (15 << 16) +#define SSI_CONFIG_DD (1 << 11) +#define SSI_CONFIG_AD (1 << 10) +#define SSI_CONFIG_BM (3 << 8) +#define SSI_CONFIG_CE (1 << 7) +#define SSI_CONFIG_DP (1 << 6) +#define SSI_CONFIG_DL (1 << 5) +#define SSI_CONFIG_EP (1 << 4) +#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) +#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) +#define SSI_CONFIG_BM_HI (0 << 8) +#define SSI_CONFIG_BM_LO (1 << 8) +#define SSI_CONFIG_BM_CY (2 << 8) + +#define SSI_ADATA_D (1 << 24) +#define SSI_ADATA_ADDR (0xFF << 16) +#define SSI_ADATA_DATA 0x0FFF +#define SSI_ADATA_ADDR_N(N) (N << 16) + +#define SSI_ENABLE_CD (1 << 1) +#define SSI_ENABLE_E (1 << 0) /* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) -#define IR_RING_SIZE (IRDA_BASE+0x0C) -#define IR_RING_PROMPT (IRDA_BASE+0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) -#define IR_INT_CLEAR (IRDA_BASE+0x18) -#define IR_CONFIG_1 (IRDA_BASE+0x20) -# define IR_RX_INVERT_LED (1<<0) -# define IR_TX_INVERT_LED (1<<1) -# define IR_ST (1<<2) -# define IR_SF (1<<3) -# define IR_SIR (1<<4) -# define IR_MIR (1<<5) -# define IR_FIR (1<<6) -# define IR_16CRC (1<<7) -# define IR_TD (1<<8) -# define IR_RX_ALL (1<<9) -# define IR_DMA_ENABLE (1<<10) -# define IR_RX_ENABLE (1<<11) -# define IR_TX_ENABLE (1<<12) -# define IR_LOOPBACK (1<<14) -# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE+0x24) -#define IR_ENABLE (IRDA_BASE+0x28) -# define IR_RX_STATUS (1<<9) -# define IR_TX_STATUS (1<<10) -#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) -#define IR_CONFIG_2 (IRDA_BASE+0x3C) -# define IR_MODE_INV (1<<0) -# define IR_ONE_PIN (1<<1) -#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) +#define IRDA_BASE 0xB0300000 +#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) +#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) +#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) +#define IR_RING_SIZE (IRDA_BASE + 0x0C) +#define IR_RING_PROMPT (IRDA_BASE + 0x10) +#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) +#define IR_INT_CLEAR (IRDA_BASE + 0x18) +#define IR_CONFIG_1 (IRDA_BASE + 0x20) +# define IR_RX_INVERT_LED (1 << 0) +# define IR_TX_INVERT_LED (1 << 1) +# define IR_ST (1 << 2) +# define IR_SF (1 << 3) +# define IR_SIR (1 << 4) +# define IR_MIR (1 << 5) +# define IR_FIR (1 << 6) +# define IR_16CRC (1 << 7) +# define IR_TD (1 << 8) +# define IR_RX_ALL (1 << 9) +# define IR_DMA_ENABLE (1 << 10) +# define IR_RX_ENABLE (1 << 11) +# define IR_TX_ENABLE (1 << 12) +# define IR_LOOPBACK (1 << 14) +# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ + IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) +#define IR_SIR_FLAGS (IRDA_BASE + 0x24) +#define IR_ENABLE (IRDA_BASE + 0x28) +# define IR_RX_STATUS (1 << 9) +# define IR_TX_STATUS (1 << 10) +#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) +#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) +#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) +#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) +#define IR_CONFIG_2 (IRDA_BASE + 0x3C) +# define IR_MODE_INV (1 << 0) +# define IR_ONE_PIN (1 << 1) +#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) /* GPIO */ -#define SYS_PINFUNC 0xB190002C -# define SYS_PF_USB (1<<15) /* 2nd USB device/host */ -# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ -# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ -# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ -# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ -# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ -# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ -# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ -# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ -# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ -# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ -# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ -# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ -# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ -# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ -# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ - -/* Au1100 Only */ -# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ -# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ -# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ -# define SYS_PF_EX0 (1<<9) /* gpio2/clock */ - -/* Au1550 Only. Redefines lots of pins */ -# define SYS_PF_PSC2_MASK (7 << 17) -# define SYS_PF_PSC2_AC97 (0) -# define SYS_PF_PSC2_SPI (0) -# define SYS_PF_PSC2_I2S (1 << 17) -# define SYS_PF_PSC2_SMBUS (3 << 17) -# define SYS_PF_PSC2_GPIO (7 << 17) -# define SYS_PF_PSC3_MASK (7 << 20) -# define SYS_PF_PSC3_AC97 (0) -# define SYS_PF_PSC3_SPI (0) -# define SYS_PF_PSC3_I2S (1 << 20) -# define SYS_PF_PSC3_SMBUS (3 << 20) -# define SYS_PF_PSC3_GPIO (7 << 20) -# define SYS_PF_PSC1_S1 (1 << 1) -# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) - -/* Au1200 Only */ +#define SYS_PINFUNC 0xB190002C +# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ +# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ +# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ +# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ +# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ +# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ +# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ +# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ +# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ +# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ +# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ +# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ +# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ +# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ +# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ +# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ + +/* Au1100 only */ +# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ +# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ +# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ +# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ + +/* Au1550 only. Redefines lots of pins */ +# define SYS_PF_PSC2_MASK (7 << 17) +# define SYS_PF_PSC2_AC97 0 +# define SYS_PF_PSC2_SPI 0 +# define SYS_PF_PSC2_I2S (1 << 17) +# define SYS_PF_PSC2_SMBUS (3 << 17) +# define SYS_PF_PSC2_GPIO (7 << 17) +# define SYS_PF_PSC3_MASK (7 << 20) +# define SYS_PF_PSC3_AC97 0 +# define SYS_PF_PSC3_SPI 0 +# define SYS_PF_PSC3_I2S (1 << 20) +# define SYS_PF_PSC3_SMBUS (3 << 20) +# define SYS_PF_PSC3_GPIO (7 << 20) +# define SYS_PF_PSC1_S1 (1 << 1) +# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) + +/* Au1200 only */ #ifdef CONFIG_SOC_AU1200 -#define SYS_PINFUNC_DMA (1<<31) -#define SYS_PINFUNC_S0A (1<<30) -#define SYS_PINFUNC_S1A (1<<29) -#define SYS_PINFUNC_LP0 (1<<28) -#define SYS_PINFUNC_LP1 (1<<27) -#define SYS_PINFUNC_LD16 (1<<26) -#define SYS_PINFUNC_LD8 (1<<25) -#define SYS_PINFUNC_LD1 (1<<24) -#define SYS_PINFUNC_LD0 (1<<23) -#define SYS_PINFUNC_P1A (3<<21) -#define SYS_PINFUNC_P1B (1<<20) -#define SYS_PINFUNC_FS3 (1<<19) -#define SYS_PINFUNC_P0A (3<<17) -#define SYS_PINFUNC_CS (1<<16) -#define SYS_PINFUNC_CIM (1<<15) -#define SYS_PINFUNC_P1C (1<<14) -#define SYS_PINFUNC_U1T (1<<12) -#define SYS_PINFUNC_U1R (1<<11) -#define SYS_PINFUNC_EX1 (1<<10) -#define SYS_PINFUNC_EX0 (1<<9) -#define SYS_PINFUNC_U0R (1<<8) -#define SYS_PINFUNC_MC (1<<7) -#define SYS_PINFUNC_S0B (1<<6) -#define SYS_PINFUNC_S0C (1<<5) -#define SYS_PINFUNC_P0B (1<<4) -#define SYS_PINFUNC_U0T (1<<3) -#define SYS_PINFUNC_S1B (1<<2) +#define SYS_PINFUNC_DMA (1 << 31) +#define SYS_PINFUNC_S0A (1 << 30) +#define SYS_PINFUNC_S1A (1 << 29) +#define SYS_PINFUNC_LP0 (1 << 28) +#define SYS_PINFUNC_LP1 (1 << 27) +#define SYS_PINFUNC_LD16 (1 << 26) +#define SYS_PINFUNC_LD8 (1 << 25) +#define SYS_PINFUNC_LD1 (1 << 24) +#define SYS_PINFUNC_LD0 (1 << 23) +#define SYS_PINFUNC_P1A (3 << 21) +#define SYS_PINFUNC_P1B (1 << 20) +#define SYS_PINFUNC_FS3 (1 << 19) +#define SYS_PINFUNC_P0A (3 << 17) +#define SYS_PINFUNC_CS (1 << 16) +#define SYS_PINFUNC_CIM (1 << 15) +#define SYS_PINFUNC_P1C (1 << 14) +#define SYS_PINFUNC_U1T (1 << 12) +#define SYS_PINFUNC_U1R (1 << 11) +#define SYS_PINFUNC_EX1 (1 << 10) +#define SYS_PINFUNC_EX0 (1 << 9) +#define SYS_PINFUNC_U0R (1 << 8) +#define SYS_PINFUNC_MC (1 << 7) +#define SYS_PINFUNC_S0B (1 << 6) +#define SYS_PINFUNC_S0C (1 << 5) +#define SYS_PINFUNC_P0B (1 << 4) +#define SYS_PINFUNC_U0T (1 << 3) +#define SYS_PINFUNC_S1B (1 << 2) #endif -#define SYS_TRIOUTRD 0xB1900100 -#define SYS_TRIOUTCLR 0xB1900100 -#define SYS_OUTPUTRD 0xB1900108 -#define SYS_OUTPUTSET 0xB1900108 -#define SYS_OUTPUTCLR 0xB190010C -#define SYS_PINSTATERD 0xB1900110 -#define SYS_PININPUTEN 0xB1900110 +#define SYS_TRIOUTRD 0xB1900100 +#define SYS_TRIOUTCLR 0xB1900100 +#define SYS_OUTPUTRD 0xB1900108 +#define SYS_OUTPUTSET 0xB1900108 +#define SYS_OUTPUTCLR 0xB190010C +#define SYS_PINSTATERD 0xB1900110 +#define SYS_PININPUTEN 0xB1900110 /* GPIO2, Au1500, Au1550 only */ -#define GPIO2_BASE 0xB1700000 -#define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_OUTPUT (GPIO2_BASE + 8) -#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) -#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) -#define GPIO2_ENABLE (GPIO2_BASE + 0x14) +#define GPIO2_BASE 0xB1700000 +#define GPIO2_DIR (GPIO2_BASE + 0) +#define GPIO2_OUTPUT (GPIO2_BASE + 8) +#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) +#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) +#define GPIO2_ENABLE (GPIO2_BASE + 0x14) /* Power Management */ -#define SYS_SCRATCH0 0xB1900018 -#define SYS_SCRATCH1 0xB190001C -#define SYS_WAKEMSK 0xB1900034 -#define SYS_ENDIAN 0xB1900038 -#define SYS_POWERCTRL 0xB190003C -#define SYS_WAKESRC 0xB190005C -#define SYS_SLPPWR 0xB1900078 -#define SYS_SLEEP 0xB190007C +#define SYS_SCRATCH0 0xB1900018 +#define SYS_SCRATCH1 0xB190001C +#define SYS_WAKEMSK 0xB1900034 +#define SYS_ENDIAN 0xB1900038 +#define SYS_POWERCTRL 0xB190003C +#define SYS_WAKESRC 0xB190005C +#define SYS_SLPPWR 0xB1900078 +#define SYS_SLEEP 0xB190007C /* Clock Controller */ -#define SYS_FREQCTRL0 0xB1900020 -# define SYS_FC_FRDIV2_BIT 22 -# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) -# define SYS_FC_FE2 (1<<21) -# define SYS_FC_FS2 (1<<20) -# define SYS_FC_FRDIV1_BIT 12 -# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) -# define SYS_FC_FE1 (1<<11) -# define SYS_FC_FS1 (1<<10) -# define SYS_FC_FRDIV0_BIT 2 -# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) -# define SYS_FC_FE0 (1<<1) -# define SYS_FC_FS0 (1<<0) -#define SYS_FREQCTRL1 0xB1900024 -# define SYS_FC_FRDIV5_BIT 22 -# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) -# define SYS_FC_FE5 (1<<21) -# define SYS_FC_FS5 (1<<20) -# define SYS_FC_FRDIV4_BIT 12 -# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) -# define SYS_FC_FE4 (1<<11) -# define SYS_FC_FS4 (1<<10) -# define SYS_FC_FRDIV3_BIT 2 -# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) -# define SYS_FC_FE3 (1<<1) -# define SYS_FC_FS3 (1<<0) -#define SYS_CLKSRC 0xB1900028 -# define SYS_CS_ME1_BIT 27 -# define SYS_CS_ME1_MASK (0x7< * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -31,7 +30,7 @@ #ifndef __ASM_AU1000_DMA_H #define __ASM_AU1000_DMA_H -#include /* need byte IO */ +#include /* need byte IO */ #include /* And spinlocks */ #include #include @@ -50,36 +49,36 @@ #define DMA_DAH_MASK (0x0f << 20) #define DMA_DID_BIT 16 #define DMA_DID_MASK (0x0f << DMA_DID_BIT) -#define DMA_DS (1<<15) -#define DMA_BE (1<<13) -#define DMA_DR (1<<12) -#define DMA_TS8 (1<<11) +#define DMA_DS (1 << 15) +#define DMA_BE (1 << 13) +#define DMA_DR (1 << 12) +#define DMA_TS8 (1 << 11) #define DMA_DW_BIT 9 #define DMA_DW_MASK (0x03 << DMA_DW_BIT) #define DMA_DW8 (0 << DMA_DW_BIT) #define DMA_DW16 (1 << DMA_DW_BIT) #define DMA_DW32 (2 << DMA_DW_BIT) -#define DMA_NC (1<<8) -#define DMA_IE (1<<7) -#define DMA_HALT (1<<6) -#define DMA_GO (1<<5) -#define DMA_AB (1<<4) -#define DMA_D1 (1<<3) -#define DMA_BE1 (1<<2) -#define DMA_D0 (1<<1) -#define DMA_BE0 (1<<0) - -#define DMA_PERIPHERAL_ADDR 0x00000008 -#define DMA_BUFFER0_START 0x0000000C -#define DMA_BUFFER1_START 0x00000014 -#define DMA_BUFFER0_COUNT 0x00000010 -#define DMA_BUFFER1_COUNT 0x00000018 -#define DMA_BAH_BIT 16 -#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT) -#define DMA_COUNT_BIT 0 -#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT) - -/* DMA Device ID's follow */ +#define DMA_NC (1 << 8) +#define DMA_IE (1 << 7) +#define DMA_HALT (1 << 6) +#define DMA_GO (1 << 5) +#define DMA_AB (1 << 4) +#define DMA_D1 (1 << 3) +#define DMA_BE1 (1 << 2) +#define DMA_D0 (1 << 1) +#define DMA_BE0 (1 << 0) + +#define DMA_PERIPHERAL_ADDR 0x00000008 +#define DMA_BUFFER0_START 0x0000000C +#define DMA_BUFFER1_START 0x00000014 +#define DMA_BUFFER0_COUNT 0x00000010 +#define DMA_BUFFER1_COUNT 0x00000018 +#define DMA_BAH_BIT 16 +#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT) +#define DMA_COUNT_BIT 0 +#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT) + +/* DMA Device IDs follow */ enum { DMA_ID_UART0_TX = 0, DMA_ID_UART0_RX, @@ -110,7 +109,8 @@ enum { }; struct dma_chan { - int dev_id; // this channel is allocated if >=0, free otherwise + int dev_id; /* this channel is allocated if >= 0, */ + /* free otherwise */ unsigned int io; const char *dev_str; int irq; @@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos, extern void dump_au1000_dma_channel(unsigned int dmanr); extern spinlock_t au1000_dma_spin_lock; - -static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr) +static inline struct dma_chan *get_dma_chan(unsigned int dmanr) { - if (dmanr >= NUM_AU1000_DMA_CHANNELS - || au1000_dma_table[dmanr].dev_id < 0) + if (dmanr >= NUM_AU1000_DMA_CHANNELS || + au1000_dma_table[dmanr].dev_id < 0) return NULL; return &au1000_dma_table[dmanr]; } -static __inline__ unsigned long claim_dma_lock(void) +static inline unsigned long claim_dma_lock(void) { unsigned long flags; + spin_lock_irqsave(&au1000_dma_spin_lock, flags); return flags; } -static __inline__ void release_dma_lock(unsigned long flags) +static inline void release_dma_lock(unsigned long flags) { spin_unlock_irqrestore(&au1000_dma_spin_lock, flags); } @@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags) /* * Set the DMA buffer enable bits in the mode register. */ -static __inline__ void enable_dma_buffer0(unsigned int dmanr) +static inline void enable_dma_buffer0(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(DMA_BE0, chan->io + DMA_MODE_SET); } -static __inline__ void enable_dma_buffer1(unsigned int dmanr) + +static inline void enable_dma_buffer1(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(DMA_BE1, chan->io + DMA_MODE_SET); } -static __inline__ void enable_dma_buffers(unsigned int dmanr) +static inline void enable_dma_buffers(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); } -static __inline__ void start_dma(unsigned int dmanr) +static inline void start_dma(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; - au_writel(DMA_GO, chan->io + DMA_MODE_SET); } #define DMA_HALT_POLL 0x5000 -static __inline__ void halt_dma(unsigned int dmanr) +static inline void halt_dma(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); int i; + if (!chan) return; - au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); - // poll the halt bit + + /* Poll the halt bit */ for (i = 0; i < DMA_HALT_POLL; i++) if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) break; @@ -205,55 +210,57 @@ static __inline__ void halt_dma(unsigned int dmanr) printk(KERN_INFO "halt_dma: HALT poll expired!\n"); } - -static __inline__ void disable_dma(unsigned int dmanr) +static inline void disable_dma(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; halt_dma(dmanr); - // now we can disable the buffers + /* Now we can disable the buffers */ au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); } -static __inline__ int dma_halted(unsigned int dmanr) +static inline int dma_halted(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return 1; return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; } -/* initialize a DMA channel */ -static __inline__ void init_dma(unsigned int dmanr) +/* Initialize a DMA channel. */ +static inline void init_dma(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); u32 mode; + if (!chan) return; disable_dma(dmanr); - // set device FIFO address - au_writel(CPHYSADDR(chan->fifo_addr), - chan->io + DMA_PERIPHERAL_ADDR); + /* Set device FIFO address */ + au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); mode = chan->mode | (chan->dev_id << DMA_DID_BIT); if (chan->irq) mode |= DMA_IE; au_writel(~mode, chan->io + DMA_MODE_CLEAR); - au_writel(mode, chan->io + DMA_MODE_SET); + au_writel(mode, chan->io + DMA_MODE_SET); } /* - * set mode for a specific DMA channel + * Set mode for a specific DMA channel */ -static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode) +static inline void set_dma_mode(unsigned int dmanr, unsigned int mode) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; /* @@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode) chan->mode |= mode; } -static __inline__ unsigned int get_dma_mode(unsigned int dmanr) +static inline unsigned int get_dma_mode(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return 0; return chan->mode; } -static __inline__ int get_dma_active_buffer(unsigned int dmanr) +static inline int get_dma_active_buffer(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return -1; return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; } - /* - * set the device FIFO address for a specific DMA channel - only + * Set the device FIFO address for a specific DMA channel - only * applicable to GPO4 and GPO5. All the other devices have fixed * FIFO addresses. */ -static __inline__ void set_dma_fifo_addr(unsigned int dmanr, - unsigned int a) +static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; - if (chan->mode & DMA_DS) /* second bank of device ids */ + if (chan->mode & DMA_DS) /* second bank of device IDs */ return; if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) @@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr, /* * Clear the DMA buffer done bits in the mode register. */ -static __inline__ void clear_dma_done0(unsigned int dmanr) +static inline void clear_dma_done0(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); } -static __inline__ void clear_dma_done1(unsigned int dmanr) + +static inline void clear_dma_done1(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); @@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr) /* * This does nothing - not applicable to Au1000 DMA. */ -static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) +static inline void set_dma_page(unsigned int dmanr, char pagenr) { } /* * Set Buffer 0 transfer address for specific DMA channel. */ -static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a) +static inline void set_dma_addr0(unsigned int dmanr, unsigned int a) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(a, chan->io + DMA_BUFFER0_START); @@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a) /* * Set Buffer 1 transfer address for specific DMA channel. */ -static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a) +static inline void set_dma_addr1(unsigned int dmanr, unsigned int a) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; au_writel(a, chan->io + DMA_BUFFER1_START); @@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a) /* * Set Buffer 0 transfer size (max 64k) for a specific DMA channel. */ -static __inline__ void set_dma_count0(unsigned int dmanr, - unsigned int count) +static inline void set_dma_count0(unsigned int dmanr, unsigned int count) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; count &= DMA_COUNT_MASK; @@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr, /* * Set Buffer 1 transfer size (max 64k) for a specific DMA channel. */ -static __inline__ void set_dma_count1(unsigned int dmanr, - unsigned int count) +static inline void set_dma_count1(unsigned int dmanr, unsigned int count) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; count &= DMA_COUNT_MASK; @@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr, /* * Set both buffer transfer sizes (max 64k) for a specific DMA channel. */ -static __inline__ void set_dma_count(unsigned int dmanr, - unsigned int count) +static inline void set_dma_count(unsigned int dmanr, unsigned int count) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return; count &= DMA_COUNT_MASK; @@ -396,35 +409,36 @@ static __inline__ void set_dma_count(unsigned int dmanr, * Returns which buffer has its done bit set in the mode register. * Returns -1 if neither or both done bits set. */ -static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr) +static inline unsigned int get_dma_buffer_done(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return 0; - - return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); + return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); } /* * Returns the DMA channel's Buffer Done IRQ number. */ -static __inline__ int get_dma_done_irq(unsigned int dmanr) +static inline int get_dma_done_irq(unsigned int dmanr) { struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return -1; - return chan->irq; } /* * Get DMA residue count. Returns the number of _bytes_ left to transfer. */ -static __inline__ int get_dma_residue(unsigned int dmanr) +static inline int get_dma_residue(unsigned int dmanr) { int curBufCntReg, count; struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) return 0; @@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr) } #endif /* __ASM_AU1000_DMA_H */ - diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h index 298f92012e8e..d8c96fda5549 100644 --- a/include/asm-mips/mach-au1x00/au1000_gpio.h +++ b/include/asm-mips/mach-au1x00/au1000_gpio.h @@ -2,12 +2,12 @@ * FILE NAME au1000_gpio.h * * BRIEF MODULE DESCRIPTION - * API to Alchemy Au1000 GPIO device. + * API to Alchemy Au1xx0 GPIO device. * * Author: MontaVista Software, Inc. - * Steve Longerbeam + * Steve Longerbeam * - * Copyright 2001 MontaVista Software Inc. + * Copyright 2001, 2008 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -37,12 +37,12 @@ #define AU1000GPIO_IOC_MAGIC 'A' -#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int) -#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int) -#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int) -#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int) -#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int) -#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int) +#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int) +#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int) +#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int) +#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int) +#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int) +#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int) #ifdef __KERNEL__ extern u32 get_au1000_avail_gpio_mask(void); diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h index c2f0466523ec..40e6c489833a 100644 --- a/include/asm-mips/mach-au1x00/au1550_spi.h +++ b/include/asm-mips/mach-au1x00/au1550_spi.h @@ -1,5 +1,5 @@ /* - * au1550_spi.h - au1550 psc spi controller driver - platform data struct + * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure */ #ifndef _AU1550_SPI_H_ diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h index 947135941033..1b3655090ed3 100644 --- a/include/asm-mips/mach-au1x00/au1xxx.h +++ b/include/asm-mips/mach-au1x00/au1xxx.h @@ -23,10 +23,10 @@ #ifndef _AU1XXX_H_ #define _AU1XXX_H_ - #include -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) +#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \ + defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) #include #elif defined(CONFIG_MIPS_PB1550) diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h index 93d507cea518..ad17d7ce516a 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -28,17 +28,18 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first - * seen in the AU1550 part. +/* + * Specifics for the Au1xxx Descriptor-Based DMA Controller, + * first seen in the AU1550 part. */ #ifndef _AU1000_DBDMA_H_ #define _AU1000_DBDMA_H_ - #ifndef _LANGUAGE_ASSEMBLY -/* The DMA base addresses. - * The Channels are every 256 bytes (0x0100) from the channel 0 base. +/* + * The DMA base addresses. + * The channels are every 256 bytes (0x0100) from the channel 0 base. * Interrupt status/enable is bits 15:0 for channels 15 to zero. */ #define DDMA_GLOBAL_BASE 0xb4003000 @@ -51,16 +52,14 @@ typedef volatile struct dbdma_global { u32 ddma_inten; } dbdma_global_t; -/* General Configuration. -*/ +/* General Configuration. */ #define DDMA_CONFIG_AF (1 << 2) #define DDMA_CONFIG_AH (1 << 1) #define DDMA_CONFIG_AL (1 << 0) #define DDMA_THROTTLE_EN (1 << 31) -/* The structure of a DMA Channel. -*/ +/* The structure of a DMA Channel. */ typedef volatile struct au1xxx_dma_channel { u32 ddma_cfg; /* See below */ u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ @@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel { u32 ddma_irq; /* If bit 0 set, interrupt pending */ u32 ddma_stat; /* See below */ u32 ddma_bytecnt; /* Byte count, valid only when chan idle */ - /* Remainder, up to the 256 byte boundary, is reserved. - */ + /* Remainder, up to the 256 byte boundary, is reserved. */ } au1x_dma_chan_t; #define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */ @@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel { #define DDMA_CFG_DBE (1 << 1) /* Destination big endian */ #define DDMA_CFG_EN (1 << 0) /* Channel enable */ -/* Always set when descriptor processing done, regardless of +/* + * Always set when descriptor processing done, regardless of * interrupt enable state. Reflected in global intstat, don't * clear this until global intstat is read/used. */ @@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel { #define DDMA_STAT_V (1 << 1) /* Descriptor valid */ #define DDMA_STAT_H (1 << 0) /* Channel Halted */ -/* "Standard" DDMA Descriptor. +/* + * "Standard" DDMA Descriptor. * Must be 32-byte aligned. */ typedef volatile struct au1xxx_ddma_desc { @@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc { u32 dscr_dest1; /* See below */ u32 dscr_stat; /* completion status */ u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ - /* First 32bytes are HW specific!!! - Lets have some SW data following.. make sure its 32bytes + /* + * First 32 bytes are HW specific!!! + * Lets have some SW data following -- make sure it's 32 bytes. */ u32 sw_status; u32 sw_context; @@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ -#define SW_STATUS_INUSE (1<<0) +#define SW_STATUS_INUSE (1 << 0) -/* Command 0 device IDs. -*/ +/* Command 0 device IDs. */ #ifdef CONFIG_SOC_AU1550 #define DSCR_CMD0_UART0_TX 0 #define DSCR_CMD0_UART0_RX 1 @@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 -/* THis macro is used to find/create custom device types */ -#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) -#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) - +/* This macro is used to find/create custom device types */ +#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \ + ((d) & 0xFF)) +#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF) #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) -/* Source/Destination transfer width. -*/ +/* Source/Destination transfer width. */ #define DSCR_CMD0_BYTE 0 #define DSCR_CMD0_HALFWORD 1 #define DSCR_CMD0_WORD 2 @@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) -/* DDMA Descriptor Type. -*/ +/* DDMA Descriptor Type. */ #define DSCR_CMD0_STANDARD 0 #define DSCR_CMD0_LITERAL 1 #define DSCR_CMD0_CMP_BRANCH 2 #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) -/* Status Instruction. -*/ +/* Status Instruction. */ #define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */ #define DSCR_CMD0_ST_CURRENT 1 /* Write current status */ #define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */ @@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) -/* Descriptor Command 1 -*/ +/* Descriptor Command 1. */ #define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */ #define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */ #define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */ #define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */ -/* Flag description. -*/ +/* Flag description. */ #define DSCR_CMD1_FL_MEM_STRIDE0 0 #define DSCR_CMD1_FL_MEM_STRIDE1 1 #define DSCR_CMD1_FL_MEM_STRIDE2 2 #define DSCR_CMD1_FL(x) (((x) & 0x3) << 22) -/* Source1, 1-dimensional stride. -*/ +/* Source1, 1-dimensional stride. */ #define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */ #define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */ #define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */ @@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */ #define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0) -/* Dest1, 1-dimensional stride. -*/ +/* Dest1, 1-dimensional stride. */ #define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */ #define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */ #define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */ @@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_SRC1_SAM(x) (((x) & 3) << 28) #define DSCR_DEST1_DAM(x) (((x) & 3) << 28) -/* The next descriptor pointer. -*/ +/* The next descriptor pointer. */ #define DSCR_NXTPTR_MASK (0x07ffffff) #define DSCR_NXTPTR(x) ((x) >> 5) #define DSCR_GET_NXTPTR(x) ((x) << 5) #define DSCR_NXTPTR_MS (1 << 27) -/* The number of DBDMA channels. -*/ +/* The number of DBDMA channels. */ #define NUM_DBDMA_CHANS 16 /* - * Ddma API definitions + * DDMA API definitions * FIXME: may not fit to this header file */ typedef struct dbdma_device_table { - u32 dev_id; - u32 dev_flags; - u32 dev_tsize; - u32 dev_devwidth; - u32 dev_physaddr; /* If FIFO */ - u32 dev_intlevel; - u32 dev_intpolarity; + u32 dev_id; + u32 dev_flags; + u32 dev_tsize; + u32 dev_devwidth; + u32 dev_physaddr; /* If FIFO */ + u32 dev_intlevel; + u32 dev_intpolarity; } dbdev_tab_t; @@ -316,44 +307,41 @@ typedef struct dbdma_chan_config { au1x_ddma_desc_t *chan_desc_base; au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; void *chan_callparam; - void (*chan_callback)(int, void *); + void (*chan_callback)(int, void *); } chan_tab_t; #define DEV_FLAGS_INUSE (1 << 0) #define DEV_FLAGS_ANYUSE (1 << 1) #define DEV_FLAGS_OUT (1 << 2) #define DEV_FLAGS_IN (1 << 3) -#define DEV_FLAGS_BURSTABLE (1 << 4) +#define DEV_FLAGS_BURSTABLE (1 << 4) #define DEV_FLAGS_SYNC (1 << 5) -/* end Ddma API definitions */ +/* end DDMA API definitions */ -/* External functions for drivers to use. -*/ -/* Use this to allocate a dbdma channel. The device ids are one of the - * DSCR_CMD0 devices IDs, which is usually redefined to a more - * meaningful name. The 'callback' is called during dma completion +/* + * External functions for drivers to use. + * Use this to allocate a DBDMA channel. The device IDs are one of + * the DSCR_CMD0 devices IDs, which is usually redefined to a more + * meaningful name. The 'callback' is called during DMA completion * interrupt. */ extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, - void (*callback)(int, void *), void *callparam); + void (*callback)(int, void *), + void *callparam); #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS -/* Set the device width of a in/out fifo. -*/ +/* Set the device width of an in/out FIFO. */ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); -/* Allocate a ring of descriptors for dbdma. -*/ +/* Allocate a ring of descriptors for DBDMA. */ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); -/* Put buffers on source/destination descriptors. -*/ +/* Put buffers on source/destination descriptors. */ u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); -/* Get a buffer from the destination descriptor. -*/ +/* Get a buffer from the destination descriptor. */ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); void au1xxx_dbdma_stop(u32 chanid); @@ -364,29 +352,34 @@ u32 au1xxx_get_dma_residue(u32 chanid); void au1xxx_dbdma_chan_free(u32 chanid); void au1xxx_dbdma_dump(u32 chanid); -u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ); +u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); -u32 au1xxx_ddma_add_device( dbdev_tab_t *dev ); -void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); +u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); +void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); /* - Some compatibilty macros -- - Needed to make changes to API without breaking existing drivers -*/ -#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) - - -#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) + * Some compatibilty macros -- needed to make changes to API + * without breaking existing drivers. + */ +#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \ + _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \ + _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) +#define put_source_flags(chanid, buf, nbytes, flags) \ + au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) + +#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \ + _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \ + _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) +#define put_dest_flags(chanid, buf, nbytes, flags) \ + au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) /* * Flags for the put_source/put_dest functions. */ -#define DDMA_FLAGS_IE (1<<0) -#define DDMA_FLAGS_NOIE (1<<1) +#define DDMA_FLAGS_IE (1 << 0) +#define DDMA_FLAGS_NOIE (1 << 1) #endif /* _LANGUAGE_ASSEMBLY */ #endif /* _AU1000_DBDMA_H_ */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index b493a5e46c63..60638b8969ba 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -31,167 +31,164 @@ */ #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - #define DMA_WAIT_TIMEOUT 100 - #define NUM_DESCRIPTORS PRD_ENTRIES +#define DMA_WAIT_TIMEOUT 100 +#define NUM_DESCRIPTORS PRD_ENTRIES #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ - #define NUM_DESCRIPTORS 2 +#define NUM_DESCRIPTORS 2 #endif #ifndef AU1XXX_ATA_RQSIZE - #define AU1XXX_ATA_RQSIZE 128 +#define AU1XXX_ATA_RQSIZE 128 #endif /* Disable Burstable-Support for DBDMA */ #ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON - #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 +#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 #endif #ifdef CONFIG_PM /* -* This will enable the device to be powered up when write() or read() -* is called. If this is not defined, the driver will return -EBUSY. -*/ + * This will enable the device to be powered up when write() or read() + * is called. If this is not defined, the driver will return -EBUSY. + */ #define WAKE_ON_ACCESS 1 -typedef struct -{ - spinlock_t lock; /* Used to block on state transitions */ - au1xxx_power_dev_t *dev; /* Power Managers device structure */ - unsigned stopped; /* USed to signaling device is stopped */ +typedef struct { + spinlock_t lock; /* Used to block on state transitions */ + au1xxx_power_dev_t *dev; /* Power Managers device structure */ + unsigned stopped; /* Used to signal device is stopped */ } pm_state; #endif - -typedef struct -{ - u32 tx_dev_id, rx_dev_id, target_dev_id; - u32 tx_chan, rx_chan; - void *tx_desc_head, *rx_desc_head; - ide_hwif_t *hwif; +typedef struct { + u32 tx_dev_id, rx_dev_id, target_dev_id; + u32 tx_chan, rx_chan; + void *tx_desc_head, *rx_desc_head; + ide_hwif_t *hwif; #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - ide_drive_t *drive; - struct dbdma_cmd *dma_table_cpu; - dma_addr_t dma_table_dma; + ide_drive_t *drive; + struct dbdma_cmd *dma_table_cpu; + dma_addr_t dma_table_dma; #endif int irq; u32 regbase; #ifdef CONFIG_PM - pm_state pm; + pm_state pm; #endif } _auide_hwif; -/******************************************************************************* -* PIO Mode timing calculation : * -* * -* Static Bus Spec ATA Spec * -* Tcsoe = t1 * -* Toecs = t9 * -* Twcs = t9 * -* Tcsh = t2i | t2 * -* Tcsoff = t2i | t2 * -* Twp = t2 * -* Tcsw = t1 * -* Tpm = 0 * -* Ta = t1+t2 * -*******************************************************************************/ +/******************************************************************************/ +/* PIO Mode timing calculation : */ +/* */ +/* Static Bus Spec ATA Spec */ +/* Tcsoe = t1 */ +/* Toecs = t9 */ +/* Twcs = t9 */ +/* Tcsh = t2i | t2 */ +/* Tcsoff = t2i | t2 */ +/* Twp = t2 */ +/* Tcsw = t1 */ +/* Tpm = 0 */ +/* Ta = t1+t2 */ +/******************************************************************************/ -#define TCSOE_MASK (0x07<<29) -#define TOECS_MASK (0x07<<26) -#define TWCS_MASK (0x07<<28) -#define TCSH_MASK (0x0F<<24) -#define TCSOFF_MASK (0x07<<20) -#define TWP_MASK (0x3F<<14) -#define TCSW_MASK (0x0F<<10) -#define TPM_MASK (0x0F<<6) -#define TA_MASK (0x3F<<0) -#define TS_MASK (1<<8) +#define TCSOE_MASK (0x07 << 29) +#define TOECS_MASK (0x07 << 26) +#define TWCS_MASK (0x07 << 28) +#define TCSH_MASK (0x0F << 24) +#define TCSOFF_MASK (0x07 << 20) +#define TWP_MASK (0x3F << 14) +#define TCSW_MASK (0x0F << 10) +#define TPM_MASK (0x0F << 6) +#define TA_MASK (0x3F << 0) +#define TS_MASK (1 << 8) /* Timing parameters PIO mode 0 */ -#define SBC_IDE_PIO0_TCSOE (0x04<<29) -#define SBC_IDE_PIO0_TOECS (0x01<<26) -#define SBC_IDE_PIO0_TWCS (0x02<<28) -#define SBC_IDE_PIO0_TCSH (0x08<<24) -#define SBC_IDE_PIO0_TCSOFF (0x07<<20) -#define SBC_IDE_PIO0_TWP (0x10<<14) -#define SBC_IDE_PIO0_TCSW (0x04<<10) -#define SBC_IDE_PIO0_TPM (0x0<<6) -#define SBC_IDE_PIO0_TA (0x15<<0) +#define SBC_IDE_PIO0_TCSOE (0x04 << 29) +#define SBC_IDE_PIO0_TOECS (0x01 << 26) +#define SBC_IDE_PIO0_TWCS (0x02 << 28) +#define SBC_IDE_PIO0_TCSH (0x08 << 24) +#define SBC_IDE_PIO0_TCSOFF (0x07 << 20) +#define SBC_IDE_PIO0_TWP (0x10 << 14) +#define SBC_IDE_PIO0_TCSW (0x04 << 10) +#define SBC_IDE_PIO0_TPM (0x00 << 6) +#define SBC_IDE_PIO0_TA (0x15 << 0) /* Timing parameters PIO mode 1 */ -#define SBC_IDE_PIO1_TCSOE (0x03<<29) -#define SBC_IDE_PIO1_TOECS (0x01<<26) -#define SBC_IDE_PIO1_TWCS (0x01<<28) -#define SBC_IDE_PIO1_TCSH (0x06<<24) -#define SBC_IDE_PIO1_TCSOFF (0x06<<20) -#define SBC_IDE_PIO1_TWP (0x08<<14) -#define SBC_IDE_PIO1_TCSW (0x03<<10) -#define SBC_IDE_PIO1_TPM (0x00<<6) -#define SBC_IDE_PIO1_TA (0x0B<<0) +#define SBC_IDE_PIO1_TCSOE (0x03 << 29) +#define SBC_IDE_PIO1_TOECS (0x01 << 26) +#define SBC_IDE_PIO1_TWCS (0x01 << 28) +#define SBC_IDE_PIO1_TCSH (0x06 << 24) +#define SBC_IDE_PIO1_TCSOFF (0x06 << 20) +#define SBC_IDE_PIO1_TWP (0x08 << 14) +#define SBC_IDE_PIO1_TCSW (0x03 << 10) +#define SBC_IDE_PIO1_TPM (0x00 << 6) +#define SBC_IDE_PIO1_TA (0x0B << 0) /* Timing parameters PIO mode 2 */ -#define SBC_IDE_PIO2_TCSOE (0x05<<29) -#define SBC_IDE_PIO2_TOECS (0x01<<26) -#define SBC_IDE_PIO2_TWCS (0x01<<28) -#define SBC_IDE_PIO2_TCSH (0x07<<24) -#define SBC_IDE_PIO2_TCSOFF (0x07<<20) -#define SBC_IDE_PIO2_TWP (0x1F<<14) -#define SBC_IDE_PIO2_TCSW (0x05<<10) -#define SBC_IDE_PIO2_TPM (0x00<<6) -#define SBC_IDE_PIO2_TA (0x22<<0) +#define SBC_IDE_PIO2_TCSOE (0x05 << 29) +#define SBC_IDE_PIO2_TOECS (0x01 << 26) +#define SBC_IDE_PIO2_TWCS (0x01 << 28) +#define SBC_IDE_PIO2_TCSH (0x07 << 24) +#define SBC_IDE_PIO2_TCSOFF (0x07 << 20) +#define SBC_IDE_PIO2_TWP (0x1F << 14) +#define SBC_IDE_PIO2_TCSW (0x05 << 10) +#define SBC_IDE_PIO2_TPM (0x00 << 6) +#define SBC_IDE_PIO2_TA (0x22 << 0) /* Timing parameters PIO mode 3 */ -#define SBC_IDE_PIO3_TCSOE (0x05<<29) -#define SBC_IDE_PIO3_TOECS (0x01<<26) -#define SBC_IDE_PIO3_TWCS (0x01<<28) -#define SBC_IDE_PIO3_TCSH (0x0D<<24) -#define SBC_IDE_PIO3_TCSOFF (0x0D<<20) -#define SBC_IDE_PIO3_TWP (0x15<<14) -#define SBC_IDE_PIO3_TCSW (0x05<<10) -#define SBC_IDE_PIO3_TPM (0x00<<6) -#define SBC_IDE_PIO3_TA (0x1A<<0) +#define SBC_IDE_PIO3_TCSOE (0x05 << 29) +#define SBC_IDE_PIO3_TOECS (0x01 << 26) +#define SBC_IDE_PIO3_TWCS (0x01 << 28) +#define SBC_IDE_PIO3_TCSH (0x0D << 24) +#define SBC_IDE_PIO3_TCSOFF (0x0D << 20) +#define SBC_IDE_PIO3_TWP (0x15 << 14) +#define SBC_IDE_PIO3_TCSW (0x05 << 10) +#define SBC_IDE_PIO3_TPM (0x00 << 6) +#define SBC_IDE_PIO3_TA (0x1A << 0) /* Timing parameters PIO mode 4 */ -#define SBC_IDE_PIO4_TCSOE (0x04<<29) -#define SBC_IDE_PIO4_TOECS (0x01<<26) -#define SBC_IDE_PIO4_TWCS (0x01<<28) -#define SBC_IDE_PIO4_TCSH (0x04<<24) -#define SBC_IDE_PIO4_TCSOFF (0x04<<20) -#define SBC_IDE_PIO4_TWP (0x0D<<14) -#define SBC_IDE_PIO4_TCSW (0x03<<10) -#define SBC_IDE_PIO4_TPM (0x00<<6) -#define SBC_IDE_PIO4_TA (0x12<<0) +#define SBC_IDE_PIO4_TCSOE (0x04 << 29) +#define SBC_IDE_PIO4_TOECS (0x01 << 26) +#define SBC_IDE_PIO4_TWCS (0x01 << 28) +#define SBC_IDE_PIO4_TCSH (0x04 << 24) +#define SBC_IDE_PIO4_TCSOFF (0x04 << 20) +#define SBC_IDE_PIO4_TWP (0x0D << 14) +#define SBC_IDE_PIO4_TCSW (0x03 << 10) +#define SBC_IDE_PIO4_TPM (0x00 << 6) +#define SBC_IDE_PIO4_TA (0x12 << 0) /* Timing parameters MDMA mode 0 */ -#define SBC_IDE_MDMA0_TCSOE (0x03<<29) -#define SBC_IDE_MDMA0_TOECS (0x01<<26) -#define SBC_IDE_MDMA0_TWCS (0x01<<28) -#define SBC_IDE_MDMA0_TCSH (0x07<<24) -#define SBC_IDE_MDMA0_TCSOFF (0x07<<20) -#define SBC_IDE_MDMA0_TWP (0x0C<<14) -#define SBC_IDE_MDMA0_TCSW (0x03<<10) -#define SBC_IDE_MDMA0_TPM (0x00<<6) -#define SBC_IDE_MDMA0_TA (0x0F<<0) +#define SBC_IDE_MDMA0_TCSOE (0x03 << 29) +#define SBC_IDE_MDMA0_TOECS (0x01 << 26) +#define SBC_IDE_MDMA0_TWCS (0x01 << 28) +#define SBC_IDE_MDMA0_TCSH (0x07 << 24) +#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20) +#define SBC_IDE_MDMA0_TWP (0x0C << 14) +#define SBC_IDE_MDMA0_TCSW (0x03 << 10) +#define SBC_IDE_MDMA0_TPM (0x00 << 6) +#define SBC_IDE_MDMA0_TA (0x0F << 0) /* Timing parameters MDMA mode 1 */ -#define SBC_IDE_MDMA1_TCSOE (0x05<<29) -#define SBC_IDE_MDMA1_TOECS (0x01<<26) -#define SBC_IDE_MDMA1_TWCS (0x01<<28) -#define SBC_IDE_MDMA1_TCSH (0x05<<24) -#define SBC_IDE_MDMA1_TCSOFF (0x05<<20) -#define SBC_IDE_MDMA1_TWP (0x0F<<14) -#define SBC_IDE_MDMA1_TCSW (0x05<<10) -#define SBC_IDE_MDMA1_TPM (0x00<<6) -#define SBC_IDE_MDMA1_TA (0x15<<0) +#define SBC_IDE_MDMA1_TCSOE (0x05 << 29) +#define SBC_IDE_MDMA1_TOECS (0x01 << 26) +#define SBC_IDE_MDMA1_TWCS (0x01 << 28) +#define SBC_IDE_MDMA1_TCSH (0x05 << 24) +#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20) +#define SBC_IDE_MDMA1_TWP (0x0F << 14) +#define SBC_IDE_MDMA1_TCSW (0x05 << 10) +#define SBC_IDE_MDMA1_TPM (0x00 << 6) +#define SBC_IDE_MDMA1_TA (0x15 << 0) /* Timing parameters MDMA mode 2 */ -#define SBC_IDE_MDMA2_TCSOE (0x04<<29) -#define SBC_IDE_MDMA2_TOECS (0x01<<26) -#define SBC_IDE_MDMA2_TWCS (0x01<<28) -#define SBC_IDE_MDMA2_TCSH (0x04<<24) -#define SBC_IDE_MDMA2_TCSOFF (0x04<<20) -#define SBC_IDE_MDMA2_TWP (0x0D<<14) -#define SBC_IDE_MDMA2_TCSW (0x04<<10) -#define SBC_IDE_MDMA2_TPM (0x00<<6) -#define SBC_IDE_MDMA2_TA (0x12<<0) +#define SBC_IDE_MDMA2_TCSOE (0x04 << 29) +#define SBC_IDE_MDMA2_TOECS (0x01 << 26) +#define SBC_IDE_MDMA2_TWCS (0x01 << 28) +#define SBC_IDE_MDMA2_TCSH (0x04 << 24) +#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20) +#define SBC_IDE_MDMA2_TWP (0x0D << 14) +#define SBC_IDE_MDMA2_TCSW (0x04 << 10) +#define SBC_IDE_MDMA2_TPM (0x00 << 6) +#define SBC_IDE_MDMA2_TA (0x12 << 0) #define SBC_IDE_TIMING(mode) \ - SBC_IDE_##mode##_TWCS | \ - SBC_IDE_##mode##_TCSH | \ - SBC_IDE_##mode##_TCSOFF | \ - SBC_IDE_##mode##_TWP | \ - SBC_IDE_##mode##_TCSW | \ - SBC_IDE_##mode##_TPM | \ - SBC_IDE_##mode##_TA + (SBC_IDE_##mode##_TWCS | \ + SBC_IDE_##mode##_TCSH | \ + SBC_IDE_##mode##_TCSOFF | \ + SBC_IDE_##mode##_TWP | \ + SBC_IDE_##mode##_TCSW | \ + SBC_IDE_##mode##_TPM | \ + SBC_IDE_##mode##_TA) diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h index 1bd4e27caf6b..dae4eca2417e 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h @@ -33,7 +33,6 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ - /* The PSC base addresses. */ #ifdef CONFIG_SOC_AU1550 #define PSC0_BASE_ADDR 0xb1a00000 @@ -47,8 +46,8 @@ #define PSC1_BASE_ADDR 0xb1b00000 #endif -/* The PSC select and control registers are common to - * all protocols. +/* + * The PSC select and control registers are common to all protocols. */ #define PSC_SEL_OFFSET 0x00000000 #define PSC_CTRL_OFFSET 0x00000004 @@ -59,18 +58,17 @@ #define PSC_SEL_CLK_SERCLK (2 << 4) #define PSC_SEL_PS_MASK 0x00000007 -#define PSC_SEL_PS_DISABLED (0) -#define PSC_SEL_PS_SPIMODE (2) -#define PSC_SEL_PS_I2SMODE (3) -#define PSC_SEL_PS_AC97MODE (4) -#define PSC_SEL_PS_SMBUSMODE (5) - -#define PSC_CTRL_DISABLE (0) -#define PSC_CTRL_SUSPEND (2) -#define PSC_CTRL_ENABLE (3) - -/* AC97 Registers. -*/ +#define PSC_SEL_PS_DISABLED 0 +#define PSC_SEL_PS_SPIMODE 2 +#define PSC_SEL_PS_I2SMODE 3 +#define PSC_SEL_PS_AC97MODE 4 +#define PSC_SEL_PS_SMBUSMODE 5 + +#define PSC_CTRL_DISABLE 0 +#define PSC_CTRL_SUSPEND 2 +#define PSC_CTRL_ENABLE 3 + +/* AC97 Registers. */ #define PSC_AC97CFG_OFFSET 0x00000008 #define PSC_AC97MSK_OFFSET 0x0000000c #define PSC_AC97PCR_OFFSET 0x00000010 @@ -95,8 +93,7 @@ #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) -/* AC97 Config Register. -*/ +/* AC97 Config Register. */ #define PSC_AC97CFG_RT_MASK (3 << 30) #define PSC_AC97CFG_RT_FIFO1 (0 << 30) #define PSC_AC97CFG_RT_FIFO2 (1 << 30) @@ -118,20 +115,19 @@ #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) #define PSC_AC97CFG_GE_ENABLE (1) -/* Enable slots 3-12. -*/ +/* Enable slots 3-12. */ #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) -/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. +/* + * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the * arithmetic in the macro. */ -#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21) +#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) -/* AC97 Mask Register. -*/ +/* AC97 Mask Register. */ #define PSC_AC97MSK_GR (1 << 25) #define PSC_AC97MSK_CD (1 << 24) #define PSC_AC97MSK_RR (1 << 13) @@ -148,8 +144,7 @@ PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ PSC_AC97MSK_RD | PSC_AC97MSK_TD) -/* AC97 Protocol Control Register. -*/ +/* AC97 Protocol Control Register. */ #define PSC_AC97PCR_RC (1 << 6) #define PSC_AC97PCR_RP (1 << 5) #define PSC_AC97PCR_RS (1 << 4) @@ -157,8 +152,7 @@ #define PSC_AC97PCR_TP (1 << 1) #define PSC_AC97PCR_TS (1 << 0) -/* AC97 Status register (read only). -*/ +/* AC97 Status register (read only). */ #define PSC_AC97STAT_CB (1 << 26) #define PSC_AC97STAT_CP (1 << 25) #define PSC_AC97STAT_CR (1 << 24) @@ -174,8 +168,7 @@ #define PSC_AC97STAT_DR (1 << 1) #define PSC_AC97STAT_SR (1 << 0) -/* AC97 Event Register. -*/ +/* AC97 Event Register. */ #define PSC_AC97EVNT_GR (1 << 25) #define PSC_AC97EVNT_CD (1 << 24) #define PSC_AC97EVNT_RR (1 << 13) @@ -187,22 +180,18 @@ #define PSC_AC97EVNT_RD (1 << 5) #define PSC_AC97EVNT_TD (1 << 4) -/* CODEC Command Register. -*/ +/* CODEC Command Register. */ #define PSC_AC97CDC_RD (1 << 25) #define PSC_AC97CDC_ID_MASK (3 << 23) #define PSC_AC97CDC_INDX_MASK (0x7f << 16) -#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23) +#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) -/* AC97 Reset Control Register. -*/ +/* AC97 Reset Control Register. */ #define PSC_AC97RST_RST (1 << 1) #define PSC_AC97RST_SNC (1 << 0) - -/* PSC in I2S Mode. -*/ +/* PSC in I2S Mode. */ typedef struct psc_i2s { u32 psc_sel; u32 psc_ctrl; @@ -215,8 +204,7 @@ typedef struct psc_i2s { u32 psc_i2sudf; } psc_i2s_t; -/* I2S Config Register. -*/ +/* I2S Config Register. */ #define PSC_I2SCFG_RT_MASK (3 << 30) #define PSC_I2SCFG_RT_FIFO1 (0 << 30) #define PSC_I2SCFG_RT_FIFO2 (1 << 30) @@ -247,8 +235,7 @@ typedef struct psc_i2s { #define PSC_I2SCFG_MLJ (1 << 10) #define PSC_I2SCFG_XM (1 << 9) -/* The word length equation is simply LEN+1. - */ +/* The word length equation is simply LEN+1. */ #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) @@ -256,8 +243,7 @@ typedef struct psc_i2s { #define PSC_I2SCFG_MLF (1 << 1) #define PSC_I2SCFG_MS (1 << 0) -/* I2S Mask Register. -*/ +/* I2S Mask Register. */ #define PSC_I2SMSK_RR (1 << 13) #define PSC_I2SMSK_RO (1 << 12) #define PSC_I2SMSK_RU (1 << 11) @@ -271,8 +257,7 @@ typedef struct psc_i2s { PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ PSC_I2SMSK_RD | PSC_I2SMSK_TD) -/* I2S Protocol Control Register. -*/ +/* I2S Protocol Control Register. */ #define PSC_I2SPCR_RC (1 << 6) #define PSC_I2SPCR_RP (1 << 5) #define PSC_I2SPCR_RS (1 << 4) @@ -280,8 +265,7 @@ typedef struct psc_i2s { #define PSC_I2SPCR_TP (1 << 1) #define PSC_I2SPCR_TS (1 << 0) -/* I2S Status register (read only). -*/ +/* I2S Status register (read only). */ #define PSC_I2SSTAT_RF (1 << 13) #define PSC_I2SSTAT_RE (1 << 12) #define PSC_I2SSTAT_RR (1 << 11) @@ -294,8 +278,7 @@ typedef struct psc_i2s { #define PSC_I2SSTAT_DR (1 << 1) #define PSC_I2SSTAT_SR (1 << 0) -/* I2S Event Register. -*/ +/* I2S Event Register. */ #define PSC_I2SEVNT_RR (1 << 13) #define PSC_I2SEVNT_RO (1 << 12) #define PSC_I2SEVNT_RU (1 << 11) @@ -305,8 +288,7 @@ typedef struct psc_i2s { #define PSC_I2SEVNT_RD (1 << 5) #define PSC_I2SEVNT_TD (1 << 4) -/* PSC in SPI Mode. -*/ +/* PSC in SPI Mode. */ typedef struct psc_spi { u32 psc_sel; u32 psc_ctrl; @@ -318,8 +300,7 @@ typedef struct psc_spi { u32 psc_spitxrx; } psc_spi_t; -/* SPI Config Register. -*/ +/* SPI Config Register. */ #define PSC_SPICFG_RT_MASK (3 << 30) #define PSC_SPICFG_RT_FIFO1 (0 << 30) #define PSC_SPICFG_RT_FIFO2 (1 << 30) @@ -355,8 +336,7 @@ typedef struct psc_spi { #define PSC_SPICFG_MLF (1 << 1) #define PSC_SPICFG_MO (1 << 0) -/* SPI Mask Register. -*/ +/* SPI Mask Register. */ #define PSC_SPIMSK_MM (1 << 16) #define PSC_SPIMSK_RR (1 << 13) #define PSC_SPIMSK_RO (1 << 12) @@ -371,16 +351,14 @@ typedef struct psc_spi { PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ PSC_SPIMSK_MD) -/* SPI Protocol Control Register. -*/ +/* SPI Protocol Control Register. */ #define PSC_SPIPCR_RC (1 << 6) #define PSC_SPIPCR_SP (1 << 5) #define PSC_SPIPCR_SS (1 << 4) #define PSC_SPIPCR_TC (1 << 2) #define PSC_SPIPCR_MS (1 << 0) -/* SPI Status register (read only). -*/ +/* SPI Status register (read only). */ #define PSC_SPISTAT_RF (1 << 13) #define PSC_SPISTAT_RE (1 << 12) #define PSC_SPISTAT_RR (1 << 11) @@ -393,8 +371,7 @@ typedef struct psc_spi { #define PSC_SPISTAT_DR (1 << 1) #define PSC_SPISTAT_SR (1 << 0) -/* SPI Event Register. -*/ +/* SPI Event Register. */ #define PSC_SPIEVNT_MM (1 << 16) #define PSC_SPIEVNT_RR (1 << 13) #define PSC_SPIEVNT_RO (1 << 12) @@ -405,13 +382,11 @@ typedef struct psc_spi { #define PSC_SPIEVNT_SD (1 << 5) #define PSC_SPIEVNT_MD (1 << 4) -/* Transmit register control. -*/ +/* Transmit register control. */ #define PSC_SPITXRX_LC (1 << 29) #define PSC_SPITXRX_SR (1 << 28) -/* PSC in SMBus (I2C) Mode. -*/ +/* PSC in SMBus (I2C) Mode. */ typedef struct psc_smb { u32 psc_sel; u32 psc_ctrl; @@ -424,8 +399,7 @@ typedef struct psc_smb { u32 psc_smbtmr; } psc_smb_t; -/* SMBus Config Register. -*/ +/* SMBus Config Register. */ #define PSC_SMBCFG_RT_MASK (3 << 30) #define PSC_SMBCFG_RT_FIFO1 (0 << 30) #define PSC_SMBCFG_RT_FIFO2 (1 << 30) @@ -452,8 +426,7 @@ typedef struct psc_smb { #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) -/* SMBus Mask Register. -*/ +/* SMBus Mask Register. */ #define PSC_SMBMSK_DN (1 << 30) #define PSC_SMBMSK_AN (1 << 29) #define PSC_SMBMSK_AL (1 << 28) @@ -471,13 +444,11 @@ typedef struct psc_smb { PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ PSC_SMBMSK_MD) -/* SMBus Protocol Control Register. -*/ +/* SMBus Protocol Control Register. */ #define PSC_SMBPCR_DC (1 << 2) #define PSC_SMBPCR_MS (1 << 0) -/* SMBus Status register (read only). -*/ +/* SMBus Status register (read only). */ #define PSC_SMBSTAT_BB (1 << 28) #define PSC_SMBSTAT_RF (1 << 13) #define PSC_SMBSTAT_RE (1 << 12) @@ -491,8 +462,7 @@ typedef struct psc_smb { #define PSC_SMBSTAT_DR (1 << 1) #define PSC_SMBSTAT_SR (1 << 0) -/* SMBus Event Register. -*/ +/* SMBus Event Register. */ #define PSC_SMBEVNT_DN (1 << 30) #define PSC_SMBEVNT_AN (1 << 29) #define PSC_SMBEVNT_AL (1 << 28) @@ -510,15 +480,13 @@ typedef struct psc_smb { PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ PSC_SMBEVNT_MD) -/* Transmit register control. -*/ +/* Transmit register control. */ #define PSC_SMBTXRX_RSR (1 << 28) #define PSC_SMBTXRX_STP (1 << 29) -#define PSC_SMBTXRX_DATAMASK (0xff) +#define PSC_SMBTXRX_DATAMASK 0xff -/* SMBus protocol timers register. -*/ -#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30) +/* SMBus protocol timers register. */ +#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) @@ -526,5 +494,4 @@ typedef struct psc_smb { #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) - #endif /* _AU1000_PSC_H_ */ -- cgit v1.2.3 From abd14cc00d940b8b5b4fc92be23f656b57c6ecfe Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:25:04 +0400 Subject: [MIPS] DBAu1xx0 code style cleanup Fix several errors and warnings given by checkpatch.pl: - macros with complex values not enclosed in parentheses; - leading spaces instead of tabs; - printk() without KERN_* facility level; - using simple_strtol() where strict_strtol() could be used; - line over 80 characters. In addition to these changes, also do the following: - initialize variable instead of assigning value later where it makes sense; - insert spaces between operator and its operands, also remove excess spaces there; - remove unneeded numeric literal type casts; - remove needless parentheses; - remove space after the type cast's closing parenthesis; - insert missing space before closing brace in the array initializers; - replace spaces after the macro name with tabs in the #define directives; - remove excess tabs after the macro name in the #define directives; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first/last line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-db1x00/db1x00.h | 83 ++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index e7a88ba35833..612ae90dbcb8 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -1,9 +1,8 @@ /* - * AMD Alchemy DB1x00 Reference Boards + * AMD Alchemy DBAu1x00 Reference Boards * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) * * ######################################################################## @@ -32,26 +31,26 @@ #ifdef CONFIG_MIPS_DB1550 -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR +#define SPI_PSC_BASE PSC0_BASE_ADDR +#define AC97_PSC_BASE PSC1_BASE_ADDR +#define SMBUS_PSC_BASE PSC2_BASE_ADDR +#define I2S_PSC_BASE PSC3_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xAF000000 -#define NAND_PHYS_ADDR 0x20000000 +#define BCSR_KSEG1_ADDR 0xAF000000 +#define NAND_PHYS_ADDR 0x20000000 #else #define BCSR_KSEG1_ADDR 0xAE000000 #endif /* - * Overlay data structure of the Db1x00 board registers. - * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx + * Overlay data structure of the DBAu1x00 board registers. + * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx. */ typedef volatile struct { @@ -138,18 +137,19 @@ typedef volatile struct #define BCSR_SWRESET_RESET 0x0080 -/* PCMCIA Db1x00 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) +/* PCMCIA DBAu1x00 specific defines */ +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) /* VPP/VCC */ #define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) + ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -/* SD controller macros */ /* - * Detect card. + * SD controller macros */ + +/* Detect card. */ #define mmc_card_inserted(_n_, _res_) \ do { \ BCSR * const bcsr = (BCSR *)0xAE000000; \ @@ -176,10 +176,10 @@ typedef volatile struct unsigned long mmc_pwr, mmc_wp, board_specific; \ if ((_n_)) { \ mmc_pwr = BCSR_BOARD_SD1_PWR; \ - mmc_wp = BCSR_BOARD_SD1_WP; \ + mmc_wp = BCSR_BOARD_SD1_WP; \ } else { \ mmc_pwr = BCSR_BOARD_SD0_PWR; \ - mmc_wp = BCSR_BOARD_SD0_WP; \ + mmc_wp = BCSR_BOARD_SD0_WP; \ } \ board_specific = au_readl((unsigned long)(&bcsr->specific)); \ if (!(board_specific & mmc_wp)) {/* low means card present */ \ @@ -190,17 +190,19 @@ typedef volatile struct } while (0) -/* NAND defines */ -/* Timing values as described in databook, * ns value stripped of +/* + * NAND defines + * + * Timing values as described in databook, * ns value stripped of the * lower 2 bits. - * These defines are here rather than an SOC1550 generic file because + * These defines are here rather than an Au1550 generic file because * the parts chosen on another board may be different and may require * different timings. */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) +#define NAND_T_H (18 >> 2) +#define NAND_T_PUL (30 >> 2) +#define NAND_T_SU (30 >> 2) +#define NAND_T_WH (30 >> 2) /* Bitfield shift amounts */ #define NAND_T_H_SHIFT 0 @@ -208,16 +210,15 @@ typedef volatile struct #define NAND_T_SU_SHIFT 8 #define NAND_T_WH_SHIFT 12 -#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) -#define NAND_CS 1 +#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) +#define NAND_CS 1 -/* should be done by yamon */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ +/* Should be done by YAMON */ +#define NAND_STCFG 0x00400005 /* 8-bit NAND */ +#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ +#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ #endif /* __ASM_DB1X00_H */ - -- cgit v1.2.3 From 7916c3548e53bffb0545a1d0dc7fde86d79add92 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:25:55 +0400 Subject: [MIPS] Pb1000 code style cleanup Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - brace not on the same line with condition in the 'switch' statement; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - properly indent the 'switch' statement; - remove needless parentheses; - insert spaces between operator and its operands; - replace numeric literals/expressions with the matching macros; - remove useless #if dirctive from board_setup(); - remove unneeded numeric literal type casts; - remove space after the type cast's closing parenthesis; - replace spaces after the macro name with tabs in the #define directives, and sometimes insert spaces there; - remove excess new lines; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first/last line; - combine some comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-pb1x00/pb1000.h | 189 ++++++++++------------------------ 1 file changed, 52 insertions(+), 137 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h index b52e0e7ee3fb..6d1ff9060e44 100644 --- a/include/asm-mips/mach-pb1x00/pb1000.h +++ b/include/asm-mips/mach-pb1x00/pb1000.h @@ -1,9 +1,8 @@ /* - * Alchemy Semi PB1000 Referrence Board + * Alchemy Semi Pb1000 Referrence Board * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * ######################################################################## * @@ -28,145 +27,61 @@ #define __ASM_PB1000_H /* PCMCIA PB1000 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) - -#define PB1000_PCR 0xBE000000 -# define PCR_SLOT_0_VPP0 (1<<0) -# define PCR_SLOT_0_VPP1 (1<<1) -# define PCR_SLOT_0_VCC0 (1<<2) -# define PCR_SLOT_0_VCC1 (1<<3) -# define PCR_SLOT_0_RST (1<<4) - -# define PCR_SLOT_1_VPP0 (1<<8) -# define PCR_SLOT_1_VPP1 (1<<9) -# define PCR_SLOT_1_VCC0 (1<<10) -# define PCR_SLOT_1_VCC1 (1<<11) -# define PCR_SLOT_1_RST (1<<12) - -#define PB1000_MDR 0xBE000004 -# define MDR_PI (1<<5) /* pcmcia int latch */ -# define MDR_EPI (1<<14) /* enable pcmcia int */ -# define MDR_CPI (1<<15) /* clear pcmcia int */ - -#define PB1000_ACR1 0xBE000008 -# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ -# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ -# define ACR1_SLOT_0_READY (1<<2) /* ready */ -# define ACR1_SLOT_0_STATUS (1<<3) /* status change */ -# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ -# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ -# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ -# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ -# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ -# define ACR1_SLOT_1_READY (1<<10) /* ready */ -# define ACR1_SLOT_1_STATUS (1<<11) /* status change */ -# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ -# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ -# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ - -#define CPLD_AUX0 0xBE00000C -#define CPLD_AUX1 0xBE000010 -#define CPLD_AUX2 0xBE000014 +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) + +#define PB1000_PCR 0xBE000000 +# define PCR_SLOT_0_VPP0 (1 << 0) +# define PCR_SLOT_0_VPP1 (1 << 1) +# define PCR_SLOT_0_VCC0 (1 << 2) +# define PCR_SLOT_0_VCC1 (1 << 3) +# define PCR_SLOT_0_RST (1 << 4) +# define PCR_SLOT_1_VPP0 (1 << 8) +# define PCR_SLOT_1_VPP1 (1 << 9) +# define PCR_SLOT_1_VCC0 (1 << 10) +# define PCR_SLOT_1_VCC1 (1 << 11) +# define PCR_SLOT_1_RST (1 << 12) + +#define PB1000_MDR 0xBE000004 +# define MDR_PI (1 << 5) /* PCMCIA int latch */ +# define MDR_EPI (1 << 14) /* enable PCMCIA int */ +# define MDR_CPI (1 << 15) /* clear PCMCIA int */ + +#define PB1000_ACR1 0xBE000008 +# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */ +# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */ +# define ACR1_SLOT_0_READY (1 << 2) /* ready */ +# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */ +# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */ +# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */ +# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */ +# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */ +# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */ +# define ACR1_SLOT_1_READY (1 << 10) /* ready */ +# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */ +# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */ +# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */ +# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */ + +#define CPLD_AUX0 0xBE00000C +#define CPLD_AUX1 0xBE000010 +#define CPLD_AUX2 0xBE000014 /* Voltage levels */ /* VPPEN1 - VPPEN0 */ -#define VPP_GND ((0<<1) | (0<<0)) -#define VPP_5V ((1<<1) | (0<<0)) -#define VPP_3V ((0<<1) | (1<<0)) -#define VPP_12V ((0<<1) | (1<<0)) -#define VPP_HIZ ((1<<1) | (1<<0)) +#define VPP_GND ((0 << 1) | (0 << 0)) +#define VPP_5V ((1 << 1) | (0 << 0)) +#define VPP_3V ((0 << 1) | (1 << 0)) +#define VPP_12V ((0 << 1) | (1 << 0)) +#define VPP_HIZ ((1 << 1) | (1 << 0)) /* VCCEN1 - VCCEN0 */ -#define VCC_3V ((0<<1) | (1<<0)) -#define VCC_5V ((1<<1) | (0<<0)) -#define VCC_HIZ ((0<<1) | (0<<0)) +#define VCC_3V ((0 << 1) | (1 << 0)) +#define VCC_5V ((1 << 1) | (0 << 0)) +#define VCC_HIZ ((0 << 1) | (0 << 0)) /* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) - - -/* PCI PB1000 specific defines */ -/* The reason these defines are here instead of au1000.h is because - * the Au1000 does not have a PCI bus controller so the PCI implementation - * on the some of the older Pb1000 boards was very board specific. - */ -#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */ - -#define SDRAM_DEVID 0xBA010000 -#define SDRAM_CMD 0xBA010004 -#define SDRAM_CLASS 0xBA010008 -#define SDRAM_MISC 0xBA01000C -#define SDRAM_MBAR 0xBA010010 - -#define PCI_IO_DATA_PORT 0xBA800000 - -#define PCI_IO_ADDR 0xBE00001C -#define PCI_INT_ACK 0xBBC00000 -#define PCI_IO_READ 0xBBC00020 -#define PCI_IO_WRITE 0xBBC00030 - -#define PCI_BRIDGE_CONFIG 0xBE000018 - -#define PCI_IO_START 0x10000000 -#define PCI_IO_END 0x1000ffff -#define PCI_MEM_START 0x18000000 -#define PCI_MEM_END 0x18ffffff - -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 1 - -static inline u8 au_pci_io_readb(u32 addr) -{ - writel(addr, PCI_IO_ADDR); - writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG); - return (readl(PCI_IO_DATA_PORT) & 0xff); -} - -static inline u16 au_pci_io_readw(u32 addr) -{ - writel(addr, PCI_IO_ADDR); - writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG); - return (readl(PCI_IO_DATA_PORT) & 0xffff); -} - -static inline u32 au_pci_io_readl(u32 addr) -{ - writel(addr, PCI_IO_ADDR); - writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG); - return readl(PCI_IO_DATA_PORT); -} - -static inline void au_pci_io_writeb(u8 val, u32 addr) -{ - writel(addr, PCI_IO_ADDR); - writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG); - writel(val, PCI_IO_DATA_PORT); -} - -static inline void au_pci_io_writew(u16 val, u32 addr) -{ - writel(addr, PCI_IO_ADDR); - writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG); - writel(val, PCI_IO_DATA_PORT); -} - -static inline void au_pci_io_writel(u32 val, u32 addr) -{ - writel(addr, PCI_IO_ADDR); - writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG); - writel(val, PCI_IO_DATA_PORT); -} - -static inline void set_sdram_extbyte(void) -{ - writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG); -} - -static inline void set_slot_extbyte(void) -{ - writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG); -} +#define SET_VCC_VPP(VCC, VPP, SLOT) \ + ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) #endif /* __ASM_PB1000_H */ -- cgit v1.2.3 From be1c3c1ed13f31ae8f9d5d043d96d2e56b5ee1d5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:26:28 +0400 Subject: [MIPS] Pb1100 code style cleanup Fix several errors and warnings given by checkpatch.pl: - space between asterisk and variable name; - use of C99 // comments; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - properly indent the code; - remove space after the type cast's closing parenthesis; - replace numeric literals/expressions with the matching macros; - replace spaces after the macro name with tabs in the #define directives, and sometimes insert spaces there; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-pb1x00/pb1100.h | 96 +++++++++++++++++------------------ 1 file changed, 48 insertions(+), 48 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h index 63aa3926b297..b1a60f1cbd02 100644 --- a/include/asm-mips/mach-pb1x00/pb1100.h +++ b/include/asm-mips/mach-pb1x00/pb1100.h @@ -1,9 +1,8 @@ /* - * Alchemy Semi PB1100 Referrence Board + * Alchemy Semi Pb1100 Referrence Board * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * ######################################################################## * @@ -27,59 +26,60 @@ #ifndef __ASM_PB1100_H #define __ASM_PB1100_H -#define PB1100_IDENT 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -# define PB1100_ROM_SEL (1<<15) -# define PB1100_ROM_SIZ (1<<14) -# define PB1100_SWAP_BOOT (1<<13) -# define PB1100_FLASH_WP (1<<12) -# define PB1100_ROM_H_STS (1<<11) -# define PB1100_ROM_L_STS (1<<10) -# define PB1100_FLASH_H_STS (1<<9) -# define PB1100_FLASH_L_STS (1<<8) -# define PB1100_SRAM_SIZ (1<<7) -# define PB1100_TSC_BUSY (1<<6) -# define PB1100_PCMCIA_VS_MASK (3<<4) -# define PB1100_RS232_CD (1<<3) -# define PB1100_RS232_CTS (1<<2) -# define PB1100_RS232_DSR (1<<1) -# define PB1100_RS232_RI (1<<0) +#define PB1100_IDENT 0xAE000000 +#define BOARD_STATUS_REG 0xAE000004 +# define PB1100_ROM_SEL (1 << 15) +# define PB1100_ROM_SIZ (1 << 14) +# define PB1100_SWAP_BOOT (1 << 13) +# define PB1100_FLASH_WP (1 << 12) +# define PB1100_ROM_H_STS (1 << 11) +# define PB1100_ROM_L_STS (1 << 10) +# define PB1100_FLASH_H_STS (1 << 9) +# define PB1100_FLASH_L_STS (1 << 8) +# define PB1100_SRAM_SIZ (1 << 7) +# define PB1100_TSC_BUSY (1 << 6) +# define PB1100_PCMCIA_VS_MASK (3 << 4) +# define PB1100_RS232_CD (1 << 3) +# define PB1100_RS232_CTS (1 << 2) +# define PB1100_RS232_DSR (1 << 1) +# define PB1100_RS232_RI (1 << 0) -#define PB1100_IRDA_RS232 0xAE00000C -# define PB1100_IRDA_FULL (0<<14) /* full power */ -# define PB1100_IRDA_SHUTDOWN (1<<14) -# define PB1100_IRDA_TT (2<<14) /* 2/3 power */ -# define PB1100_IRDA_OT (3<<14) /* 1/3 power */ -# define PB1100_IRDA_FIR (1<<13) +#define PB1100_IRDA_RS232 0xAE00000C +# define PB1100_IRDA_FULL (0 << 14) /* full power */ +# define PB1100_IRDA_SHUTDOWN (1 << 14) +# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */ +# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */ +# define PB1100_IRDA_FIR (1 << 13) -#define PCMCIA_BOARD_REG 0xAE000010 -# define PB1100_SD_WP1_RO (1<<15) /* read only */ -# define PB1100_SD_WP0_RO (1<<14) /* read only */ -# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ -# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ -# define PB1100_SEL_SD_CONN1 (1<<9) -# define PB1100_SEL_SD_CONN0 (1<<8) -# define PC_DEASSERT_RST (1<<7) -# define PC_DRV_EN (1<<4) +#define PCMCIA_BOARD_REG 0xAE000010 +# define PB1100_SD_WP1_RO (1 << 15) /* read only */ +# define PB1100_SD_WP0_RO (1 << 14) /* read only */ +# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */ +# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */ +# define PB1100_SEL_SD_CONN1 (1 << 9) +# define PB1100_SEL_SD_CONN0 (1 << 8) +# define PC_DEASSERT_RST (1 << 7) +# define PC_DRV_EN (1 << 4) -#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ +#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ -#define PB1100_RST_VDDI 0xAE00001C -# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ -# define PB1100_VDDI_MASK (0x1F) +#define PB1100_RST_VDDI 0xAE00001C +# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */ +# define PB1100_VDDI_MASK 0x1F -#define PB1100_LEDS 0xAE000018 +#define PB1100_LEDS 0xAE000018 -/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. - * 7:0 is the LED Display's decimal points. +/* + * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. + * 7:0 is the LED Display's decimal points. */ -#define PB1100_HEX_LED 0xAE000018 +#define PB1100_HEX_LED 0xAE000018 -/* PCMCIA PB1100 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) +/* PCMCIA Pb1100 specific defines */ +#define PCMCIA_MAX_SOCK 0 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) /* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) +#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) #endif /* __ASM_PB1100_H */ -- cgit v1.2.3 From 2091a17ff7f32432976d1eacbb79a06819d95301 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:27:20 +0400 Subject: [MIPS] Pb1500 code style cleanup Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - replace numeric literals/expressions with the matching macros; - insert spaces between operator and its operands; - properly indent the code and the array initializers; - remove useless #if dirctive from board_setup(); - remove needless parentheses; - remove unneeded type casts; - remove excess new lines; - make hexadecimal literals all lower case; - remove space after the type cast's closing parenthesis; - insert missing space before closing brace in the array initializers; - replace spaces after the macro name with tabs in the #define directives, also sometimes insert space there for better looks; - fix typos/errors, capitalize acronyms, etc. in the comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-pb1x00/pb1500.h | 38 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h index ff6d40c87a25..da51a2eb7b82 100644 --- a/include/asm-mips/mach-pb1x00/pb1500.h +++ b/include/asm-mips/mach-pb1x00/pb1500.h @@ -1,9 +1,8 @@ /* - * Alchemy Semi PB1500 Referrence Board + * Alchemy Semi Pb1500 Referrence Board * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * ######################################################################## * @@ -27,25 +26,24 @@ #ifndef __ASM_PB1500_H #define __ASM_PB1500_H +#define IDENT_BOARD_REG 0xAE000000 +#define BOARD_STATUS_REG 0xAE000004 +#define PCI_BOARD_REG 0xAE000010 +#define PCMCIA_BOARD_REG 0xAE000010 +# define PC_DEASSERT_RST 0x80 +# define PC_DRV_EN 0x10 +#define PB1500_G_CONTROL 0xAE000014 +#define PB1500_RST_VDDI 0xAE00001C +#define PB1500_LEDS 0xAE000018 -#define IDENT_BOARD_REG 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -#define PCI_BOARD_REG 0xAE000010 -#define PCMCIA_BOARD_REG 0xAE000010 - #define PC_DEASSERT_RST 0x80 - #define PC_DRV_EN 0x10 -#define PB1500_G_CONTROL 0xAE000014 -#define PB1500_RST_VDDI 0xAE00001C -#define PB1500_LEDS 0xAE000018 +#define PB1500_HEX_LED 0xAF000004 +#define PB1500_HEX_LED_BLANK 0xAF000008 -#define PB1500_HEX_LED 0xAF000004 -#define PB1500_HEX_LED_BLANK 0xAF000008 - -/* PCMCIA PB1500 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) +/* PCMCIA Pb1500 specific defines */ +#define PCMCIA_MAX_SOCK 0 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) /* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) +#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) #endif /* __ASM_PB1500_H */ -- cgit v1.2.3 From 6afabe6c9335c0534224b53c3db4b091621af2dd Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:28:17 +0400 Subject: [MIPS] Pb1550 code style cleanup Fix a few errors and warnings given by checkpatch.pl: - macros with complex values not enclosed in parentheses; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - replace numeric literals with the matching macros; - properly indent the code and the array initializers; - insert spaces between operator and its operands, also remove excess spaces there; - remove space after the type cast's closing parenthesis; - insert missing space before closing brace in the array initializers; - replace spaces after the macro name with tabs in the #define directives, also sometimes insert space there for better looks; - remove excess tabs after the macro name in the #define directives; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-pb1x00/pb1550.h | 51 ++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h index c2ab0e2df4ae..6704a11497db 100644 --- a/include/asm-mips/mach-pb1x00/pb1550.h +++ b/include/asm-mips/mach-pb1x00/pb1550.h @@ -30,15 +30,15 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR +#define SPI_PSC_BASE PSC0_BASE_ADDR +#define AC97_PSC_BASE PSC1_BASE_ADDR +#define SMBUS_PSC_BASE PSC2_BASE_ADDR +#define I2S_PSC_BASE PSC3_BASE_ADDR #define BCSR_PHYS_ADDR 0xAF000000 @@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; #define BCSR_SYSTEM_POWEROFF 0x4000 #define BCSR_SYSTEM_RESET 0x8000 -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) /* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) +#define SET_VCC_VPP(VCC, VPP, SLOT) \ + ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) #define PB1550_BOTH_BANKS @@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; #define PB1550_USER_ONLY #endif -/* Timing values as described in databook, * ns value stripped of +/* + * Timing values as described in databook, * ns value stripped of * lower 2 bits. * These defines are here rather than an SOC1550 generic file because * the parts chosen on another board may be different and may require * different timings. */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) +#define NAND_T_H (18 >> 2) +#define NAND_T_PUL (30 >> 2) +#define NAND_T_SU (30 >> 2) +#define NAND_T_WH (30 >> 2) /* Bitfield shift amounts */ #define NAND_T_H_SHIFT 0 @@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; #define NAND_T_SU_SHIFT 8 #define NAND_T_WH_SHIFT 12 -#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) +#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) #define NAND_CS 1 -/* should be done by yamon */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ +/* Should be done by YAMON */ +#define NAND_STCFG 0x00400005 /* 8-bit NAND */ +#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ +#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ #endif /* __ASM_PB1550_H */ -- cgit v1.2.3 From c3d1d5c8c10c937c65186f6dac75e2fb4675ef07 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 30 Apr 2008 23:29:04 +0400 Subject: [MIPS] Pb1200/DBAu1200 code style cleanup Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - initialization of a 'static' variable to 0; - space after opening and before closing parentheses; - missing space between 'for' and opening parenthesis; - macros with complex values not enclosed in parentheses; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used; - line over 80 characters. In addition to these changes, also do the following: - mention DBAu1200 board in the Makefile; - replace the group of #include/#ifdef directives by a single #include since this header contains the needed stuff; - properly indent the blocks; - insert spaces between operator and its operands, remove excess spaces there; - remove needless parentheses and add some for clarity; - replace numeric literals/expressions with the matching macros; - remove space after the type cast's closing parenthesis; - reduce pb1200_setup_cascade() to the single 'return' statement; - reduce the number of printed empty lines in the so-called CPLD workaround; - remove #undef AU1X00_EXTERNAL_INT since that macro is not defined anywhere; - replace spaces after the macro name with tabs in the #define directives; - remove excess tabs after the macro name in the #define directives; - fix typo in the BCSR_RESETS_PWMR1mUX macro's name; - group all Pb1200 PCMCIA definitions together; - put the function's result type and name/parameters on the same line; - insert missing and remove excess new lines; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line and/or adding space/asterisk on their left side; - fix typos/errors, capitalize acronyms, etc. in the comments; - combine some comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-db1x00/db1200.h | 73 +++++++++++++-------------- include/asm-mips/mach-pb1x00/pb1200.h | 93 +++++++++++++++++------------------ 2 files changed, 81 insertions(+), 85 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h index eedd048a7261..27f26102b1bb 100644 --- a/include/asm-mips/mach-db1x00/db1200.h +++ b/include/asm-mips/mach-db1x00/db1200.h @@ -1,6 +1,6 @@ /* - * AMD Alchemy DB1200 Referrence Board - * Board Registers defines. + * AMD Alchemy DBAu1200 Reference Board + * Board register defines. * * ######################################################################## * @@ -27,26 +27,25 @@ #include #include -// This is defined in au1000.h with bogus value -#undef AU1X00_EXTERNAL_INT +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* SPI and SMB are muxed on the Pb1200 board. - Refer to board documentation. +/* + * SPI and SMB are muxed on the DBAu1200 board. + * Refer to board documentation. */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* AC97 and I2S are muxed on the Pb1200 board. - Refer to board documentation. +#define SPI_PSC_BASE PSC0_BASE_ADDR +#define SMBUS_PSC_BASE PSC0_BASE_ADDR +/* + * AC'97 and I2S are muxed on the DBAu1200 board. + * Refer to board documentation. */ -#define AC97_PSC_BASE PSC1_BASE_ADDR +#define AC97_PSC_BASE PSC1_BASE_ADDR #define I2S_PSC_BASE PSC1_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xB9800000 +#define BCSR_KSEG1_ADDR 0xB9800000 typedef volatile struct { @@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_STATUS_SWAPBOOT 0x0040 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 +#define BCSR_STATUS_SD0WP 0x0400 +#define BCSR_STATUS_U0RXD 0x1000 +#define BCSR_STATUS_U1RXD 0x2000 #define BCSR_SWITCHES_OCTAL 0x00FF #define BCSR_SWITCHES_DIP_1 0x0080 @@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_RESETS_DC 0x0004 #define BCSR_RESETS_IDE 0x0008 #define BCSR_RESETS_TV 0x0010 -/* not resets but in the same register */ -#define BCSR_RESETS_PWMR1mUX 0x0800 +/* Not resets but in the same register */ +#define BCSR_RESETS_PWMR1MUX 0x0800 #define BCSR_RESETS_PCS0MUX 0x1000 #define BCSR_RESETS_PCS1MUX 0x2000 #define BCSR_RESETS_SPISEL 0x4000 @@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_INT_PC0STSCHG 0x0008 #define BCSR_INT_PC1 0x0010 #define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 +#define BCSR_INT_DC 0x0040 #define BCSR_INT_FLASHBUSY 0x0080 #define BCSR_INT_PC0INSERT 0x0100 #define BCSR_INT_PC0EJECT 0x0200 @@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 #define IDE_RQSIZE 128 -#define NAND_PHYS_ADDR 0x20000000 +#define NAND_PHYS_ADDR 0x20000000 /* - * External Interrupts for Pb1200 as of 8/6/2004. + * External Interrupts for DBAu1200 as of 8/6/2004. * Bit positions in the CPLD registers can be calculated by taking * the interrupt define and subtracting the DB1200_INT_BEGIN value. * @@ -211,23 +210,21 @@ enum external_pb1200_ints { }; -/* For drivers/pcmcia/au1000_db1x00.c */ - -/* PCMCIA Db1x00 specific defines */ - -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) +/* + * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c + */ +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) /* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) +#define SET_VCC_VPP(VCC, VPP, SLOT) \ + ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -#define BOARD_PC0_INT DB1200_PC0_INT -#define BOARD_PC1_INT DB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) +#define BOARD_PC0_INT DB1200_PC0_INT +#define BOARD_PC1_INT DB1200_PC1_INT +#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) -/* Nand chip select */ +/* NAND chip select */ #define NAND_CS 1 #endif /* __ASM_DB1200_H */ - diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h index e2c6bcac3b42..c8618df88cb5 100644 --- a/include/asm-mips/mach-pb1x00/pb1200.h +++ b/include/asm-mips/mach-pb1x00/pb1200.h @@ -1,5 +1,5 @@ /* - * AMD Alchemy PB1200 Referrence Board + * AMD Alchemy Pb1200 Referrence Board * Board Registers defines. * * ######################################################################## @@ -27,21 +27,20 @@ #include #include -// This is defined in au1000.h with bogus value -#undef AU1X00_EXTERNAL_INT +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* SPI and SMB are muxed on the Pb1200 board. - Refer to board documentation. +/* + * SPI and SMB are muxed on the Pb1200 board. + * Refer to board documentation. */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* AC97 and I2S are muxed on the Pb1200 board. - Refer to board documentation. +#define SPI_PSC_BASE PSC0_BASE_ADDR +#define SMBUS_PSC_BASE PSC0_BASE_ADDR +/* + * AC97 and I2S are muxed on the Pb1200 board. + * Refer to board documentation. */ #define AC97_PSC_BASE PSC1_BASE_ADDR #define I2S_PSC_BASE PSC1_BASE_ADDR @@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_STATUS_SWAPBOOT 0x0040 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_SD1WP 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 +#define BCSR_STATUS_SD0WP 0x0400 +#define BCSR_STATUS_SD1WP 0x0800 +#define BCSR_STATUS_U0RXD 0x1000 +#define BCSR_STATUS_U1RXD 0x2000 #define BCSR_SWITCHES_OCTAL 0x00FF #define BCSR_SWITCHES_DIP_1 0x0080 @@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_RESETS_DC 0x0004 #define BCSR_RESETS_IDE 0x0008 /* not resets but in the same register */ -#define BCSR_RESETS_WSCFSM 0x0800 +#define BCSR_RESETS_WSCFSM 0x0800 #define BCSR_RESETS_PCS0MUX 0x1000 #define BCSR_RESETS_PCS1MUX 0x2000 #define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_SD1MUX 0x8000 +#define BCSR_RESETS_SD1MUX 0x8000 #define BCSR_PCMCIA_PC0VPP 0x0003 #define BCSR_PCMCIA_PC0VCC 0x000C @@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_INT_PC0STSCHG 0x0008 #define BCSR_INT_PC1 0x0010 #define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 +#define BCSR_INT_DC 0x0040 #define BCSR_INT_FLASHBUSY 0x0080 #define BCSR_INT_PC0INSERT 0x0100 #define BCSR_INT_PC0EJECT 0x0200 @@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_INT_SD1INSERT 0x4000 #define BCSR_INT_SD1EJECT 0x8000 -/* PCMCIA Db1x00 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) - #define SMC91C111_PHYS_ADDR 0x0D000300 #define SMC91C111_INT PB1200_ETH_INT @@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 #define IDE_RQSIZE 128 -#define NAND_PHYS_ADDR 0x1C000000 +#define NAND_PHYS_ADDR 0x1C000000 -/* Timing values as described in databook, * ns value stripped of +/* + * Timing values as described in databook, * ns value stripped of * lower 2 bits. - * These defines are here rather than an SOC1200 generic file because + * These defines are here rather than an Au1200 generic file because * the parts chosen on another board may be different and may require * different timings. */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) +#define NAND_T_H (18 >> 2) +#define NAND_T_PUL (30 >> 2) +#define NAND_T_SU (30 >> 2) +#define NAND_T_WH (30 >> 2) /* Bitfield shift amounts */ #define NAND_T_H_SHIFT 0 @@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define NAND_T_SU_SHIFT 8 #define NAND_T_WH_SHIFT 12 -#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) - +#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) /* * External Interrupts for Pb1200 as of 8/6/2004. @@ -248,13 +239,21 @@ enum external_pb1200_ints { PB1200_INT_END = PB1200_INT_BEGIN + 15 }; -/* For drivers/pcmcia/au1000_db1x00.c */ -#define BOARD_PC0_INT PB1200_PC0_INT -#define BOARD_PC1_INT PB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) +/* + * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c + */ +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) -/* Nand chip select */ +/* VPP/VCC */ +#define SET_VCC_VPP(VCC, VPP, SLOT) \ + ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) + +#define BOARD_PC0_INT PB1200_PC0_INT +#define BOARD_PC1_INT PB1200_PC1_INT +#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) + +/* NAND chip select */ #define NAND_CS 1 #endif /* __ASM_PB1200_H */ - -- cgit v1.2.3 From fcd84f2fca49166dab2dba259eca6e633585763f Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sun, 4 May 2008 00:25:02 +0200 Subject: [MIPS] Fix __fls for non-MIPS32/MIPS64 cpus Only MIPS32 and MIPS64 CPUs implement clz/dclz. Therefore don't export __ilog2() for non MIPS32/MIPS64 cpus and use generic __fls bitop code for these cpus. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index c2bd126c3b4e..5e1f590a24a1 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -558,6 +558,8 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * __clear_bit(nr, addr); } +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + /* * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists @@ -596,8 +598,6 @@ static inline unsigned long __fls(unsigned long x) return __ilog2(x); } -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - /* * __ffs - find first bit in word. * @word: The word to search @@ -654,6 +654,7 @@ static inline int ffs(int word) #else #include +#include #include #include #include -- cgit v1.2.3 From ddc0d009947bf8645fa3543f4532063a787202da Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 4 May 2008 14:53:53 +0100 Subject: [MIPS] Get rid of __ilog2 56a6b1eb7bfb5ace0b5cb9c149f502fbd101b8ab was a bit too conservative and left __ilog2 around which is only used as an internal function for other bitops. Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 5e1f590a24a1..642724734eba 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -564,7 +564,7 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ -static inline int __ilog2(unsigned long x) +static inline unsigned long __fls(unsigned long x) { int lz; @@ -593,11 +593,6 @@ static inline int __ilog2(unsigned long x) return 63 - lz; } -static inline unsigned long __fls(unsigned long x) -{ - return __ilog2(x); -} - /* * __ffs - find first bit in word. * @word: The word to search @@ -607,7 +602,7 @@ static inline unsigned long __fls(unsigned long x) */ static inline unsigned long __ffs(unsigned long word) { - return __ilog2(word & -word); + return __fls(word & -word); } /* -- cgit v1.2.3 From 2ccdcfeeca6a1888180ffc4a1ab097f1fb2bd029 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Fri, 9 May 2008 09:46:38 -0700 Subject: types: s390: fix #ifdef reversal in The #ifdef for the integer types was reversed; the standard pattern in these files are: #ifndef __s390x__ /* 32-bit code */ #else /* 64-bit code */ #endif Stick with the original pattern, but make sure the 32-bit code actually comes first! Reported by Al Viro. Signed-off-by: H. Peter Anvin Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: Al Viro --- include/asm-s390/types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-s390/types.h b/include/asm-s390/types.h index 78dda038dd47..0e959e20e9a3 100644 --- a/include/asm-s390/types.h +++ b/include/asm-s390/types.h @@ -10,9 +10,9 @@ #define _S390_TYPES_H #ifndef __s390x__ -# include -#else # include +#else +# include #endif #ifndef __ASSEMBLY__ -- cgit v1.2.3 From 9404ef02974a5411687b6c1b8ef3984305620e02 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Mon, 12 May 2008 10:14:22 -0700 Subject: Fix up 'need_resched()' definition We should not go through the task pointer to get at the thread info, since it's usually cheaper to just access the thread info directly. So don't make the code look up 'current', when we can just use the thread info accessor functions directly. This generally avoids one level of indirection and tends to work better together with code that also looks at other thread flags (eg preempt_count). Signed-off-by: Linus Torvalds --- include/linux/sched.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/sched.h b/include/linux/sched.h index 4ab9f32f9238..5a63f2d72af6 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -2027,7 +2027,7 @@ static inline int fatal_signal_pending(struct task_struct *p) static inline int need_resched(void) { - return unlikely(test_tsk_need_resched(current)); + return unlikely(test_thread_flag(TIF_NEED_RESCHED)); } /* -- cgit v1.2.3 From c714a534d85576af21b06be605ca55cb2fb887ee Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Mon, 12 May 2008 13:34:13 -0700 Subject: Make 'cond_resched()' nullification depend on PREEMPT_BKL Because it's not correct with a non-preemptable BKL and just causes PREEMPT kernels to have longer latencies than non-PREEMPT ones (which is obviously not the point of it at all). Of course, that config option actually got removed as an option earlier, so for now this basically disables it entirely, but if BKL preemption is ever resurrected it will be a meaningful optimization. And in the meantime, it at least documents the intent of the code, while not doing the wrong thing. Signed-off-by: Linus Torvalds --- include/linux/sched.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/sched.h b/include/linux/sched.h index 5a63f2d72af6..5395a6176f4b 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -2038,7 +2038,7 @@ static inline int need_resched(void) * cond_resched_softirq() will enable bhs before scheduling. */ extern int _cond_resched(void); -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPT_BKL static inline int cond_resched(void) { return 0; -- cgit v1.2.3 From 94d149c34cda933ff5096aca94bb23bf68602f4e Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 12 May 2008 16:33:33 -0700 Subject: sparc: Fix mremap address range validation. Just like mmap, we need to validate address ranges regardless of MAP_FIXED. sparc{,64}_mmap_check()'s flag argument is unused, remove. Based upon a report and preliminary patch by Jan Lieskovsky Signed-off-by: David S. Miller --- include/asm-sparc/mman.h | 5 ++--- include/asm-sparc64/mman.h | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-sparc/mman.h b/include/asm-sparc/mman.h index e18be984c01d..3d16b40bb8ef 100644 --- a/include/asm-sparc/mman.h +++ b/include/asm-sparc/mman.h @@ -24,9 +24,8 @@ #ifdef __KERNEL__ #ifndef __ASSEMBLY__ -#define arch_mmap_check sparc_mmap_check -int sparc_mmap_check(unsigned long addr, unsigned long len, - unsigned long flags); +#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len) +int sparc_mmap_check(unsigned long addr, unsigned long len); #endif #endif diff --git a/include/asm-sparc64/mman.h b/include/asm-sparc64/mman.h index e584563b56eb..625be4d61baf 100644 --- a/include/asm-sparc64/mman.h +++ b/include/asm-sparc64/mman.h @@ -24,9 +24,8 @@ #ifdef __KERNEL__ #ifndef __ASSEMBLY__ -#define arch_mmap_check sparc64_mmap_check -int sparc64_mmap_check(unsigned long addr, unsigned long len, - unsigned long flags); +#define arch_mmap_check(addr,len,flags) sparc64_mmap_check(addr,len) +int sparc64_mmap_check(unsigned long addr, unsigned long len); #endif #endif -- cgit v1.2.3 From 8388e3da34edb141362bb42811ee487dfec15525 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 12 May 2008 20:17:33 -0700 Subject: net: Set LL_MAX_HEADER properly for wireless. Wireless networking, particularly with MESH enabled, has quite strong requirements for link-layer header space. Based upon some numbers and descriptions from Johannes Berg we use 96 (same as AX25) for plain wireless, and with mesh enabled we use 128. In the process, simplify the cpp conditional logic here by ordering the cases by those needing the most space down to those needing the least case. Signed-off-by: David S. Miller --- include/linux/netdevice.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 746901774d49..a3fb57fde623 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -93,14 +93,16 @@ struct wireless_dev; * used. */ -#if !defined(CONFIG_AX25) && !defined(CONFIG_AX25_MODULE) && !defined(CONFIG_TR) -#define LL_MAX_HEADER 32 +#if defined(CONFIG_WLAN_80211) || defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE) +# if defined(CONFIG_MAC80211_MESH) +# define LL_MAX_HEADER 128 +# else +# define LL_MAX_HEADER 96 +# endif +#elif defined(CONFIG_TR) +# define LL_MAX_HEADER 48 #else -#if defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE) -#define LL_MAX_HEADER 96 -#else -#define LL_MAX_HEADER 48 -#endif +# define LL_MAX_HEADER 32 #endif #if !defined(CONFIG_NET_IPIP) && !defined(CONFIG_NET_IPIP_MODULE) && \ -- cgit v1.2.3 From f5184d267c1aedb9b7a8cc44e08ff6b8d382c3b5 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Mon, 12 May 2008 20:48:31 -0700 Subject: net: Allow netdevices to specify needed head/tailroom This patch adds needed_headroom/needed_tailroom members to struct net_device and updates many places that allocate sbks to use them. Not all of them can be converted though, and I'm sure I missed some (I mostly grepped for LL_RESERVED_SPACE) Signed-off-by: Johannes Berg Signed-off-by: David S. Miller --- include/linux/netdevice.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index a3fb57fde623..b11e6e19e96c 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -246,11 +246,16 @@ struct hh_cache * * We could use other alignment values, but we must maintain the * relationship HH alignment <= LL alignment. + * + * LL_ALLOCATED_SPACE also takes into account the tailroom the device + * may need. */ #define LL_RESERVED_SPACE(dev) \ - (((dev)->hard_header_len&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) + ((((dev)->hard_header_len+(dev)->needed_headroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) #define LL_RESERVED_SPACE_EXTRA(dev,extra) \ - ((((dev)->hard_header_len+extra)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) + ((((dev)->hard_header_len+(dev)->needed_headroom+(extra))&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) +#define LL_ALLOCATED_SPACE(dev) \ + ((((dev)->hard_header_len+(dev)->needed_headroom+(dev)->needed_tailroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) struct header_ops { int (*create) (struct sk_buff *skb, struct net_device *dev, @@ -569,6 +574,13 @@ struct net_device unsigned short type; /* interface hardware type */ unsigned short hard_header_len; /* hardware hdr length */ + /* extra head- and tailroom the hardware may need, but not in all cases + * can this be guaranteed, especially tailroom. Some cases also use + * LL_MAX_HEADER instead to allocate the skb. + */ + unsigned short needed_headroom; + unsigned short needed_tailroom; + struct net_device *master; /* Pointer to master device of a group, * which this device is member of. */ -- cgit v1.2.3 From 9a28dbf8af11d127bf1c644143e7882cb91515dd Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 12 May 2008 22:45:15 -0700 Subject: sparc64: Use a TS_RESTORE_SIGMASK This mirrors x86 changeset 5a8da0ea82db6fa9737041381079fd16f25dcce2 ("signals: x86 TS_RESTORE_SIGMASK") on sparc64. Signed-off-by: David S. Miller --- include/asm-sparc64/thread_info.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h index 71e42d1a80d9..e5873e385306 100644 --- a/include/asm-sparc64/thread_info.h +++ b/include/asm-sparc64/thread_info.h @@ -38,7 +38,7 @@ struct thread_info { struct task_struct *task; unsigned long flags; __u8 fpsaved[7]; - __u8 pad; + __u8 status; unsigned long ksp; /* D$ line 2 */ @@ -217,7 +217,7 @@ register struct thread_info *current_thread_info_reg asm("g6"); * nop */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_RESTORE_SIGMASK 1 /* restore signal mask in do_signal() */ +/* flags bit 1 is available */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_PERFCTR 4 /* performance counters active */ @@ -244,14 +244,34 @@ register struct thread_info *current_thread_info_reg asm("g6"); #define _TIF_32BIT (1<status |= TS_RESTORE_SIGMASK; + set_bit(TIF_SIGPENDING, &ti->flags); +} +#endif /* !__ASSEMBLY__ */ + #endif /* __KERNEL__ */ #endif /* _ASM_THREAD_INFO_H */ -- cgit v1.2.3 From 392abe9cb36f04ccdda9c96938077b0d43f2b50b Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Tue, 13 May 2008 14:03:40 +0200 Subject: [ALSA] ASoC: build fix for snd_soc_info_bool_ext I suspect that snd_ctl_boolean_mono should have been snd_ctl_boolean_mono_info instead. This fixes the build for magician. Signed-off-by: Philipp Zabel Acked-by: Mark Brown Signed-off-by: Takashi Iwai --- include/sound/soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/sound/soc.h b/include/sound/soc.h index e6ea6f750941..d3c8c033dff8 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -238,7 +238,7 @@ int snd_soc_info_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); int snd_soc_info_volsw_ext(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); -#define snd_soc_info_bool_ext snd_ctl_boolean_mono +#define snd_soc_info_bool_ext snd_ctl_boolean_mono_info int snd_soc_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int snd_soc_put_volsw(struct snd_kcontrol *kcontrol, -- cgit v1.2.3 From 309e96cdf2f2c1a071102e8bdf828a3493e6e50a Mon Sep 17 00:00:00 2001 From: Jeff Dike Date: Mon, 12 May 2008 14:01:52 -0700 Subject: uml: remove unused header From: Adrian Bunk This patch removes the unused and broken (the normal asm/keyboard.h files no longer exists) include/asm-um/keyboard.h Signed-off-by: Adrian Bunk Signed-off-by: Jeff Dike Cc: WANG Cong Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-um/keyboard.h | 6 ------ 1 file changed, 6 deletions(-) delete mode 100644 include/asm-um/keyboard.h (limited to 'include') diff --git a/include/asm-um/keyboard.h b/include/asm-um/keyboard.h deleted file mode 100644 index ee2e2303d0e4..000000000000 --- a/include/asm-um/keyboard.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __UM_KEYBOARD_H -#define __UM_KEYBOARD_H - -#include "asm/arch/keyboard.h" - -#endif -- cgit v1.2.3 From a7dfa9403bf3b03899d5ef5d10b0c5c3f74b0682 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Mon, 12 May 2008 14:01:56 -0700 Subject: uml: use PAGE_SIZE in linker scripts This patch includes page.h header into linker scripts that allow us to use PAGE_SIZE macro instead of numeric constant. To be able to include page.h into linker scripts page.h is needed for some modification - i.e. we need to use __ASSEMBLY__ and _AC macro [jdike@linux.intel.com - fixed conflict with as-layout.h] Signed-off-by: Cyrill Gorcunov Signed-off-by: Jeff Dike Cc: WANG Cong Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-um/page.h | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-um/page.h b/include/asm-um/page.h index 381f96b1c825..916e1a61999f 100644 --- a/include/asm-um/page.h +++ b/include/asm-um/page.h @@ -7,16 +7,20 @@ #ifndef __UM_PAGE_H #define __UM_PAGE_H -struct page; - -#include -#include +#include /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 -#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) +#ifndef __ASSEMBLY__ + +struct page; + +#include +#include + /* * These are used to make use of C type-checking.. */ @@ -120,4 +124,5 @@ extern struct page *arch_validate(struct page *page, gfp_t mask, int order); #include #include -#endif +#endif /* __ASSEMBLY__ */ +#endif /* __UM_PAGE_H */ -- cgit v1.2.3 From 5d33e4d7fd9a52d2673e5c730eab81856e100a74 Mon Sep 17 00:00:00 2001 From: Jeff Dike Date: Mon, 12 May 2008 14:01:58 -0700 Subject: uml: random driver fixes The random driver would essentially hang if the host's /dev/random returned -EAGAIN. There was a test of need_resched followed by a schedule inside the loop, but that didn't help and it's the wrong way to work anyway. The right way is to ask for an interrupt when there is input available from the host and handle it then rather than polling. Now, when the host's /dev/random returns -EAGAIN, the driver asks for a wakeup when there's randomness available again and sleeps. The interrupt routine just wakes up whatever processes are sleeping on host_read_wait. There is an atomic_t, host_sleep_count, which counts the number of processes waiting for randomness. When this reaches zero, the interrupt is disabled. An added complication is that async I/O notification was only recently added to /dev/random (by me), so essentially all hosts will lack it. So, we use the sigio workaround here, which is to have a separate thread poll on the descriptor and send an interrupt when there is input on it. This mechanism is activated when a process gets -EAGAIN (activating this multiple times is harmless, if a bit wasteful) and deactivated by the last process still waiting. The module name was changed from "random" to "hw_random" in order for udev to recognize it. The sigio workaround needed some changes. sigio_broken was added for cases when we know that async notification doesn't work. This is now called from maybe_sigio_broken, which deals with pts devices. Signed-off-by: Jeff Dike Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-um/irq.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-um/irq.h b/include/asm-um/irq.h index de389a477cdd..4a2037f8204b 100644 --- a/include/asm-um/irq.h +++ b/include/asm-um/irq.h @@ -15,8 +15,9 @@ #define SIGIO_WRITE_IRQ 11 #define TELNETD_IRQ 12 #define XTERM_IRQ 13 +#define RANDOM_IRQ 14 -#define LAST_IRQ XTERM_IRQ +#define LAST_IRQ RANDOM_IRQ #define NR_IRQS (LAST_IRQ + 1) #endif -- cgit v1.2.3 From f4ed0deae8983591264d0e194e168ef65f4775f5 Mon Sep 17 00:00:00 2001 From: Paul Jackson Date: Mon, 12 May 2008 14:02:29 -0700 Subject: cpumask: remove bitmap_scnprintf_len and cpumask_scnprintf_len They aren't used. They were briefly used as part of some other patches to provide an alternative format for displaying some /proc and /sys cpumasks. They probably should have been removed when those other patches were dropped, in favor of a different solution. Signed-off-by: Paul Jackson Cc: "Mike Travis" Cc: "Bert Wesarg" Cc: Alexey Dobriyan Cc: WANG Cong Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/bitmap.h | 1 - include/linux/cpumask.h | 7 ------- 2 files changed, 8 deletions(-) (limited to 'include') diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h index 43b406def35f..1abfe664c444 100644 --- a/include/linux/bitmap.h +++ b/include/linux/bitmap.h @@ -110,7 +110,6 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits); extern int bitmap_scnprintf(char *buf, unsigned int len, const unsigned long *src, int nbits); -extern int bitmap_scnprintf_len(unsigned int len); extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user, unsigned long *dst, int nbits); extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen, diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index 9650806fe2ea..5df3db58fcc6 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -289,13 +289,6 @@ static inline int __cpumask_scnprintf(char *buf, int len, return bitmap_scnprintf(buf, len, srcp->bits, nbits); } -#define cpumask_scnprintf_len(len) \ - __cpumask_scnprintf_len((len)) -static inline int __cpumask_scnprintf_len(int len) -{ - return bitmap_scnprintf_len(len); -} - #define cpumask_parse_user(ubuf, ulen, dst) \ __cpumask_parse_user((ubuf), (ulen), &(dst), NR_CPUS) static inline int __cpumask_parse_user(const char __user *buf, int len, -- cgit v1.2.3 From 4cd1a8fc3d3cd740416b14ece2693dbb5d065eaf Mon Sep 17 00:00:00 2001 From: KOSAKI Motohiro Date: Mon, 12 May 2008 14:02:31 -0700 Subject: memcg: fix possible panic when CONFIG_MM_OWNER=y When mm destruction happens, we should pass mm_update_next_owner() the old mm. But unfortunately new mm is passed in exec_mmap(). Thus, kernel panic is possible when a multi-threaded process uses exec(). Also, the owner member comment description is wrong. mm->owner does not necessarily point to the thread group leader. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: KOSAKI Motohiro Acked-by: Balbir Singh Cc: "Paul Menage" Cc: "KAMEZAWA Hiroyuki" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/mm_types.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index eb7c16cc9559..02a27ae78539 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -226,8 +226,17 @@ struct mm_struct { rwlock_t ioctx_list_lock; /* aio lock */ struct kioctx *ioctx_list; #ifdef CONFIG_MM_OWNER - struct task_struct *owner; /* The thread group leader that */ - /* owns the mm_struct. */ + /* + * "owner" points to a task that is regarded as the canonical + * user/owner of this mm. All of the following must be true in + * order for it to be changed: + * + * current == mm->owner + * current->mm != mm + * new_owner->mm == mm + * new_owner->alloc_lock is held + */ + struct task_struct *owner; #endif #ifdef CONFIG_PROC_FS -- cgit v1.2.3 From 78bb6cb9a890d3d50ca3b02fce9223d3e734ab9b Mon Sep 17 00:00:00 2001 From: Miklos Szeredi Date: Mon, 12 May 2008 14:02:32 -0700 Subject: fuse: add flag to turn on big writes Prior to 2.6.26 fuse only supported single page write requests. In theory all fuse filesystem should be able support bigger than 4k writes, as there's nothing in the API to prevent it. Unfortunately there's a known case in NTFS-3G where big writes cause filesystem corruption. There could also be other filesystems, where the lack of testing with big write requests would result in bugs. To prevent such problems on a kernel upgrade, disable big writes by default, but let filesystems set a flag to turn it on. Signed-off-by: Miklos Szeredi Cc: Szabolcs Szakacsits Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/fuse.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/fuse.h b/include/linux/fuse.h index 5c86f1196c3a..d48282197696 100644 --- a/include/linux/fuse.h +++ b/include/linux/fuse.h @@ -109,6 +109,7 @@ struct fuse_file_lock { #define FUSE_POSIX_LOCKS (1 << 1) #define FUSE_FILE_OPS (1 << 2) #define FUSE_ATOMIC_O_TRUNC (1 << 3) +#define FUSE_BIG_WRITES (1 << 5) /** * Release flags -- cgit v1.2.3 From 332223831e86b2e17b48b4afafad07d8e3b73861 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Tue, 13 May 2008 23:25:57 -0700 Subject: irda: Fix a misalign access issue. (v2) Replace u16ho with put/get_unaligned functions Signed-off-by: Graf Yang Signed-off-by: Bryan Wu Signed-off-by: David S. Miller --- include/net/irda/discovery.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/net/irda/discovery.h b/include/net/irda/discovery.h index e4efad1f9eff..0ce93398720d 100644 --- a/include/net/irda/discovery.h +++ b/include/net/irda/discovery.h @@ -57,9 +57,6 @@ typedef union { __u8 byte[2]; } __u16_host_order; -/* Same purpose, different application */ -#define u16ho(array) (* ((__u16 *) array)) - /* Types of discovery */ typedef enum { DISCOVERY_LOG, /* What's in our discovery log */ -- cgit v1.2.3 From d23039eec77473124c9635c01378314f196f2211 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 25 Apr 2008 19:23:16 -0700 Subject: USB: add association.h This will be used by the wireless usb code, as well as potentially other USB code. Originally based on some .c code written by Inaky Perez-Gonzalez Cc: Inaky Perez-Gonzalez Cc: David Brownell Signed-off-by: Greg Kroah-Hartman --- include/linux/usb/association.h | 150 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 include/linux/usb/association.h (limited to 'include') diff --git a/include/linux/usb/association.h b/include/linux/usb/association.h new file mode 100644 index 000000000000..07c5e3cf5898 --- /dev/null +++ b/include/linux/usb/association.h @@ -0,0 +1,150 @@ +/* + * Wireless USB - Cable Based Association + * + * Copyright (C) 2006 Intel Corporation + * Inaky Perez-Gonzalez + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + */ +#ifndef __LINUX_USB_ASSOCIATION_H +#define __LINUX_USB_ASSOCIATION_H + + +/* + * Association attributes + * + * Association Models Supplement to WUSB 1.0 T[3-1] + * + * Each field in the structures has it's ID, it's length and then the + * value. This is the actual definition of the field's ID and its + * length. + */ +struct wusb_am_attr { + __u8 id; + __u8 len; +}; + +/* Different fields defined by the spec */ +#define WUSB_AR_AssociationTypeId { .id = 0x0000, .len = 2 } +#define WUSB_AR_AssociationSubTypeId { .id = 0x0001, .len = 2 } +#define WUSB_AR_Length { .id = 0x0002, .len = 4 } +#define WUSB_AR_AssociationStatus { .id = 0x0004, .len = 4 } +#define WUSB_AR_LangID { .id = 0x0008, .len = 2 } +#define WUSB_AR_DeviceFriendlyName { .id = 0x000b, .len = 64 } /* max */ +#define WUSB_AR_HostFriendlyName { .id = 0x000c, .len = 64 } /* max */ +#define WUSB_AR_CHID { .id = 0x1000, .len = 16 } +#define WUSB_AR_CDID { .id = 0x1001, .len = 16 } +#define WUSB_AR_ConnectionContext { .id = 0x1002, .len = 48 } +#define WUSB_AR_BandGroups { .id = 0x1004, .len = 2 } + +/* CBAF Control Requests (AMS1.0[T4-1] */ +enum { + CBAF_REQ_GET_ASSOCIATION_INFORMATION = 0x01, + CBAF_REQ_GET_ASSOCIATION_REQUEST, + CBAF_REQ_SET_ASSOCIATION_RESPONSE +}; + +/* + * CBAF USB-interface defitions + * + * No altsettings, one optional interrupt endpoint. + */ +enum { + CBAF_IFACECLASS = 0xef, + CBAF_IFACESUBCLASS = 0x03, + CBAF_IFACEPROTOCOL = 0x01, +}; + +/* Association Information (AMS1.0[T4-3]) */ +struct wusb_cbaf_assoc_info { + __le16 Length; + __u8 NumAssociationRequests; + __le16 Flags; + __u8 AssociationRequestsArray[]; +} __attribute__((packed)); + +/* Association Request (AMS1.0[T4-4]) */ +struct wusb_cbaf_assoc_request { + __u8 AssociationDataIndex; + __u8 Reserved; + __le16 AssociationTypeId; + __le16 AssociationSubTypeId; + __le32 AssociationTypeInfoSize; +} __attribute__((packed)); + +enum { + AR_TYPE_WUSB = 0x0001, + AR_TYPE_WUSB_RETRIEVE_HOST_INFO = 0x0000, + AR_TYPE_WUSB_ASSOCIATE = 0x0001, +}; + +/* Association Attribute header (AMS1.0[3.8]) */ +struct wusb_cbaf_attr_hdr { + __le16 id; + __le16 len; +} __attribute__((packed)); + +/* Host Info (AMS1.0[T4-7]) (yeah, more headers and fields...) */ +struct wusb_cbaf_host_info { + struct wusb_cbaf_attr_hdr AssociationTypeId_hdr; + __le16 AssociationTypeId; + struct wusb_cbaf_attr_hdr AssociationSubTypeId_hdr; + __le16 AssociationSubTypeId; + struct wusb_cbaf_attr_hdr CHID_hdr; + struct wusb_ckhdid CHID; + struct wusb_cbaf_attr_hdr LangID_hdr; + __le16 LangID; + struct wusb_cbaf_attr_hdr HostFriendlyName_hdr; + __u8 HostFriendlyName[]; +} __attribute__((packed)); + +/* Device Info (AMS1.0[T4-8]) + * + * I still don't get this tag'n'header stuff for each goddamn + * field... + */ +struct wusb_cbaf_device_info { + struct wusb_cbaf_attr_hdr Length_hdr; + __le32 Length; + struct wusb_cbaf_attr_hdr CDID_hdr; + struct wusb_ckhdid CDID; + struct wusb_cbaf_attr_hdr BandGroups_hdr; + __le16 BandGroups; + struct wusb_cbaf_attr_hdr LangID_hdr; + __le16 LangID; + struct wusb_cbaf_attr_hdr DeviceFriendlyName_hdr; + __u8 DeviceFriendlyName[]; +} __attribute__((packed)); + +/* Connection Context; CC_DATA - Success case (AMS1.0[T4-9]) */ +struct wusb_cbaf_cc_data { + struct wusb_cbaf_attr_hdr AssociationTypeId_hdr; + __le16 AssociationTypeId; + struct wusb_cbaf_attr_hdr AssociationSubTypeId_hdr; + __le16 AssociationSubTypeId; + struct wusb_cbaf_attr_hdr Length_hdr; + __le32 Length; + struct wusb_cbaf_attr_hdr ConnectionContext_hdr; + struct wusb_ckhdid CHID; + struct wusb_ckhdid CDID; + struct wusb_ckhdid CK; + struct wusb_cbaf_attr_hdr BandGroups_hdr; + __le16 BandGroups; +} __attribute__((packed)); + +/* CC_DATA - Failure case (AMS1.0[T4-10]) */ +struct wusb_cbaf_cc_data_fail { + struct wusb_cbaf_attr_hdr AssociationTypeId_hdr; + __le16 AssociationTypeId; + struct wusb_cbaf_attr_hdr AssociationSubTypeId_hdr; + __le16 AssociationSubTypeId; + struct wusb_cbaf_attr_hdr Length_hdr; + __le16 Length; + struct wusb_cbaf_attr_hdr AssociationStatus_hdr; + __u32 AssociationStatus; +} __attribute__((packed)); + +#endif /* __LINUX_USB_ASSOCIATION_H */ -- cgit v1.2.3 From 73f10281ea96d7e8b4fc1c5d755a7c8eb484155b Mon Sep 17 00:00:00 2001 From: Nick Piggin Date: Wed, 14 May 2008 06:35:11 +0200 Subject: read_barrier_depends arch fixlets read_barrie_depends has always been a noop (not a compiler barrier) on all architectures except SMP alpha. This brings UP alpha and frv into line with all other architectures, and fixes incorrect documentation. Signed-off-by: Nick Piggin Acked-by: Paul E. McKenney Signed-off-by: Linus Torvalds --- include/asm-alpha/barrier.h | 2 +- include/asm-frv/system.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-alpha/barrier.h b/include/asm-alpha/barrier.h index 384dc08d6f53..ac78eba909bc 100644 --- a/include/asm-alpha/barrier.h +++ b/include/asm-alpha/barrier.h @@ -24,7 +24,7 @@ __asm__ __volatile__("mb": : :"memory") #define smp_mb() barrier() #define smp_rmb() barrier() #define smp_wmb() barrier() -#define smp_read_barrier_depends() barrier() +#define smp_read_barrier_depends() do { } while (0) #endif #define set_mb(var, value) \ diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h index cb307f8a6b48..d3a12a9079f7 100644 --- a/include/asm-frv/system.h +++ b/include/asm-frv/system.h @@ -179,7 +179,7 @@ do { \ #define mb() asm volatile ("membar" : : :"memory") #define rmb() asm volatile ("membar" : : :"memory") #define wmb() asm volatile ("membar" : : :"memory") -#define read_barrier_depends() barrier() +#define read_barrier_depends() do { } while (0) #ifdef CONFIG_SMP #define smp_mb() mb() -- cgit v1.2.3 From 362a61ad61199e19a61b8e432015e2586b288f5b Mon Sep 17 00:00:00 2001 From: Nick Piggin Date: Wed, 14 May 2008 06:37:36 +0200 Subject: fix SMP data race in pagetable setup vs walking There is a possible data race in the page table walking code. After the split ptlock patches, it actually seems to have been introduced to the core code, but even before that I think it would have impacted some architectures (powerpc and sparc64, at least, walk the page tables without taking locks eg. see find_linux_pte()). The race is as follows: The pte page is allocated, zeroed, and its struct page gets its spinlock initialized. The mm-wide ptl is then taken, and then the pte page is inserted into the pagetables. At this point, the spinlock is not guaranteed to have ordered the previous stores to initialize the pte page with the subsequent store to put it in the page tables. So another Linux page table walker might be walking down (without any locks, because we have split-leaf-ptls), and find that new pte we've inserted. It might try to take the spinlock before the store from the other CPU initializes it. And subsequently it might read a pte_t out before stores from the other CPU have cleared the memory. There are also similar races in higher levels of the page tables. They obviously don't involve the spinlock, but could see uninitialized memory. Arch code and hardware pagetable walkers that walk the pagetables without locks could see similar uninitialized memory problems, regardless of whether split ptes are enabled or not. I prefer to put the barriers in core code, because that's where the higher level logic happens, but the page table accessors are per-arch, and open-coding them everywhere I don't think is an option. I'll put the read-side barriers in alpha arch code for now (other architectures perform data-dependent loads in order). Signed-off-by: Nick Piggin Signed-off-by: Linus Torvalds --- include/asm-alpha/pgtable.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h index 05ce5fba43e3..3f0c59f6d8aa 100644 --- a/include/asm-alpha/pgtable.h +++ b/include/asm-alpha/pgtable.h @@ -287,17 +287,34 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; } #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) +/* + * The smp_read_barrier_depends() in the following functions are required to + * order the load of *dir (the pointer in the top level page table) with any + * subsequent load of the returned pmd_t *ret (ret is data dependent on *dir). + * + * If this ordering is not enforced, the CPU might load an older value of + * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for + * more details. + * + * Note that we never change the mm->pgd pointer after the task is running, so + * pgd_offset does not require such a barrier. + */ + /* Find an entry in the second-level page table.. */ extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) { - return (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); + pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); + smp_read_barrier_depends(); /* see above */ + return ret; } /* Find an entry in the third-level page table.. */ extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address) { - return (pte_t *) pmd_page_vaddr(*dir) + pte_t *ret = (pte_t *) pmd_page_vaddr(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1)); + smp_read_barrier_depends(); /* see above */ + return ret; } #define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr)) -- cgit v1.2.3 From 30f2f0eb4bd2c43d10a8b0d872c6e5ad8f31c9a0 Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Tue, 6 May 2008 22:31:33 +0200 Subject: block: do_mounts - accept root= Some devices, like md, may create partitions only at first access, so allow root= to be set to a valid non-existant partition of an existing disk. This applies only to non-initramfs root mounting. This fixes a regression from 2.6.24 which did allow this to happen and broke some users machines :( Acked-by: Neil Brown Tested-by: Joao Luis Meloni Assirati Cc: stable Signed-off-by: Kay Sievers Signed-off-by: Greg Kroah-Hartman --- include/linux/genhd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/genhd.h b/include/linux/genhd.h index e9874e7fcdf9..ae7aec3cabee 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -525,7 +525,7 @@ struct unixware_disklabel { #define ADDPART_FLAG_RAID 1 #define ADDPART_FLAG_WHOLEDISK 2 -extern dev_t blk_lookup_devt(const char *name); +extern dev_t blk_lookup_devt(const char *name, int part); extern char *disk_name (struct gendisk *hd, int part, char *buf); extern int rescan_partitions(struct gendisk *disk, struct block_device *bdev); @@ -553,7 +553,7 @@ static inline struct block_device *bdget_disk(struct gendisk *disk, int index) static inline void printk_all_partitions(void) { } -static inline dev_t blk_lookup_devt(const char *name) +static inline dev_t blk_lookup_devt(const char *name, int part) { dev_t devt = MKDEV(0, 0); return devt; -- cgit v1.2.3 From 0a3ad00ca09632c6d0675f606276e92bdf1b306c Mon Sep 17 00:00:00 2001 From: Dave Young Date: Fri, 9 May 2008 15:24:08 +0800 Subject: Driver core: struct class remove children list because of the class_device was removed, now do the children list removing Signed-off-by: Dave Young Signed-off-by: Greg Kroah-Hartman --- include/linux/device.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/linux/device.h b/include/linux/device.h index 8c23e3dfe3ac..15e9fa3ad3af 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -183,7 +183,6 @@ struct class { struct module *owner; struct kset subsys; - struct list_head children; struct list_head devices; struct list_head interfaces; struct kset class_dirs; -- cgit v1.2.3 From e0b4eb5193fed5c63413b0c137be29b0477d15ca Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Wed, 14 May 2008 23:06:15 +0200 Subject: make ide-iops.c:SELECT_MASK() static SELECT_MASK() can now become static. [bart: remove space between function name and open parenthesis] Signed-off-by: Adrian Bunk Signed-off-by: Bartlomiej Zolnierkiewicz --- include/linux/ide.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/linux/ide.h b/include/linux/ide.h index b0135b0c3a04..19ec852dffd2 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -965,7 +965,6 @@ typedef struct ide_task_s { void ide_tf_dump(const char *, struct ide_taskfile *); extern void SELECT_DRIVE(ide_drive_t *); -extern void SELECT_MASK(ide_drive_t *, int); extern int drive_is_ready(ide_drive_t *); -- cgit v1.2.3 From cafa027b8cc6f605ccebc43a960644307a12d8dd Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 14 May 2008 23:06:16 +0200 Subject: cs5520: disable VDMA Disable Virtual DMA support for now (it causes system hangs). Thanks to TAKADA Yoshihito for the help with debugging the problem. Reported-by: TAKADA Yoshihito Signed-off-by: Bartlomiej Zolnierkiewicz --- include/linux/ide.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/ide.h b/include/linux/ide.h index 19ec852dffd2..f8f195c20da2 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1057,8 +1057,8 @@ enum { IDE_HFLAG_NO_SET_MODE = (1 << 9), /* trust BIOS for programming chipset/device for DMA */ IDE_HFLAG_TRUST_BIOS_FOR_DMA = (1 << 10), - /* host uses VDMA (tied with IDE_HFLAG_CS5520 for now) */ - IDE_HFLAG_VDMA = (1 << 11), + /* host is CS5510/CS5520 */ + IDE_HFLAG_CS5520 = (1 << 11), /* ATAPI DMA is unsupported */ IDE_HFLAG_NO_ATAPI_DMA = (1 << 12), /* set if host is a "non-bootable" controller */ @@ -1069,8 +1069,6 @@ enum { IDE_HFLAG_NO_AUTODMA = (1 << 15), /* host uses MMIO */ IDE_HFLAG_MMIO = (1 << 16), - /* host is CS5510/CS5520 */ - IDE_HFLAG_CS5520 = IDE_HFLAG_VDMA, /* no LBA48 */ IDE_HFLAG_NO_LBA48 = (1 << 17), /* no LBA48 DMA */ @@ -1100,6 +1098,8 @@ enum { IDE_HFLAG_NO_IO_32BIT = (1 << 30), /* never unmask IRQs */ IDE_HFLAG_NO_UNMASK_IRQS = (1 << 31), + /* host uses VDMA (disabled for now) */ + IDE_HFLAG_VDMA = 0, }; #ifdef CONFIG_BLK_DEV_OFFBOARD -- cgit v1.2.3 From 7868f1ed84696d3cca83558e8dd459f20a36d077 Mon Sep 17 00:00:00 2001 From: Jack Steiner Date: Tue, 6 May 2008 15:18:55 -0500 Subject: [IA64] Add header files for SGI UV platform Add new UV-specific header files. Signed-off-by: Jack Steiner Signed-off-by: Tony Luck --- include/asm-ia64/uv/uv_hub.h | 309 ++++++++++++++++++++++++++++++++++++++++++ include/asm-ia64/uv/uv_mmrs.h | 266 ++++++++++++++++++++++++++++++++++++ 2 files changed, 575 insertions(+) create mode 100644 include/asm-ia64/uv/uv_hub.h create mode 100644 include/asm-ia64/uv/uv_mmrs.h (limited to 'include') diff --git a/include/asm-ia64/uv/uv_hub.h b/include/asm-ia64/uv/uv_hub.h new file mode 100644 index 000000000000..f607018af4a1 --- /dev/null +++ b/include/asm-ia64/uv/uv_hub.h @@ -0,0 +1,309 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SGI UV architectural definitions + * + * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef __ASM_IA64_UV_HUB_H__ +#define __ASM_IA64_UV_HUB_H__ + +#include +#include +#include +#include + + +/* + * Addressing Terminology + * + * M - The low M bits of a physical address represent the offset + * into the blade local memory. RAM memory on a blade is physically + * contiguous (although various IO spaces may punch holes in + * it).. + * + * N - Number of bits in the node portion of a socket physical + * address. + * + * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of + * routers always have low bit of 1, C/MBricks have low bit + * equal to 0. Most addressing macros that target UV hub chips + * right shift the NASID by 1 to exclude the always-zero bit. + * NASIDs contain up to 15 bits. + * + * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead + * of nasids. + * + * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant + * of the nasid for socket usage. + * + * + * NumaLink Global Physical Address Format: + * +--------------------------------+---------------------+ + * |00..000| GNODE | NodeOffset | + * +--------------------------------+---------------------+ + * |<-------53 - M bits --->|<--------M bits -----> + * + * M - number of node offset bits (35 .. 40) + * + * + * Memory/UV-HUB Processor Socket Address Format: + * +----------------+---------------+---------------------+ + * |00..000000000000| PNODE | NodeOffset | + * +----------------+---------------+---------------------+ + * <--- N bits --->|<--------M bits -----> + * + * M - number of node offset bits (35 .. 40) + * N - number of PNODE bits (0 .. 10) + * + * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). + * The actual values are configuration dependent and are set at + * boot time. M & N values are set by the hardware/BIOS at boot. + */ + + +/* + * Maximum number of bricks in all partitions and in all coherency domains. + * This is the total number of bricks accessible in the numalink fabric. It + * includes all C & M bricks. Routers are NOT included. + * + * This value is also the value of the maximum number of non-router NASIDs + * in the numalink fabric. + * + * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. + */ +#define UV_MAX_NUMALINK_BLADES 16384 + +/* + * Maximum number of C/Mbricks within a software SSI (hardware may support + * more). + */ +#define UV_MAX_SSI_BLADES 1 + +/* + * The largest possible NASID of a C or M brick (+ 2) + */ +#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) + +/* + * The following defines attributes of the HUB chip. These attributes are + * frequently referenced and are kept in the per-cpu data areas of each cpu. + * They are kept together in a struct to minimize cache misses. + */ +struct uv_hub_info_s { + unsigned long global_mmr_base; + unsigned long gpa_mask; + unsigned long gnode_upper; + unsigned long lowmem_remap_top; + unsigned long lowmem_remap_base; + unsigned short pnode; + unsigned short pnode_mask; + unsigned short coherency_domain_number; + unsigned short numa_blade_id; + unsigned char blade_processor_id; + unsigned char m_val; + unsigned char n_val; +}; +DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); +#define uv_hub_info (&__get_cpu_var(__uv_hub_info)) +#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) + +/* + * Local & Global MMR space macros. + * Note: macros are intended to be used ONLY by inline functions + * in this file - not by other kernel code. + * n - NASID (full 15-bit global nasid) + * g - GNODE (full 15-bit global nasid, right shifted 1) + * p - PNODE (local part of nsids, right shifted 1) + */ +#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) +#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper) + +#define UV_LOCAL_MMR_BASE 0xf4000000UL +#define UV_GLOBAL_MMR32_BASE 0xf8000000UL +#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) + +#define UV_GLOBAL_MMR32_PNODE_SHIFT 15 +#define UV_GLOBAL_MMR64_PNODE_SHIFT 26 + +#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) + +#define UV_GLOBAL_MMR64_PNODE_BITS(p) \ + ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) + +/* + * Macros for converting between kernel virtual addresses, socket local physical + * addresses, and UV global physical addresses. + * Note: use the standard __pa() & __va() macros for converting + * between socket virtual and socket physical addresses. + */ + +/* socket phys RAM --> UV global physical address */ +static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) +{ + if (paddr < uv_hub_info->lowmem_remap_top) + paddr += uv_hub_info->lowmem_remap_base; + return paddr | uv_hub_info->gnode_upper; +} + + +/* socket virtual --> UV global physical address */ +static inline unsigned long uv_gpa(void *v) +{ + return __pa(v) | uv_hub_info->gnode_upper; +} + +/* socket virtual --> UV global physical address */ +static inline void *uv_vgpa(void *v) +{ + return (void *)uv_gpa(v); +} + +/* UV global physical address --> socket virtual */ +static inline void *uv_va(unsigned long gpa) +{ + return __va(gpa & uv_hub_info->gpa_mask); +} + +/* pnode, offset --> socket virtual */ +static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) +{ + return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); +} + + +/* + * Access global MMRs using the low memory MMR32 space. This region supports + * faster MMR access but not all MMRs are accessible in this space. + */ +static inline unsigned long *uv_global_mmr32_address(int pnode, + unsigned long offset) +{ + return __va(UV_GLOBAL_MMR32_BASE | + UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); +} + +static inline void uv_write_global_mmr32(int pnode, unsigned long offset, + unsigned long val) +{ + *uv_global_mmr32_address(pnode, offset) = val; +} + +static inline unsigned long uv_read_global_mmr32(int pnode, + unsigned long offset) +{ + return *uv_global_mmr32_address(pnode, offset); +} + +/* + * Access Global MMR space using the MMR space located at the top of physical + * memory. + */ +static inline unsigned long *uv_global_mmr64_address(int pnode, + unsigned long offset) +{ + return __va(UV_GLOBAL_MMR64_BASE | + UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); +} + +static inline void uv_write_global_mmr64(int pnode, unsigned long offset, + unsigned long val) +{ + *uv_global_mmr64_address(pnode, offset) = val; +} + +static inline unsigned long uv_read_global_mmr64(int pnode, + unsigned long offset) +{ + return *uv_global_mmr64_address(pnode, offset); +} + +/* + * Access hub local MMRs. Faster than using global space but only local MMRs + * are accessible. + */ +static inline unsigned long *uv_local_mmr_address(unsigned long offset) +{ + return __va(UV_LOCAL_MMR_BASE | offset); +} + +static inline unsigned long uv_read_local_mmr(unsigned long offset) +{ + return *uv_local_mmr_address(offset); +} + +static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) +{ + *uv_local_mmr_address(offset) = val; +} + +/* + * Structures and definitions for converting between cpu, node, pnode, and blade + * numbers. + */ + +/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ +static inline int uv_blade_processor_id(void) +{ + return smp_processor_id(); +} + +/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ +static inline int uv_numa_blade_id(void) +{ + return 0; +} + +/* Convert a cpu number to the the UV blade number */ +static inline int uv_cpu_to_blade_id(int cpu) +{ + return 0; +} + +/* Convert linux node number to the UV blade number */ +static inline int uv_node_to_blade_id(int nid) +{ + return 0; +} + +/* Convert a blade id to the PNODE of the blade */ +static inline int uv_blade_to_pnode(int bid) +{ + return 0; +} + +/* Determine the number of possible cpus on a blade */ +static inline int uv_blade_nr_possible_cpus(int bid) +{ + return num_possible_cpus(); +} + +/* Determine the number of online cpus on a blade */ +static inline int uv_blade_nr_online_cpus(int bid) +{ + return num_online_cpus(); +} + +/* Convert a cpu id to the PNODE of the blade containing the cpu */ +static inline int uv_cpu_to_pnode(int cpu) +{ + return 0; +} + +/* Convert a linux node number to the PNODE of the blade */ +static inline int uv_node_to_pnode(int nid) +{ + return 0; +} + +/* Maximum possible number of blades */ +static inline int uv_num_possible_blades(void) +{ + return 1; +} + +#endif /* __ASM_IA64_UV_HUB__ */ + diff --git a/include/asm-ia64/uv/uv_mmrs.h b/include/asm-ia64/uv/uv_mmrs.h new file mode 100644 index 000000000000..1cc1dbb0182f --- /dev/null +++ b/include/asm-ia64/uv/uv_mmrs.h @@ -0,0 +1,266 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SGI UV MMR definitions + * + * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef __ASM_IA64_UV_MMRS__ +#define __ASM_IA64_UV_MMRS__ + +/* + * AUTO GENERATED - Do not edit + */ + + #define UV_MMR_ENABLE (1UL << 63) + +/* ========================================================================= */ +/* UVH_NODE_ID */ +/* ========================================================================= */ +#define UVH_NODE_ID 0x0UL + +#define UVH_NODE_ID_FORCE1_SHFT 0 +#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL +#define UVH_NODE_ID_MANUFACTURER_SHFT 1 +#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL +#define UVH_NODE_ID_PART_NUMBER_SHFT 12 +#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL +#define UVH_NODE_ID_REVISION_SHFT 28 +#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL +#define UVH_NODE_ID_NODE_ID_SHFT 32 +#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL +#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48 +#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL +#define UVH_NODE_ID_NI_PORT_SHFT 56 +#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL + +union uvh_node_id_u { + unsigned long v; + struct uvh_node_id_s { + unsigned long force1 : 1; /* RO */ + unsigned long manufacturer : 11; /* RO */ + unsigned long part_number : 16; /* RO */ + unsigned long revision : 4; /* RO */ + unsigned long node_id : 15; /* RW */ + unsigned long rsvd_47 : 1; /* */ + unsigned long nodes_per_bit : 7; /* RW */ + unsigned long rsvd_55 : 1; /* */ + unsigned long ni_port : 4; /* RO */ + unsigned long rsvd_60_63 : 4; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL + +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL + +union uvh_rh_gam_alias210_redirect_config_0_mmr_u { + unsigned long v; + struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { + unsigned long rsvd_0_23 : 24; /* */ + unsigned long dest_base : 22; /* RW */ + unsigned long rsvd_46_63: 18; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL + +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL + +union uvh_rh_gam_alias210_redirect_config_1_mmr_u { + unsigned long v; + struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { + unsigned long rsvd_0_23 : 24; /* */ + unsigned long dest_base : 22; /* RW */ + unsigned long rsvd_46_63: 18; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL + +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL + +union uvh_rh_gam_alias210_redirect_config_2_mmr_u { + unsigned long v; + struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { + unsigned long rsvd_0_23 : 24; /* */ + unsigned long dest_base : 22; /* RW */ + unsigned long rsvd_46_63: 18; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL + +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46 +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 +#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL + +union uvh_rh_gam_gru_overlay_config_mmr_u { + unsigned long v; + struct uvh_rh_gam_gru_overlay_config_mmr_s { + unsigned long rsvd_0_27: 28; /* */ + unsigned long base : 18; /* RW */ + unsigned long gr4 : 1; /* RW */ + unsigned long rsvd_47_51: 5; /* */ + unsigned long n_gru : 4; /* RW */ + unsigned long rsvd_56_62: 7; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL + +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 +#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL + +union uvh_rh_gam_mmr_overlay_config_mmr_u { + unsigned long v; + struct uvh_rh_gam_mmr_overlay_config_mmr_s { + unsigned long rsvd_0_25: 26; /* */ + unsigned long base : 20; /* RW */ + unsigned long dual_hub : 1; /* RW */ + unsigned long rsvd_47_62: 16; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RTC */ +/* ========================================================================= */ +#define UVH_RTC 0x28000UL + +#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 +#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL + +union uvh_rtc_u { + unsigned long v; + struct uvh_rtc_s { + unsigned long real_time_clock : 56; /* RW */ + unsigned long rsvd_56_63 : 8; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_SI_ADDR_MAP_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL + +#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0 +#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL +#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8 +#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL + +union uvh_si_addr_map_config_u { + unsigned long v; + struct uvh_si_addr_map_config_s { + unsigned long m_skt : 6; /* RW */ + unsigned long rsvd_6_7: 2; /* */ + unsigned long n_skt : 4; /* RW */ + unsigned long rsvd_12_63: 52; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_SI_ALIAS0_OVERLAY_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL + +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24 +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63 +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL + +union uvh_si_alias0_overlay_config_u { + unsigned long v; + struct uvh_si_alias0_overlay_config_s { + unsigned long rsvd_0_23: 24; /* */ + unsigned long base : 8; /* RW */ + unsigned long rsvd_32_47: 16; /* */ + unsigned long m_alias : 5; /* RW */ + unsigned long rsvd_53_62: 10; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_SI_ALIAS1_OVERLAY_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL + +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24 +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63 +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL + +union uvh_si_alias1_overlay_config_u { + unsigned long v; + struct uvh_si_alias1_overlay_config_s { + unsigned long rsvd_0_23: 24; /* */ + unsigned long base : 8; /* RW */ + unsigned long rsvd_32_47: 16; /* */ + unsigned long m_alias : 5; /* RW */ + unsigned long rsvd_53_62: 10; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_SI_ALIAS2_OVERLAY_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL + +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24 +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63 +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL + +union uvh_si_alias2_overlay_config_u { + unsigned long v; + struct uvh_si_alias2_overlay_config_s { + unsigned long rsvd_0_23: 24; /* */ + unsigned long base : 8; /* RW */ + unsigned long rsvd_32_47: 16; /* */ + unsigned long m_alias : 5; /* RW */ + unsigned long rsvd_53_62: 10; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + + +#endif /* __ASM_IA64_UV_MMRS__ */ -- cgit v1.2.3 From 2224661494278bfc1c35b392cf6ee6f58e1d5e64 Mon Sep 17 00:00:00 2001 From: Jack Steiner Date: Tue, 6 May 2008 15:18:57 -0500 Subject: [IA64] machvec support for SGI UV platform This patch adds the basic IA64 machvec infrastructure to support the SGI "UV" platform. Signed-off-by: Jack Steiner Signed-off-by: Tony Luck --- include/asm-ia64/machvec.h | 2 ++ include/asm-ia64/machvec_uv.h | 26 ++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/asm-ia64/machvec_uv.h (limited to 'include') diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h index 9f020eb825c5..0721a5e8271e 100644 --- a/include/asm-ia64/machvec.h +++ b/include/asm-ia64/machvec.h @@ -126,6 +126,8 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *); # include # elif defined (CONFIG_IA64_SGI_SN2) # include +# elif defined (CONFIG_IA64_SGI_UV) +# include # elif defined (CONFIG_IA64_GENERIC) # ifdef MACHVEC_PLATFORM_HEADER diff --git a/include/asm-ia64/machvec_uv.h b/include/asm-ia64/machvec_uv.h new file mode 100644 index 000000000000..2931447f3813 --- /dev/null +++ b/include/asm-ia64/machvec_uv.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SGI UV Core Functions + * + * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_MACHVEC_UV_H +#define _ASM_IA64_MACHVEC_UV_H + +extern ia64_mv_setup_t uv_setup; + +/* + * This stuff has dual use! + * + * For a generic kernel, the macros are used to initialize the + * platform's machvec structure. When compiling a non-generic kernel, + * the macros are used directly. + */ +#define platform_name "uv" +#define platform_setup uv_setup + +#endif /* _ASM_IA64_MACHVEC_UV_H */ -- cgit v1.2.3 From b32a09db4fb9a87246ba4e7726a979ac4709ad97 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Tue, 26 Feb 2008 09:57:11 -0600 Subject: add match_strlcpy() us it to make v9fs make uname and remotename parsing more robust match_strcpy() is a somewhat creepy function: the caller needs to make sure that the destination buffer is big enough, and when he screws up or forgets, match_strcpy() happily overruns the buffer. There's exactly one customer: v9fs_parse_options(). I believe it currently can't overflow its buffer, but that's not exactly obvious. The source string is a substing of the mount options. The kernel silently truncates those to PAGE_SIZE bytes, including the terminating zero. See compat_sys_mount() and do_mount(). The destination buffer is obtained from __getname(), which allocates from name_cachep, which is initialized by vfs_caches_init() for size PATH_MAX. We're safe as long as PATH_MAX <= PAGE_SIZE. PATH_MAX is 4096. As far as I know, the smallest PAGE_SIZE is also 4096. Here's a patch that makes the code a bit more obviously correct. It doesn't depend on PATH_MAX <= PAGE_SIZE. Signed-off-by: Markus Armbruster Cc: Latchesar Ionkov Cc: Jim Meyering Cc: "Randy.Dunlap" Signed-off-by: Andrew Morton Signed-off-by: Eric Van Hensbergen --- include/linux/parser.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/parser.h b/include/linux/parser.h index 26b2bdfcaf06..7dcd05075756 100644 --- a/include/linux/parser.h +++ b/include/linux/parser.h @@ -29,5 +29,5 @@ int match_token(char *, match_table_t table, substring_t args[]); int match_int(substring_t *, int *result); int match_octal(substring_t *, int *result); int match_hex(substring_t *, int *result); -void match_strcpy(char *, const substring_t *); +size_t match_strlcpy(char *, const substring_t *, size_t); char *match_strdup(const substring_t *); -- cgit v1.2.3 From ee443996a35c1e04f210cafd43d5a98d41e46085 Mon Sep 17 00:00:00 2001 From: Eric Van Hensbergen Date: Wed, 5 Mar 2008 07:08:09 -0600 Subject: 9p: Documentation updates The kernel-doc comments of much of the 9p system have been in disarray since reorganization. This patch fixes those problems, adds additional documentation and a template book which collects the 9p information. Signed-off-by: Eric Van Hensbergen --- include/net/9p/9p.h | 239 +++++++++++++++++++++++++++++++++++++++------ include/net/9p/client.h | 35 +++++++ include/net/9p/transport.h | 43 ++++++++ 3 files changed, 287 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h index 585eb4496990..7bfb2f2e423c 100644 --- a/include/net/9p/9p.h +++ b/include/net/9p/9p.h @@ -29,14 +29,31 @@ #ifdef CONFIG_NET_9P_DEBUG -#define P9_DEBUG_ERROR (1<<0) -#define P9_DEBUG_9P (1<<2) -#define P9_DEBUG_VFS (1<<3) -#define P9_DEBUG_CONV (1<<4) -#define P9_DEBUG_MUX (1<<5) -#define P9_DEBUG_TRANS (1<<6) -#define P9_DEBUG_SLABS (1<<7) -#define P9_DEBUG_FCALL (1<<8) +/** + * enum p9_debug_flags - bits for mount time debug parameter + * @P9_DEBUG_ERROR: more verbose error messages including original error string + * @P9_DEBUG_9P: 9P protocol tracing + * @P9_DEBUG_VFS: VFS API tracing + * @P9_DEBUG_CONV: protocol conversion tracing + * @P9_DEBUG_MUX: trace management of concurrent transactions + * @P9_DEBUG_TRANS: transport tracing + * @P9_DEBUG_SLABS: memory management tracing + * @P9_DEBUG_FCALL: verbose dump of protocol messages + * + * These flags are passed at mount time to turn on various levels of + * verbosity and tracing which will be output to the system logs. + */ + +enum p9_debug_flags { + P9_DEBUG_ERROR = (1<<0), + P9_DEBUG_9P = (1<<2), + P9_DEBUG_VFS = (1<<3), + P9_DEBUG_CONV = (1<<4), + P9_DEBUG_MUX = (1<<5), + P9_DEBUG_TRANS = (1<<6), + P9_DEBUG_SLABS = (1<<7), + P9_DEBUG_FCALL = (1<<8), +}; extern unsigned int p9_debug_level; @@ -62,9 +79,47 @@ do { \ format , __FUNCTION__, task_pid_nr(current), ## arg); \ } while (0) +/** + * enum p9_msg_t - 9P message types + * @P9_TVERSION: version handshake request + * @P9_RVERSION: version handshake response + * @P9_TAUTH: request to establish authentication channel + * @P9_RAUTH: response with authentication information + * @P9_TATTACH: establish user access to file service + * @P9_RATTACH: response with top level handle to file hierarchy + * @P9_TERROR: not used + * @P9_RERROR: response for any failed request + * @P9_TFLUSH: request to abort a previous request + * @P9_RFLUSH: response when previous request has been cancelled + * @P9_TWALK: descend a directory hierarchy + * @P9_RWALK: response with new handle for position within hierarchy + * @P9_TOPEN: prepare a handle for I/O on an existing file + * @P9_ROPEN: response with file access information + * @P9_TCREATE: prepare a handle for I/O on a new file + * @P9_RCREATE: response with file access information + * @P9_TREAD: request to transfer data from a file or directory + * @P9_RREAD: response with data requested + * @P9_TWRITE: reuqest to transfer data to a file + * @P9_RWRITE: response with out much data was transfered to file + * @P9_TCLUNK: forget about a handle to an entity within the file system + * @P9_RCLUNK: response when server has forgotten about the handle + * @P9_TREMOVE: request to remove an entity from the hierarchy + * @P9_RREMOVE: response when server has removed the entity + * @P9_TSTAT: request file entity attributes + * @P9_RSTAT: response with file entity attributes + * @P9_TWSTAT: request to update file entity attributes + * @P9_RWSTAT: response when file entity attributes are updated + * + * There are 14 basic operations in 9P2000, paired as + * requests and responses. The one special case is ERROR + * as there is no @P9_TERROR request for clients to transmit to + * the server, but the server may respond to any other request + * with an @P9_RERROR. + * + * See Also: http://plan9.bell-labs.com/sys/man/5/INDEX.html + */ -/* Message Types */ -enum { +enum p9_msg_t { P9_TVERSION = 100, P9_RVERSION, P9_TAUTH = 102, @@ -95,30 +150,71 @@ enum { P9_RWSTAT, }; -/* open modes */ -enum { +/** + * enum p9_open_mode_t - 9P open modes + * @P9_OREAD: open file for reading only + * @P9_OWRITE: open file for writing only + * @P9_ORDWR: open file for reading or writing + * @P9_OEXEC: open file for execution + * @P9_OTRUNC: truncate file to zero-length before opening it + * @P9_OREXEC: close the file when an exec(2) system call is made + * @P9_ORCLOSE: remove the file when the file is closed + * @P9_OAPPEND: open the file and seek to the end + * @P9_OEXCL: only create a file, do not open it + * + * 9P open modes differ slightly from Posix standard modes. + * In particular, there are extra modes which specify different + * semantic behaviors than may be available on standard Posix + * systems. For example, @P9_OREXEC and @P9_ORCLOSE are modes that + * most likely will not be issued from the Linux VFS client, but may + * be supported by servers. + * + * See Also: http://plan9.bell-labs.com/magic/man2html/2/open + */ + +enum p9_open_mode_t { P9_OREAD = 0x00, P9_OWRITE = 0x01, P9_ORDWR = 0x02, P9_OEXEC = 0x03, - P9_OEXCL = 0x04, P9_OTRUNC = 0x10, P9_OREXEC = 0x20, P9_ORCLOSE = 0x40, P9_OAPPEND = 0x80, -}; - -/* permissions */ -enum { + P9_OEXCL = 0x1000, +}; + +/** + * enum p9_perm_t - 9P permissions + * @P9_DMDIR: mode bite for directories + * @P9_DMAPPEND: mode bit for is append-only + * @P9_DMEXCL: mode bit for excluse use (only one open handle allowed) + * @P9_DMMOUNT: mode bite for mount points + * @P9_DMAUTH: mode bit for authentication file + * @P9_DMTMP: mode bit for non-backed-up files + * @P9_DMSYMLINK: mode bit for symbolic links (9P2000.u) + * @P9_DMLINK: mode bit for hard-link (9P2000.u) + * @P9_DMDEVICE: mode bit for device files (9P2000.u) + * @P9_DMNAMEDPIPE: mode bit for named pipe (9P2000.u) + * @P9_DMSOCKET: mode bit for socket (9P2000.u) + * @P9_DMSETUID: mode bit for setuid (9P2000.u) + * @P9_DMSETGID: mode bit for setgid (9P2000.u) + * @P9_DMSETVTX: mode bit for sticky bit (9P2000.u) + * + * 9P permissions differ slightly from Posix standard modes. + * + * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat + */ +enum p9_perm_t { P9_DMDIR = 0x80000000, P9_DMAPPEND = 0x40000000, P9_DMEXCL = 0x20000000, P9_DMMOUNT = 0x10000000, P9_DMAUTH = 0x08000000, P9_DMTMP = 0x04000000, +/* 9P2000.u extensions */ P9_DMSYMLINK = 0x02000000, P9_DMLINK = 0x01000000, - /* 9P2000.u extensions */ P9_DMDEVICE = 0x00800000, P9_DMNAMEDPIPE = 0x00200000, P9_DMSOCKET = 0x00100000, @@ -127,8 +223,26 @@ enum { P9_DMSETVTX = 0x00010000, }; -/* qid.types */ -enum { +/** + * enum p9_qid_t - QID types + * @P9_QTDIR: directory + * @P9_QTAPPEND: append-only + * @P9_QTEXCL: excluse use (only one open handle allowed) + * @P9_QTMOUNT: mount points + * @P9_QTAUTH: authentication file + * @P9_QTTMP: non-backed-up files + * @P9_QTSYMLINK: symbolic links (9P2000.u) + * @P9_QTLINK: hard-link (9P2000.u) + * @P9_QTFILE: normal files + * + * QID types are a subset of permissions - they are primarily + * used to differentiate semantics for a file system entity via + * a jump-table. Their value is also the most signifigant 16 bits + * of the permission_t + * + * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat + */ +enum p9_qid_t { P9_QTDIR = 0x80, P9_QTAPPEND = 0x40, P9_QTEXCL = 0x20, @@ -140,6 +254,7 @@ enum { P9_QTFILE = 0x00, }; +/* 9P Magic Numbers */ #define P9_NOTAG (u16)(~0) #define P9_NOFID (u32)(~0) #define P9_MAXWELEM 16 @@ -147,19 +262,69 @@ enum { /* ample room for Twrite/Rread header */ #define P9_IOHDRSZ 24 +/** + * struct p9_str - length prefixed string type + * @len: length of the string + * @str: the string + * + * The protocol uses length prefixed strings for all + * string data, so we replicate that for our internal + * string members. + */ + struct p9_str { u16 len; char *str; }; -/* qids are the unique ID for a file (like an inode */ +/** + * struct p9_qid - file system entity information + * @type: 8-bit type &p9_qid_t + * @version: 16-bit monotonically incrementing version number + * @path: 64-bit per-server-unique ID for a file system element + * + * qids are identifiers used by 9P servers to track file system + * entities. The type is used to differentiate semantics for operations + * on the entity (ie. read means something different on a directory than + * on a file). The path provides a server unique index for an entity + * (roughly analogous to an inode number), while the version is updated + * every time a file is modified and can be used to maintain cache + * coherency between clients and serves. + * Servers will often differentiate purely synthetic entities by setting + * their version to 0, signaling that they should never be cached and + * should be accessed synchronously. + * + * See Also://plan9.bell-labs.com/magic/man2html/2/stat + */ + struct p9_qid { u8 type; u32 version; u64 path; }; -/* Plan 9 file metadata (stat) structure */ +/** + * struct p9_stat - file system metadata information + * @size: length prefix for this stat structure instance + * @type: the type of the server (equivilent to a major number) + * @dev: the sub-type of the server (equivilent to a minor number) + * @qid: unique id from the server of type &p9_qid + * @mode: Plan 9 format permissions of type &p9_perm_t + * @atime: Last access/read time + * @mtime: Last modify/write time + * @length: file length + * @name: last element of path (aka filename) in type &p9_str + * @uid: owner name in type &p9_str + * @gid: group owner in type &p9_str + * @muid: last modifier in type &p9_str + * @extension: area used to encode extended UNIX support in type &p9_str + * @n_uid: numeric user id of owner (part of 9p2000.u extension) + * @n_gid: numeric group id (part of 9p2000.u extension) + * @n_muid: numeric user id of laster modifier (part of 9p2000.u extension) + * + * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat + */ + struct p9_stat { u16 size; u16 type; @@ -179,10 +344,14 @@ struct p9_stat { u32 n_muid; /* 9p2000.u extensions */ }; -/* file metadata (stat) structure used to create Twstat message - The is similar to p9_stat, but the strings don't point to - the same memory block and should be freed separately -*/ +/* + * file metadata (stat) structure used to create Twstat message + * The is identical to &p9_stat, but the strings don't point to + * the same memory block and should be freed separately + * + * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat + */ + struct p9_wstat { u16 size; u16 type; @@ -335,10 +504,20 @@ struct p9_twstat { struct p9_rwstat { }; -/* - * fcall is the primary packet structure - * - */ +/** + * struct p9_fcall - primary packet structure + * @size: prefixed length of the structure + * @id: protocol operating identifier of type &p9_msg_t + * @tag: transaction id of the request + * @sdata: payload + * @params: per-operation parameters + * + * &p9_fcall represents the structure for all 9P RPC + * transactions. Requests are packaged into fcalls, and reponses + * must be extracted from them. + * + * See Also: http://plan9.bell-labs.com/magic/man2html/2/fcall + */ struct p9_fcall { u32 size; diff --git a/include/net/9p/client.h b/include/net/9p/client.h index e52f93d9ac5f..c936dd14de41 100644 --- a/include/net/9p/client.h +++ b/include/net/9p/client.h @@ -26,6 +26,23 @@ #ifndef NET_9P_CLIENT_H #define NET_9P_CLIENT_H +/** + * struct p9_client - per client instance state + * @lock: protect @fidlist + * @msize: maximum data size negotiated by protocol + * @dotu: extension flags negotiated by protocol + * @trans_mod: module API instantiated with this client + * @trans: tranport instance state and API + * @conn: connection state information used by trans_fd + * @fidpool: fid handle accounting for session + * @fidlist: List of active fid handles + * + * The client structure is used to keep track of various per-client + * state that has been instantiated. + * + * Bugs: duplicated data and potentially unnecessary elements. + */ + struct p9_client { spinlock_t lock; /* protect client structure */ int msize; @@ -38,6 +55,24 @@ struct p9_client { struct list_head fidlist; }; +/** + * struct p9_fid - file system entity handle + * @clnt: back pointer to instantiating &p9_client + * @fid: numeric identifier for this handle + * @mode: current mode of this fid (enum?) + * @qid: the &p9_qid server identifier this handle points to + * @iounit: the server reported maximum transaction size for this file + * @uid: the numeric uid of the local user who owns this handle + * @aux: transport specific information (unused?) + * @rdir_fpos: tracks offset of file position when reading directory contents + * @rdir_pos: (unused?) + * @rdir_fcall: holds response of last directory read request + * @flist: per-client-instance fid tracking + * @dlist: per-dentry fid tracking + * + * TODO: This needs lots of explanation. + */ + struct p9_fid { struct p9_client *clnt; u32 fid; diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h index d2209ae9d18b..240e0de888c6 100644 --- a/include/net/9p/transport.h +++ b/include/net/9p/transport.h @@ -26,12 +26,40 @@ #ifndef NET_9P_TRANSPORT_H #define NET_9P_TRANSPORT_H +/** + * enum p9_trans_status - different states of underlying transports + * @Connected: transport is connected and healthy + * @Disconnected: transport has been disconnected + * @Hung: transport is connected by wedged + * + * This enumeration details the various states a transport + * instatiation can be in. + */ + enum p9_trans_status { Connected, Disconnected, Hung, }; +/** + * struct p9_trans - per-transport state and API + * @status: transport &p9_trans_status + * @msize: negotiated maximum packet size (duplicate from client) + * @extended: negotiated protocol extensions (duplicate from client) + * @priv: transport private data + * @close: member function to disconnect and close the transport + * @rpc: member function to issue a request to the transport + * + * This is the basic API for a transport instance. It is used as + * a handle by the client to issue requests. This interface is currently + * in flux during reorganization. + * + * Bugs: there is lots of duplicated data here and its not clear that + * the member functions need to be per-instance versus per transport + * module. + */ + struct p9_trans { enum p9_trans_status status; int msize; @@ -42,6 +70,21 @@ struct p9_trans { struct p9_fcall **rc); }; +/** + * struct p9_trans_module - transport module interface + * @list: used to maintain a list of currently available transports + * @name: the human-readable name of the transport + * @maxsize: transport provided maximum packet size + * @def: set if this transport should be considered the default + * @create: member function to create a new connection on this transport + * + * This is the basic API for a transport module which is registered by the + * transport module with the 9P core network module and used by the client + * to instantiate a new connection on a transport. + * + * Bugs: the transport module list isn't protected. + */ + struct p9_trans_module { struct list_head list; char *name; /* name of transport */ -- cgit v1.2.3 From 887b3ece65be7b643dfdae0d433c91a26a3f437d Mon Sep 17 00:00:00 2001 From: Eric Van Hensbergen Date: Thu, 8 May 2008 20:26:37 -0500 Subject: 9p: fix error path during early mount There was some cleanup issues during early mount which would trigger a kernel bug for certain types of failure. This patch reorganizes the cleanup to get rid of the bad behavior. This also merges the 9pnet and 9pnet_fd modules for the purpose of configuration and initialization. Keeping the fd transport separate from the core 9pnet code seemed like a good idea at the time, but in practice has caused more harm and confusion than good. Signed-off-by: Eric Van Hensbergen --- include/net/9p/9p.h | 1 + include/net/9p/transport.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h index 7bfb2f2e423c..b3d3e27c6299 100644 --- a/include/net/9p/9p.h +++ b/include/net/9p/9p.h @@ -595,4 +595,5 @@ int p9_idpool_check(int id, struct p9_idpool *p); int p9_error_init(void); int p9_errstr2errno(char *, int); +int p9_trans_fd_init(void); #endif /* NET_9P_H */ diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h index 240e0de888c6..0db3a4038dc0 100644 --- a/include/net/9p/transport.h +++ b/include/net/9p/transport.h @@ -96,5 +96,4 @@ struct p9_trans_module { void v9fs_register_trans(struct p9_trans_module *m); struct p9_trans_module *v9fs_match_trans(const substring_t *name); struct p9_trans_module *v9fs_default_trans(void); - #endif /* NET_9P_TRANSPORT_H */ -- cgit v1.2.3 From b7cffc1f29c1bc729bc50c863c87f93f9b70994b Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 14 May 2008 16:05:42 -0700 Subject: asm-{alpha,h8300,um,v850,xtensa}/param.h: unbreak HZ for userspace I noticed this because alpha was broken due to the recent commit commit bdc807871d58285737d50dc6163d0feb72cb0dc2 ("avoid overflows in kernel/time.c"). Most arches do something like this in their asm/param.h: #ifdef __KERNEL__ # define HZ CONFIG_HZ #else # define HZ 100 #endif A few arches though (namely alpha/h8300/um/v850/xtensa) either do no set HZ at all for !__KERNEL__, or they set it wrongly. This should bring all arches in line by setting up HZ for userspace. Without this currently perl 5.10 doesn't build on alpha: perl.c: In function 'perl_construct': perl.c:388: error: 'CONFIG_HZ' undeclared (first use in this function) -> http://buildd.debian.org/fetch.cgi?pkg=perl;ver=5.10.0-10;arch=alpha;stamp=1210252894 Signed-off-by: Mike Frysinger Cc: Richard Henderson Cc: Ivan Kokshaysky Cc: Yoshinori Sato Cc: Jeff Dike Cc: Chris Zankel Cc: maximilian attems Signed-off-by: Andrew Morton [ HZ on alpha is 1024 for historical reasons. - Linus ] Signed-off-by: Linus Torvalds --- include/asm-alpha/param.h | 4 ++++ include/asm-h8300/param.h | 8 +++----- include/asm-um/param.h | 2 ++ include/asm-v850/param.h | 2 ++ include/asm-xtensa/param.h | 2 ++ 5 files changed, 13 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h index 0982f1d39499..e691ecfedb2c 100644 --- a/include/asm-alpha/param.h +++ b/include/asm-alpha/param.h @@ -5,8 +5,12 @@ hardware ignores reprogramming. We also need userland buy-in to the change in HZ, since this is visible in the wait4 resources etc. */ +#ifdef __KERNEL__ #define HZ CONFIG_HZ #define USER_HZ HZ +#else +#define HZ 1024 +#endif #define EXEC_PAGESIZE 8192 diff --git a/include/asm-h8300/param.h b/include/asm-h8300/param.h index 04f64f100379..1c72fb8080ff 100644 --- a/include/asm-h8300/param.h +++ b/include/asm-h8300/param.h @@ -1,14 +1,12 @@ #ifndef _H8300_PARAM_H #define _H8300_PARAM_H - -#ifndef HZ -#define HZ CONFIG_HZ -#endif - #ifdef __KERNEL__ +#define HZ CONFIG_HZ #define USER_HZ HZ #define CLOCKS_PER_SEC (USER_HZ) +#else +#define HZ 100 #endif #define EXEC_PAGESIZE 4096 diff --git a/include/asm-um/param.h b/include/asm-um/param.h index 4cd4a226f8c1..e44f4e60d16d 100644 --- a/include/asm-um/param.h +++ b/include/asm-um/param.h @@ -13,6 +13,8 @@ #define HZ CONFIG_HZ #define USER_HZ 100 /* .. some user interfaces are in "ticks" */ #define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ +#else +#define HZ 100 #endif #endif diff --git a/include/asm-v850/param.h b/include/asm-v850/param.h index 281832690290..4391f5fe0204 100644 --- a/include/asm-v850/param.h +++ b/include/asm-v850/param.h @@ -26,6 +26,8 @@ # define HZ CONFIG_HZ # define USER_HZ 100 # define CLOCKS_PER_SEC USER_HZ +#else +# define HZ 100 #endif #endif /* __V850_PARAM_H__ */ diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h index 82ad34d92d35..ba03d5aeab6b 100644 --- a/include/asm-xtensa/param.h +++ b/include/asm-xtensa/param.h @@ -15,6 +15,8 @@ # define HZ CONFIG_HZ /* internal timer frequency */ # define USER_HZ 100 /* for user interfaces in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */ +#else +# define HZ 100 #endif #define EXEC_PAGESIZE 4096 -- cgit v1.2.3 From 3fc957721d18c93662f7d4dab455b80f53dd2641 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Wed, 14 May 2008 16:05:49 -0700 Subject: lib: create common ascii hex array Add a common hex array in hexdump.c so everyone can use it. Add a common hi/lo helper to avoid the shifting masking that is done to get the upper and lower nibbles of a byte value. Pull the pack_hex_byte helper from kgdb as it is opencoded many places in the tree that will be consolidated. Signed-off-by: Harvey Harrison Acked-by: Paul Mundt Cc: Jason Wessel Cc: Ingo Molnar Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/kernel.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 4d46e299afb5..792bf0aa779b 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -276,7 +276,17 @@ extern void print_hex_dump(const char *level, const char *prefix_str, const void *buf, size_t len, bool ascii); extern void print_hex_dump_bytes(const char *prefix_str, int prefix_type, const void *buf, size_t len); -#define hex_asc(x) "0123456789abcdef"[x] + +extern const char hex_asc[]; +#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] +#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] + +static inline char *pack_hex_byte(char *buf, u8 byte) +{ + *buf++ = hex_asc_hi(byte); + *buf++ = hex_asc_lo(byte); + return buf; +} #define pr_emerg(fmt, arg...) \ printk(KERN_EMERG fmt, ##arg) -- cgit v1.2.3 From 44c81433e8b05dbc85985d939046f10f95901184 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 14 May 2008 16:05:51 -0700 Subject: per_cpu: fix DEFINE_PER_CPU_SHARED_ALIGNED for modules Current module loader lookups ".data.percpu" ELF section to perform per_cpu relocation. But DEFINE_PER_CPU_SHARED_ALIGNED() uses another section (".data.percpu.shared_aligned"), currently only handled in vmlinux.lds, not by module loader. To correct this problem, instead of adding logic into module loader, or using at build time a module.lds file for all arches to group ".data.percpu.shared_aligned" into ".data.percpu", just use ".data.percpu" for modules. Alignment requirements are correctly handled by ld and module loader. Signed-off-by: Eric Dumazet Cc: Rusty Russell Cc: Fenghua Yu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/percpu.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/percpu.h b/include/linux/percpu.h index d746a2abb322..4cdd393e71e1 100644 --- a/include/linux/percpu.h +++ b/include/linux/percpu.h @@ -13,8 +13,14 @@ __attribute__((__section__(".data.percpu"))) \ PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name +#ifdef MODULE +#define SHARED_ALIGNED_SECTION ".data.percpu" +#else +#define SHARED_ALIGNED_SECTION ".data.percpu.shared_aligned" +#endif + #define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ - __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __attribute__((__section__(SHARED_ALIGNED_SECTION))) \ PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name \ ____cacheline_aligned_in_smp #else -- cgit v1.2.3 From 1c12c4cf9411eb130b245fa8d0fbbaf989477c7b Mon Sep 17 00:00:00 2001 From: Venki Pallipadi Date: Wed, 14 May 2008 16:05:51 -0700 Subject: mprotect: prevent alteration of the PAT bits There is a defect in mprotect, which lets the user change the page cache type bits by-passing the kernel reserve_memtype and free_memtype wrappers. Fix the problem by not letting mprotect change the PAT bits. Signed-off-by: Venkatesh Pallipadi Signed-off-by: Suresh Siddha Signed-off-by: Ingo Molnar Signed-off-by: Hugh Dickins Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-x86/pgtable.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h index 801b31f71452..55c3a0e3a8ce 100644 --- a/include/asm-x86/pgtable.h +++ b/include/asm-x86/pgtable.h @@ -57,7 +57,8 @@ #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | \ _PAGE_DIRTY) -#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) +#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_PCD | _PAGE_PWT | \ + _PAGE_ACCESSED | _PAGE_DIRTY) #define _PAGE_CACHE_MASK (_PAGE_PCD | _PAGE_PWT) #define _PAGE_CACHE_WB (0) @@ -288,12 +289,21 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) * Chop off the NX bit (if present), and add the NX portion of * the newprot (if present): */ - val &= _PAGE_CHG_MASK & ~_PAGE_NX; - val |= pgprot_val(newprot) & __supported_pte_mask; + val &= _PAGE_CHG_MASK; + val |= pgprot_val(newprot) & (~_PAGE_CHG_MASK) & __supported_pte_mask; return __pte(val); } +/* mprotect needs to preserve PAT bits when updating vm_page_prot */ +#define pgprot_modify pgprot_modify +static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) +{ + pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; + pgprotval_t addbits = pgprot_val(newprot); + return __pgprot(preservebits | addbits); +} + #define pte_pgprot(x) __pgprot(pte_val(x) & (0xfff | _PAGE_NX)) #define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask) -- cgit v1.2.3 From cec08e7a948326b01555be6311480aa08e637de2 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 30 Apr 2008 15:41:48 +1000 Subject: [POWERPC] vmemmap fixes to use smaller pages This changes vmemmap to use a different region (region 0xf) of the address space, and to configure the page size of that region dynamically at boot. The problem with the current approach of always using 16M pages is that it's not well suited to machines that have small amounts of memory such as small partitions on pseries, or PS3's. In fact, on the PS3, failure to allocate the 16M page backing vmmemmap tends to prevent hotplugging the HV's "additional" memory, thus limiting the available memory even more, from my experience down to something like 80M total, which makes it really not very useable. The logic used by my match to choose the vmemmap page size is: - If 16M pages are available and there's 1G or more RAM at boot, use that size. - Else if 64K pages are available, use that - Else use 4K pages I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages) and it seems to work fine. Note that I intend to change the way we organize the kernel regions & SLBs so the actual region will change from 0xf back to something else at one point, as I simplify the SLB miss handler, but that will be for a later patch. Signed-off-by: Paul Mackerras --- include/asm-powerpc/mmu-hash64.h | 1 + include/asm-powerpc/pgtable-ppc64.h | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h index 0dff76776044..39c5c5f62bf5 100644 --- a/include/asm-powerpc/mmu-hash64.h +++ b/include/asm-powerpc/mmu-hash64.h @@ -177,6 +177,7 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; extern int mmu_linear_psize; extern int mmu_virtual_psize; extern int mmu_vmalloc_psize; +extern int mmu_vmemmap_psize; extern int mmu_io_psize; extern int mmu_kernel_ssize; extern int mmu_highuser_ssize; diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h index 27f18695f7d6..cc6a43ba41d0 100644 --- a/include/asm-powerpc/pgtable-ppc64.h +++ b/include/asm-powerpc/pgtable-ppc64.h @@ -65,15 +65,15 @@ #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START)) #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET)) +#define VMEMMAP_REGION_ID (0xfUL) #define USER_REGION_ID (0UL) /* - * Defines the address of the vmemap area, in the top 16th of the - * kernel region. + * Defines the address of the vmemap area, in its own region */ -#define VMEMMAP_BASE (ASM_CONST(CONFIG_KERNEL_START) + \ - (0xfUL << (REGION_SHIFT - 4))) -#define vmemmap ((struct page *)VMEMMAP_BASE) +#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT) +#define vmemmap ((struct page *)VMEMMAP_BASE) + /* * Common bits in a linux-style PTE. These match the bits in the -- cgit v1.2.3 From 9c8387afdc93f90bf0241411d44e011d8d5b76df Mon Sep 17 00:00:00 2001 From: Nate Case Date: Tue, 13 May 2008 06:14:14 +1000 Subject: [POWERPC] Fix uninitialized variable bug in copy_{to|from}_user Calls to copy_to_user() or copy_from_user() can fail when copying N bytes, where N is a constant less than 8, but not 1, 2, 4, or 8, because 'ret' is not initialized and is only set if the size is 1, 2, 4 or 8, but is tested after the switch statement for any constant size <= 8. This fixes it by initializing 'ret' to 1, causing the code to fall through to the __copy_tofrom_user call for sizes other than 1, 2, 4 or 8. Signed-off-by: Dave Scidmore Signed-off-by: Nate Case Signed-off-by: Paul Mackerras --- include/asm-powerpc/uaccess.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h index 8e798e3758bc..1a0736f8803f 100644 --- a/include/asm-powerpc/uaccess.h +++ b/include/asm-powerpc/uaccess.h @@ -380,7 +380,7 @@ static inline unsigned long __copy_from_user_inatomic(void *to, const void __user *from, unsigned long n) { if (__builtin_constant_p(n) && (n <= 8)) { - unsigned long ret; + unsigned long ret = 1; switch (n) { case 1: @@ -406,7 +406,7 @@ static inline unsigned long __copy_to_user_inatomic(void __user *to, const void *from, unsigned long n) { if (__builtin_constant_p(n) && (n <= 8)) { - unsigned long ret; + unsigned long ret = 1; switch (n) { case 1: -- cgit v1.2.3 From 9e491e54f0589cc26e2c096664e9d95493b1af29 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Wed, 14 May 2008 16:21:54 -0700 Subject: parisc: new termios definitions Signed-off-by: Alan Cox Cc: Kyle McMartin Cc: Grant Grundler Cc: Matthew Wilcox Signed-off-by: Andrew Morton Signed-off-by: Kyle McMartin --- include/asm-parisc/ioctls.h | 4 ++++ include/asm-parisc/termbits.h | 5 ++++- include/asm-parisc/termios.h | 6 ++++-- 3 files changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-parisc/ioctls.h b/include/asm-parisc/ioctls.h index ee84e4172c36..6747fad07a3e 100644 --- a/include/asm-parisc/ioctls.h +++ b/include/asm-parisc/ioctls.h @@ -46,6 +46,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID _IOR('T', 20, int) /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-parisc/termbits.h b/include/asm-parisc/termbits.h index e847fe979684..d8bbc73b16b7 100644 --- a/include/asm-parisc/termbits.h +++ b/include/asm-parisc/termbits.h @@ -141,6 +141,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -156,10 +157,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 diff --git a/include/asm-parisc/termios.h b/include/asm-parisc/termios.h index 5345b3420475..a2a57a4548af 100644 --- a/include/asm-parisc/termios.h +++ b/include/asm-parisc/termios.h @@ -80,8 +80,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ -- cgit v1.2.3 From 5cbbf16a0fab91662af8400b5ada658990932a87 Mon Sep 17 00:00:00 2001 From: Cornelia Huck Date: Thu, 15 May 2008 16:52:35 +0200 Subject: [S390] s390dbf: Use const char * for dbf name. We should use const char * for passing the name of the debug feature around since it will not be changed. Signed-off-by: Cornelia Huck Signed-off-by: Martin Schwidefsky --- include/asm-s390/debug.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-s390/debug.h b/include/asm-s390/debug.h index 335baf4fc64f..9450ce6e32de 100644 --- a/include/asm-s390/debug.h +++ b/include/asm-s390/debug.h @@ -120,10 +120,10 @@ debug_entry_t* debug_exception_common(debug_info_t* id, int level, /* Debug Feature API: */ -debug_info_t* debug_register(char* name, int pages, int nr_areas, +debug_info_t *debug_register(const char *name, int pages, int nr_areas, int buf_size); -debug_info_t *debug_register_mode(char *name, int pages, int nr_areas, +debug_info_t *debug_register_mode(const char *name, int pages, int nr_areas, int buf_size, mode_t mode, uid_t uid, gid_t gid); -- cgit v1.2.3 From f54d8a1b3fef79bb1aa2f0840dd356ce7bb180f9 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Wed, 14 May 2008 15:14:52 -0400 Subject: parisc: Remove ioctl.h content picked up from . Now that allows overriding of the most commonly changed macro values, take advantage of that. Signed-off-by: Robert P. J. Day Signed-off-by: Kyle McMartin --- include/asm-parisc/ioctl.h | 51 +--------------------------------------------- 1 file changed, 1 insertion(+), 50 deletions(-) (limited to 'include') diff --git a/include/asm-parisc/ioctl.h b/include/asm-parisc/ioctl.h index 68338d2bda4e..ec8efa02beda 100644 --- a/include/asm-parisc/ioctl.h +++ b/include/asm-parisc/ioctl.h @@ -32,21 +32,6 @@ * NOTE: This limits the max parameter size to 16kB -1 ! */ -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 -#define _IOC_SIZEBITS 14 -#define _IOC_DIRBITS 2 - -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - /* * Direction bits. */ @@ -54,40 +39,6 @@ #define _IOC_WRITE 2U #define _IOC_READ 1U -#define _IOC(dir,type,nr,size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __invalid_size_argument_for_IOC; -#define _IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ - sizeof(t) : __invalid_size_argument_for_IOC) - -/* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode ioctl numbers.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* ...and for the drivers/sound files... */ - -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) +#include #endif /* _ASM_PARISC_IOCTL_H */ -- cgit v1.2.3 From 872f6debcae63309eb39bfc2cc9462fb83450ee0 Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Thu, 15 May 2008 10:53:57 -0400 Subject: parisc: use conditional macro for 64-bit wide ops This work enables us to remove -traditional from $AFLAGS on parisc. Signed-off-by: Kyle McMartin --- include/asm-parisc/assembly.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h index 5587f0023881..ffb208840ecc 100644 --- a/include/asm-parisc/assembly.h +++ b/include/asm-parisc/assembly.h @@ -31,9 +31,8 @@ #define STREGM std,ma #define SHRREG shrd #define SHLREG shld -#define ADDIB addib,* -#define CMPB cmpb,* #define ANDCM andcm,* +#define COND(x) * ## x #define RP_OFFSET 16 #define FRAME_SIZE 128 #define CALLEE_REG_FRAME_SIZE 144 @@ -46,9 +45,8 @@ #define STREGM stwm #define SHRREG shr #define SHLREG shlw -#define ADDIB addib, -#define CMPB cmpb, #define ANDCM andcm +#define COND(x) x #define RP_OFFSET 20 #define FRAME_SIZE 64 #define CALLEE_REG_FRAME_SIZE 128 -- cgit v1.2.3 From a442ac512f36981182e66a427ad05f449ff6593b Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 15 May 2008 17:50:37 -0700 Subject: Clean up 'print_fn_descriptor_symbol()' types Everybody wants to pass it a function pointer, and in fact, that is what you _must_ pass it for it to make sense (since it knows that ia64 and ppc64 use descriptors for function pointers and fetches the actual address from there). So don't make the argument be a 'unsigned long' and force everybody to add a cast. Signed-off-by: Linus Torvalds --- include/linux/kallsyms.h | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h index 82de2fb62cb7..00c1801099fa 100644 --- a/include/linux/kallsyms.h +++ b/include/linux/kallsyms.h @@ -83,16 +83,6 @@ __attribute__((format(printf,1,2))); static inline void __check_printsym_format(const char *fmt, ...) { } -/* ia64 and ppc64 use function descriptors, which contain the real address */ -#if defined(CONFIG_IA64) || defined(CONFIG_PPC64) -#define print_fn_descriptor_symbol(fmt, addr) \ -do { \ - unsigned long *__faddr = (unsigned long*) addr; \ - print_symbol(fmt, __faddr[0]); \ -} while (0) -#else -#define print_fn_descriptor_symbol(fmt, addr) print_symbol(fmt, addr) -#endif static inline void print_symbol(const char *fmt, unsigned long addr) { @@ -101,6 +91,20 @@ static inline void print_symbol(const char *fmt, unsigned long addr) __builtin_extract_return_addr((void *)addr)); } +/* + * Pretty-print a function pointer. + * + * ia64 and ppc64 function pointers are really function descriptors, + * which contain a pointer the real address. + */ +static inline void print_fn_descriptor_symbol(const char *fmt, void *addr) +{ +#if defined(CONFIG_IA64) || defined(CONFIG_PPC64) + addr = *(void **)addr; +#endif + print_symbol(fmt, (unsigned long)addr); +} + #ifndef CONFIG_64BIT #define print_ip_sym(ip) \ do { \ -- cgit v1.2.3