From 25458fdd39a18a5ce00c36f38992da54bb7453f3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:31 +0000 Subject: dt-bindings: clock: renesas: Document RZ/G3E SoC CPG Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h (limited to 'include') diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ -- cgit v1.2.3