From f9bb7acb9b19a40dbd9d1b89380335dc8e23925f Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 24 Feb 2017 18:23:55 +0100 Subject: gpu: ipu-v3: add unsynchronised DP channel disabling When disabling the foreground DP channel during a modeset, the DC is already disabled without waiting for end of frame. There is no reason to wait for a frame boundary before updating the DP registers in that case. Add support to apply updates immediately. No functional changes, yet. Signed-off-by: Philipp Zabel Reviewed-by: Lucas Stach --- include/video/imx-ipu-v3.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h index 53cd07ccaa4c..899d2b00ad6d 100644 --- a/include/video/imx-ipu-v3.h +++ b/include/video/imx-ipu-v3.h @@ -300,7 +300,7 @@ struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); void ipu_dp_put(struct ipu_dp *); int ipu_dp_enable(struct ipu_soc *ipu); int ipu_dp_enable_channel(struct ipu_dp *dp); -void ipu_dp_disable_channel(struct ipu_dp *dp); +void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync); void ipu_dp_disable(struct ipu_soc *ipu); int ipu_dp_setup_channel(struct ipu_dp *dp, enum ipu_color_space in, enum ipu_color_space out); -- cgit v1.2.3 From ba2b5277dc52cc96944d9765281bdf1e12681f66 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 9 Jan 2015 11:05:13 +0100 Subject: drm: add RGB formats with separate alpha plane Some hardware can read the alpha components separately and then conditionally fetch color components only for non-zero alpha values. This patch adds fourcc definitions for two-plane RGB formats with an 8-bit alpha channel on a second plane. Signed-off-by: Philipp Zabel --- include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index ef20abb8119b..995c8f9c692f 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -113,6 +113,20 @@ extern "C" { #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ +/* + * 2 plane RGB + A + * index 0 = RGB plane, same format as the corresponding non _A8 format has + * index 1 = A plane, [7:0] A + */ +#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') +#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') +#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') +#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') +#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') +#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') +#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') +#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') + /* * 2 plane YCbCr * index 0 = Y plane, [7:0] Y -- cgit v1.2.3 From e72db3b1e50febff493bc5e3fb57da9cb8cc3d91 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 9 Jan 2015 11:03:13 +0100 Subject: gpu: ipu-v3: add support for separate alpha channels The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven by the Alpha Transparency Controller (ATC) for the graphics IDMAC channels. This allows to reduce memory bandwidth via a conditional read mechanism or to support planar YUV formats with alpha transparency. Signed-off-by: Philipp Zabel --- include/video/imx-ipu-v3.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h index 899d2b00ad6d..6af74f0cf161 100644 --- a/include/video/imx-ipu-v3.h +++ b/include/video/imx-ipu-v3.h @@ -161,6 +161,28 @@ enum ipu_channel_irq { #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52 #define IPUV3_NUM_CHANNELS 64 +static inline int ipu_channel_alpha_channel(int ch_num) +{ + switch (ch_num) { + case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: + return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA; + case IPUV3_CHANNEL_G_MEM_IC_PP: + return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA; + case IPUV3_CHANNEL_MEM_FG_SYNC: + return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA; + case IPUV3_CHANNEL_MEM_FG_ASYNC: + return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA; + case IPUV3_CHANNEL_MEM_BG_SYNC: + return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA; + case IPUV3_CHANNEL_MEM_BG_ASYNC: + return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA; + case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: + return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA; + default: + return -EINVAL; + } +} + int ipu_map_irq(struct ipu_soc *ipu, int irq); int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, enum ipu_channel_irq irq); -- cgit v1.2.3 From ea9c260514c15f14d43a4c099646c44238dccf1e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 8 Mar 2017 12:13:16 +0100 Subject: gpu: ipu-v3: add driver for Prefetch Resolve Gasket This adds support for the i.MX6 QUadPlus PRG unit. It glues together the IPU and the PRE units. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel --- v4: add missing ipu_soc->prg_priv --- include/video/imx-ipu-v3.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h index 6af74f0cf161..8cb07680fb41 100644 --- a/include/video/imx-ipu-v3.h +++ b/include/video/imx-ipu-v3.h @@ -330,6 +330,21 @@ int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, bool bg_chan); +/* + * IPU Prefetch Resolve Gasket (prg) functions + */ +int ipu_prg_max_active_channels(void); +bool ipu_prg_present(struct ipu_soc *ipu); +bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, + uint64_t modifier); +int ipu_prg_enable(struct ipu_soc *ipu); +void ipu_prg_disable(struct ipu_soc *ipu); +void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan); +int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, + unsigned int axi_id, unsigned int width, + unsigned int height, unsigned int stride, + u32 format, unsigned long *eba); + /* * IPU CMOS Sensor Interface (csi) functions */ -- cgit v1.2.3