From 288440de9e5fdb4a3ff73864850f080c1250fc81 Mon Sep 17 00:00:00 2001 From: Swapnil Jakhade Date: Tue, 28 Jun 2022 15:22:50 +0300 Subject: dt-bindings: phy: Add PHY_TYPE_USXGMII definition Add definition for USXGMII phy type. Cc: Rob Herring Signed-off-by: Swapnil Jakhade Signed-off-by: Roger Quadros Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220628122255.24265-3-rogerq@kernel.org Signed-off-by: Vinod Koul --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index f48c9acf251e..6b901b342348 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -22,5 +22,6 @@ #define PHY_TYPE_QSGMII 9 #define PHY_TYPE_DPHY 10 #define PHY_TYPE_CPHY 11 +#define PHY_TYPE_USXGMII 12 #endif /* _DT_BINDINGS_PHY */ -- cgit v1.2.3 From 2e9bffc4f713db465177238f6033f7d367d6f151 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 25 Aug 2022 21:38:34 +0200 Subject: phy: rockchip: Support PCIe v3 RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add data-lanes property for splitting pcie-lanes across controllers. The data-lanes is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by: Shawn Lin Suggested-by: Peter Geis Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.de Signed-off-by: Vinod Koul --- include/linux/phy/pcie.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/linux/phy/pcie.h (limited to 'include') diff --git a/include/linux/phy/pcie.h b/include/linux/phy/pcie.h new file mode 100644 index 000000000000..e7ac81764576 --- /dev/null +++ b/include/linux/phy/pcie.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ +#ifndef __PHY_PCIE_H +#define __PHY_PCIE_H + +#define PHY_MODE_PCIE_RC 20 +#define PHY_MODE_PCIE_EP 21 +#define PHY_MODE_PCIE_BIFURCATION 22 + +#endif -- cgit v1.2.3