From e55ef16b840f03749b290549ec3ffc4c07f550be Mon Sep 17 00:00:00 2001 From: Huqiang Qin Date: Fri, 14 Jul 2023 20:24:40 +0800 Subject: dt-bindings: pinctrl: Add compatibles for Amlogic C3 SoCs Add a new compatible name for Amlogic C3 pin controller, and add a new dt-binding header file which document the detail pin names. Signed-off-by: Huqiang Qin Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij --- include/dt-bindings/gpio/amlogic-c3-gpio.h | 72 ++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 include/dt-bindings/gpio/amlogic-c3-gpio.h (limited to 'include') diff --git a/include/dt-bindings/gpio/amlogic-c3-gpio.h b/include/dt-bindings/gpio/amlogic-c3-gpio.h new file mode 100644 index 000000000000..75c8da6f505f --- /dev/null +++ b/include/dt-bindings/gpio/amlogic-c3-gpio.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin + */ + +#ifndef _DT_BINDINGS_AMLOGIC_C3_GPIO_H +#define _DT_BINDINGS_AMLOGIC_C3_GPIO_H + +#define GPIOE_0 0 +#define GPIOE_1 1 +#define GPIOE_2 2 +#define GPIOE_3 3 +#define GPIOE_4 4 + +#define GPIOB_0 5 +#define GPIOB_1 6 +#define GPIOB_2 7 +#define GPIOB_3 8 +#define GPIOB_4 9 +#define GPIOB_5 10 +#define GPIOB_6 11 +#define GPIOB_7 12 +#define GPIOB_8 13 +#define GPIOB_9 14 +#define GPIOB_10 15 +#define GPIOB_11 16 +#define GPIOB_12 17 +#define GPIOB_13 18 +#define GPIOB_14 19 + +#define GPIOC_0 20 +#define GPIOC_1 21 +#define GPIOC_2 22 +#define GPIOC_3 23 +#define GPIOC_4 24 +#define GPIOC_5 25 +#define GPIOC_6 26 + +#define GPIOX_0 27 +#define GPIOX_1 28 +#define GPIOX_2 29 +#define GPIOX_3 30 +#define GPIOX_4 31 +#define GPIOX_5 32 +#define GPIOX_6 33 +#define GPIOX_7 34 +#define GPIOX_8 35 +#define GPIOX_9 36 +#define GPIOX_10 37 +#define GPIOX_11 38 +#define GPIOX_12 39 +#define GPIOX_13 40 + +#define GPIOD_0 41 +#define GPIOD_1 42 +#define GPIOD_2 43 +#define GPIOD_3 44 +#define GPIOD_4 45 +#define GPIOD_5 46 +#define GPIOD_6 47 + +#define GPIOA_0 48 +#define GPIOA_1 49 +#define GPIOA_2 50 +#define GPIOA_3 51 +#define GPIOA_4 52 +#define GPIOA_5 53 + +#define GPIO_TEST_N 54 + +#endif /* _DT_BINDINGS_AMLOGIC_C3_GPIO_H */ -- cgit v1.2.3 From 03ffa9af3a5ff88f9855b18584d00aca7eb43e6d Mon Sep 17 00:00:00 2001 From: Dhaval Shah Date: Mon, 31 Jul 2023 15:20:23 +0530 Subject: firmware: xilinx: Add support to get platform information Add function to get family code and sub family code from the idcode. This family code and sub family code helps to identify the platform. Family code of any platform is on bits 21 to 27 and Sub family code is on bits 19 and 20. Signed-off-by: Dhaval Shah Signed-off-by: Sai Krishna Potthuri Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20230731095026.3766675-2-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij --- include/linux/firmware/xlnx-zynqmp.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9dda7d9898ff..f0b341c1c847 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -34,6 +34,17 @@ /* PM API versions */ #define PM_API_VERSION_2 2 +#define ZYNQMP_FAMILY_CODE 0x23 +#define VERSAL_FAMILY_CODE 0x26 + +/* When all subfamily of platform need to support */ +#define ALL_SUB_FAMILY_CODE 0x00 +#define VERSAL_SUB_FAMILY_CODE 0x01 +#define VERSALNET_SUB_FAMILY_CODE 0x03 + +#define FAMILY_CODE_MASK GENMASK(27, 21) +#define SUB_FAMILY_CODE_MASK GENMASK(20, 19) + /* ATF only commands */ #define TF_A_PM_REGISTER_SGI 0xa04 #define PM_GET_TRUSTZONE_VERSION 0xa03 -- cgit v1.2.3 From aa5ed7b3fb3939ca6a3605c6fdc7399bb219ec23 Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Mon, 31 Jul 2023 15:20:24 +0530 Subject: firmware: xilinx: Add version check for TRISTATE configuration Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx ZynqMP Platform Management Firmware) Configuration Param Set version 2.0. If the requested configuration is TRISTATE and platform is ZYNQMP then check the version before requesting Xilinx firmware to set the configuration. Signed-off-by: Sai Krishna Potthuri Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20230731095026.3766675-3-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij --- include/linux/firmware/xlnx-zynqmp.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index f0b341c1c847..e8b12ec8b060 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -34,6 +34,8 @@ /* PM API versions */ #define PM_API_VERSION_2 2 +#define PM_PINCTRL_PARAM_SET_VERSION 2 + #define ZYNQMP_FAMILY_CODE 0x23 #define VERSAL_FAMILY_CODE 0x26 -- cgit v1.2.3 From 0e8ec0226e849e251276d4d77d1f1ae809c045d2 Mon Sep 17 00:00:00 2001 From: Huqiang Qin Date: Mon, 24 Jul 2023 14:01:06 +0800 Subject: dt-bindings: interrupt-controller: Add header file for Amlogic Meson-G12A SoCs Add a new dt-binding header that details the interrupt number of the GPIO. Signed-off-by: Huqiang Qin Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230724060108.1403662-2-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij --- .../amlogic,meson-g12a-gpio-intc.h | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h (limited to 'include') diff --git a/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h b/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h new file mode 100644 index 000000000000..bd415cb7b669 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin + */ + +#ifndef _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H +#define _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H + +/* IRQID[11:0] - GPIOAO[11:0] */ +#define IRQID_GPIOAO_0 0 +#define IRQID_GPIOAO_1 1 +#define IRQID_GPIOAO_2 2 +#define IRQID_GPIOAO_3 3 +#define IRQID_GPIOAO_4 4 +#define IRQID_GPIOAO_5 5 +#define IRQID_GPIOAO_6 6 +#define IRQID_GPIOAO_7 7 +#define IRQID_GPIOAO_8 8 +#define IRQID_GPIOAO_9 9 +#define IRQID_GPIOAO_10 10 +#define IRQID_GPIOAO_11 11 + +/* IRQID[27:12] - GPIOZ[15:0] */ +#define IRQID_GPIOZ_0 12 +#define IRQID_GPIOZ_1 13 +#define IRQID_GPIOZ_2 14 +#define IRQID_GPIOZ_3 15 +#define IRQID_GPIOZ_4 16 +#define IRQID_GPIOZ_5 17 +#define IRQID_GPIOZ_6 18 +#define IRQID_GPIOZ_7 19 +#define IRQID_GPIOZ_8 20 +#define IRQID_GPIOZ_9 21 +#define IRQID_GPIOZ_10 22 +#define IRQID_GPIOZ_11 23 +#define IRQID_GPIOZ_12 24 +#define IRQID_GPIOZ_13 25 +#define IRQID_GPIOZ_14 26 +#define IRQID_GPIOZ_15 27 + +/* IRQID[36:28] - GPIOH[8:0] */ +#define IRQID_GPIOH_0 28 +#define IRQID_GPIOH_1 29 +#define IRQID_GPIOH_2 30 +#define IRQID_GPIOH_3 31 +#define IRQID_GPIOH_4 32 +#define IRQID_GPIOH_5 33 +#define IRQID_GPIOH_6 34 +#define IRQID_GPIOH_7 35 +#define IRQID_GPIOH_8 36 + +/* IRQID[52:37] - BOOT[15:0] */ +#define IRQID_BOOT_0 37 +#define IRQID_BOOT_1 38 +#define IRQID_BOOT_2 39 +#define IRQID_BOOT_3 40 +#define IRQID_BOOT_4 41 +#define IRQID_BOOT_5 42 +#define IRQID_BOOT_6 43 +#define IRQID_BOOT_7 44 +#define IRQID_BOOT_8 45 +#define IRQID_BOOT_9 46 +#define IRQID_BOOT_10 47 +#define IRQID_BOOT_11 48 +#define IRQID_BOOT_12 49 +#define IRQID_BOOT_13 50 +#define IRQID_BOOT_14 51 +#define IRQID_BOOT_15 52 + +/* IRQID[60:53] - GPIOC[7:0] */ +#define IRQID_GPIOC_0 53 +#define IRQID_GPIOC_1 54 +#define IRQID_GPIOC_2 55 +#define IRQID_GPIOC_3 56 +#define IRQID_GPIOC_4 57 +#define IRQID_GPIOC_5 58 +#define IRQID_GPIOC_6 59 +#define IRQID_GPIOC_7 60 + +/* IRQID[76:61] - GPIOA[15:0] */ +#define IRQID_GPIOA_0 61 +#define IRQID_GPIOA_1 62 +#define IRQID_GPIOA_2 63 +#define IRQID_GPIOA_3 64 +#define IRQID_GPIOA_4 65 +#define IRQID_GPIOA_5 66 +#define IRQID_GPIOA_6 67 +#define IRQID_GPIOA_7 68 +#define IRQID_GPIOA_8 69 +#define IRQID_GPIOA_9 70 +#define IRQID_GPIOA_10 71 +#define IRQID_GPIOA_11 72 +#define IRQID_GPIOA_12 73 +#define IRQID_GPIOA_13 74 +#define IRQID_GPIOA_14 75 +#define IRQID_GPIOA_15 76 + +/* IRQID[96:77] - GPIOX[19:0] */ +#define IRQID_GPIOX_0 77 +#define IRQID_GPIOX_1 78 +#define IRQID_GPIOX_2 79 +#define IRQID_GPIOX_3 80 +#define IRQID_GPIOX_4 81 +#define IRQID_GPIOX_5 82 +#define IRQID_GPIOX_6 83 +#define IRQID_GPIOX_7 84 +#define IRQID_GPIOX_8 85 +#define IRQID_GPIOX_9 86 +#define IRQID_GPIOX_10 87 +#define IRQID_GPIOX_11 88 +#define IRQID_GPIOX_12 89 +#define IRQID_GPIOX_13 90 +#define IRQID_GPIOX_14 91 +#define IRQID_GPIOX_15 92 +#define IRQID_GPIOX_16 93 +#define IRQID_GPIOX_17 94 +#define IRQID_GPIOX_18 95 +#define IRQID_GPIOX_19 96 + +/* IRQID[99:97] - GPIOE[2:0] */ +#define IRQID_GPIOE_0 97 +#define IRQID_GPIOE_1 98 +#define IRQID_GPIOE_2 99 + +#endif /* _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H */ -- cgit v1.2.3 From 2a6c0b4777ae51222b6d9d5d5687bd6cbf9ed4f8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:12 +0300 Subject: pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper _DEFINE_DEV_PM_OPS() helps to define PM operations for the system sleep and/or runtime PM cases. Some of the existing users want to have _noirq() variants to be set. For that purpose introduce a new helper which sets up _noirq() callbacks to be assigned and struct dev_pm_ops be provided. Acked-by: "Rafael J. Wysocki" Reviewed-by: Jonathan Cameron Reviewed-by: Paul Cercueil Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230717172821.62827-2-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- include/linux/pm.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/linux/pm.h b/include/linux/pm.h index badad7d11f4f..1400c37b29c7 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -448,6 +448,15 @@ const struct dev_pm_ops __maybe_unused name = { \ SET_RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn) \ } +/* + * Use this if you want to have the suspend and resume callbacks be called + * with IRQs disabled. + */ +#define DEFINE_NOIRQ_DEV_PM_OPS(name, suspend_fn, resume_fn) \ +const struct dev_pm_ops name = { \ + NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \ +} + #define pm_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM), (_ptr)) #define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr)) -- cgit v1.2.3