From cfb6f26035b17d5d280ce4a6ceb041438643ba63 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 15 Nov 2007 23:42:11 +0000 Subject: [MIPS] Fix pcspeaker build. Signed-off-by: Ralf Baechle --- include/asm-mips/8253pit.h | 10 ---------- include/asm-mips/i8253.h | 2 ++ 2 files changed, 2 insertions(+), 10 deletions(-) delete mode 100644 include/asm-mips/8253pit.h (limited to 'include') diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h deleted file mode 100644 index 285f78488ccb..000000000000 --- a/include/asm-mips/8253pit.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * 8253/8254 Programmable Interval Timer - */ - -#ifndef _8253PIT_H -#define _8253PIT_H - -#define PIT_TICK_RATE 1193182UL - -#endif diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h index 032ca73f181b..5dabc870b322 100644 --- a/include/asm-mips/i8253.h +++ b/include/asm-mips/i8253.h @@ -12,6 +12,8 @@ #define PIT_CH0 0x40 #define PIT_CH2 0x42 +#define PIT_TICK_RATE 1193182UL + extern spinlock_t i8253_lock; extern void setup_pit_timer(void); -- cgit v1.2.3 From 98ce472181e760a552314850c238b14bbf3f04ec Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 30 Oct 2007 15:43:44 +0000 Subject: [MIPS] IP32: More interrupt renumbering fixes. Signed-off-by: Ralf Baechle --- include/asm-mips/ip32/ip32_ints.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h index ab5612f90f6f..85bc5302bce0 100644 --- a/include/asm-mips/ip32/ip32_ints.h +++ b/include/asm-mips/ip32/ip32_ints.h @@ -22,7 +22,7 @@ enum ip32_irq_no { * CPU interrupts are 0 ... 7 */ - CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE, + CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8, /* * MACE -- cgit v1.2.3 From 07500b0d855b7f3f47ca263b21b6397d743d45d2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 30 Oct 2007 17:25:26 +0000 Subject: [MIPS] Fix context DSP context / TLS pointer switching bug for new threads. A new born thread starts execution not in schedule but rather in ret_from_fork which results in it bypassing the part of the code to load a new context written in C which are the DSP context and the userlocal register which Linux uses for the TLS pointer. Frequently we were just getting away with this bug for a number of reasons: o Real world application scenarios are very unlikely to use clone or fork in blocks of DSP code. o Linux by default runs the child process right after the fork, so the child by luck will find all the right context in the DSP and userlocal registers. o So far the rdhwr instruction was emulated on all hardware so userlocal wasn't getting referenced at all and the emulation wasn't suffering from the issue since it gets it's value straight from the thread's thread_info. Fixed by moving the code to load the context from switch_to() to finish_arch_switch which will be called by newborn and old threads. Signed-off-by: Ralf Baechle --- include/asm-mips/system.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 90e4b403f531..1030562d6ea6 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -68,11 +68,15 @@ do { \ if (cpu_has_dsp) \ __save_dsp(prev); \ (last) = resume(prev, next, task_thread_info(next)); \ +} while (0) + +#define finish_arch_switch(prev) \ +do { \ if (cpu_has_dsp) \ __restore_dsp(current); \ if (cpu_has_userlocal) \ - write_c0_userlocal(task_thread_info(current)->tp_value);\ -} while(0) + write_c0_userlocal(current_thread_info()->tp_value); \ +} while (0) static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { -- cgit v1.2.3 From 0f67e90e1caea4a0a14d2c60102547bce29f7f08 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 20 Nov 2007 10:44:18 +0000 Subject: [MIPS] Fix possible hang in LL/SC futex loops. The LL / SC loops in __futex_atomic_op() have the usual fixups necessary for memory acccesses to userspace from kernel space installed: __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: ll %1, %4 # __futex_atomic_op \n" " .set mips0 \n" " " insn " \n" " .set mips3 \n" "2: sc $1, %2 \n" " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .set mips0 \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" " j 2b \n" <----- " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) : "memory"); The branch at the end of the fixup code, it goes back to the SC instruction, no matter if the fault was first taken by the LL or SC instruction resulting in an endless loop which will only terminate if the address become valid again due to another thread setting up an accessible mapping and the CPU happens to execute the SC instruction successfully which due to the preceeding ERET instruction of the fault handler would only happen if UNPREDICTABLE instruction behaviour of the SC instruction without a preceeding LL happens to favor that outcome. But normally processes are nice, pass valid arguments and we were just getting away with this. Thanks to Kaz Kylheku for providing the original report and a test case. Signed-off-by: Ralf Baechle --- include/asm-mips/futex.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index 3e7e30d4f418..17f082cfea85 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -35,7 +35,7 @@ " .set mips0 \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %6 \n" \ - " j 2b \n" \ + " j 3b \n" \ " .previous \n" \ " .section __ex_table,\"a\" \n" \ " "__UA_ADDR "\t1b, 4b \n" \ @@ -61,7 +61,7 @@ " .set mips0 \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %6 \n" \ - " j 2b \n" \ + " j 3b \n" \ " .previous \n" \ " .section __ex_table,\"a\" \n" \ " "__UA_ADDR "\t1b, 4b \n" \ @@ -200,4 +200,4 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) } #endif -#endif +#endif /* _ASM_FUTEX_H */ -- cgit v1.2.3 From 5aa85c9fc49a6ce44dc10a42e2011bbde9dc445a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 21 Nov 2007 16:39:44 +0000 Subject: [MIPS] Handle R4000/R4400 mfc0 from count register. The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source. --- include/asm-mips/time.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index ee1663e64da1..1922494a0d9e 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -58,11 +58,12 @@ extern int (*perf_irq)(void); * Initialize the calling CPU's compare interrupt as clockevent device */ #ifdef CONFIG_CEVT_R4K -extern void mips_clockevent_init(void); +extern int mips_clockevent_init(void); extern unsigned int __weak get_c0_compare_int(void); #else -static inline void mips_clockevent_init(void) +static inline int mips_clockevent_init(void) { + return -ENXIO; } #endif -- cgit v1.2.3 From 940f6b48a130e0a33cb8bd397dd0e277166470ad Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 24 Nov 2007 22:33:28 +0000 Subject: [MIPS] Only build r4k clocksource for systems that work ok with it. In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle --- include/asm-mips/time.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index 1922494a0d9e..7717934f94c3 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -67,6 +67,17 @@ static inline int mips_clockevent_init(void) } #endif +/* + * Initialize the count register as a clocksource + */ +#ifdef CONFIG_CEVT_R4K +extern void init_mips_clocksource(void); +#else +static inline void init_mips_clocksource(void) +{ +} +#endif + extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); extern void clockevent_set_clock(struct clock_event_device *cd, unsigned int clock); -- cgit v1.2.3 From cce335ae47e231398269fb05fa48e0e9cbf289e0 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 3 Nov 2007 02:05:43 +0000 Subject: [MIPS] 64-bit Sibyte kernels need DMA32. Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle --- include/asm-mips/dma.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h index 833437d31ef1..d6a6c21f16db 100644 --- a/include/asm-mips/dma.h +++ b/include/asm-mips/dma.h @@ -92,6 +92,7 @@ #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) #endif #define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) +#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT)) /* 8237 DMA controllers */ #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ -- cgit v1.2.3