From 02ab3f70791f7d5c9098acaa31a72dd7d0961cb0 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 18 Jul 2007 17:25:09 +0900 Subject: sh: intc - shared IPR and INTC2 controller This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- include/asm-sh/hw_irq.h | 68 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'include') diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 4ca3f765bacc..34ff8c7cfb55 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -1,6 +1,7 @@ #ifndef __ASM_SH_HW_IRQ_H #define __ASM_SH_HW_IRQ_H +#include #include extern atomic_t irq_err_count; @@ -47,4 +48,71 @@ void init_IRQ_ipr(void); */ void ipr_irq_enable_irlm(void); +typedef unsigned char intc_enum; + +struct intc_vect { + intc_enum enum_id; + unsigned short vect; +}; + +#define INTC_VECT(enum_id, vect) { enum_id, vect } + +struct intc_prio { + intc_enum enum_id; + unsigned char priority; +}; + +#define INTC_PRIO(enum_id, prio) { enum_id, prio } + +struct intc_group { + intc_enum enum_id; + intc_enum *enum_ids; +}; + +#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } } + +struct intc_mask_reg { + unsigned long set_reg, clr_reg, reg_width; + intc_enum enum_ids[32]; +}; + +struct intc_prio_reg { + unsigned long reg, reg_width, field_width; + intc_enum enum_ids[16]; +}; + +struct intc_sense_reg { + unsigned long reg, reg_width, field_width; + intc_enum enum_ids[16]; +}; + +struct intc_desc { + struct intc_vect *vectors; + unsigned int nr_vectors; + struct intc_group *groups; + unsigned int nr_groups; + struct intc_prio *priorities; + unsigned int nr_priorities; + struct intc_mask_reg *mask_regs; + unsigned int nr_mask_regs; + struct intc_prio_reg *prio_regs; + unsigned int nr_prio_regs; + struct intc_sense_reg *sense_regs; + unsigned int nr_sense_regs; + struct irq_chip chip; +}; + +#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) +#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ + priorities, mask_regs, prio_regs, sense_regs) \ +static struct intc_desc symbol = { \ + _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ + _INTC_ARRAY(priorities), \ + _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ + _INTC_ARRAY(sense_regs), \ + .chip.name = chipname, \ +} + +void __init register_intc_controller(struct intc_desc *desc); + #endif /* __ASM_SH_HW_IRQ_H */ -- cgit v1.2.3 From 1b06428ee56fadedd004bfc5e3fbb39fb8c99010 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 18 Jul 2007 17:51:24 +0900 Subject: sh: intc - add support for 7722 processor This patch converts the cpu specific 7722 setup code to use the new intc controller. Many new vectors are added and also support for external interrupt sense configuration. So with this patch it is now possible to configure external interrupt pins as edge or level triggered using set_irq_type(). Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- include/asm-sh/hw_irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 34ff8c7cfb55..6c21cf0dd51f 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -105,7 +105,7 @@ struct intc_desc { #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ priorities, mask_regs, prio_regs, sense_regs) \ -static struct intc_desc symbol = { \ +struct intc_desc symbol = { \ _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ _INTC_ARRAY(priorities), \ _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ -- cgit v1.2.3 From 493a358e0a8992ec13098dd084223b55b05a7f03 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 18 Jul 2007 17:54:10 +0900 Subject: sh: clean up interrupt code for solution engine 7722 board This patch cleans up solution engine 7722 specific interrupt code. The main purpose is to replace the mux function with use of set_irq_chained_handler() and replace hard coded register poking code with set_irq_type(). The board specific interrupts are also moved to start from SE7722_FPGA_IRQ_BASE. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- include/asm-sh/se7722.h | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/asm-sh/se7722.h b/include/asm-sh/se7722.h index b3b31e4725c6..e0e89fcb8388 100644 --- a/include/asm-sh/se7722.h +++ b/include/asm-sh/se7722.h @@ -81,36 +81,32 @@ /* IRQ */ #define IRQ0_IRQ 32 #define IRQ1_IRQ 33 -#define INTC_ICR0 0xA4140000UL -#define INTC_ICR1 0xA414001CUL - -#define INTMSK0 0xa4140044 -#define INTMSKCLR0 0xa4140064 -#define INTC_INTPRI0 0xa4140010 #define IRQ01_MODE 0xb1800000 #define IRQ01_STS 0xb1800004 #define IRQ01_MASK 0xb1800008 -#define EXT_BIT (0x3fc0) /* SH IRQ1 */ -#define MRSHPC_BIT0 (0x0004) /* SH IRQ1 */ -#define MRSHPC_BIT1 (0x0008) /* SH IRQ1 */ -#define MRSHPC_BIT2 (0x0010) /* SH IRQ1 */ -#define MRSHPC_BIT3 (0x0020) /* SH IRQ1 */ -#define SMC_BIT (0x0002) /* SH IRQ0 */ -#define USB_BIT (0x0001) /* SH IRQ0 */ - -#define MRSHPC_IRQ3 11 -#define MRSHPC_IRQ2 12 -#define MRSHPC_IRQ1 13 -#define MRSHPC_IRQ0 14 -#define SMC_IRQ 10 -#define EXT_IRQ 5 -#define USB_IRQ 6 +/* Bits in IRQ01_* registers */ + +#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ +#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ +#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ + +#define SE7722_FPGA_IRQ_NR 6 +#define SE7722_FPGA_IRQ_BASE 110 + +#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3) +#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2) +#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1) +#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0) +#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC) +#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB) /* arch/sh/boards/se/7722/irq.c */ void init_se7722_IRQ(void); -int se7722_irq_demux(int); #define __IO_PREFIX se7722 #include -- cgit v1.2.3 From 90015c89386ffb8967422fbe9f5e7babf1dc2c5e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 18 Jul 2007 17:57:34 +0900 Subject: sh: IPR/INTC2 IRQ setup consolidation. This patch unifies the cpu specific interrupt setup functions for interrupt controller blocks such as ipr, intc2 and intc. There is no point in having separate functions for each interrupt controller, so let's clean this up. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- include/asm-sh/hw_irq.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 6c21cf0dd51f..92c9efd9276c 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -23,7 +23,6 @@ struct intc2_desc { }; void register_intc2_controller(struct intc2_desc *); -void init_IRQ_intc2(void); struct ipr_data { unsigned char irq; @@ -41,7 +40,6 @@ struct ipr_desc { }; void register_ipr_controller(struct ipr_desc *); -void init_IRQ_ipr(void); /* * Enable individual interrupt mode for external IPR IRQs. @@ -115,4 +113,6 @@ struct intc_desc symbol = { \ void __init register_intc_controller(struct intc_desc *desc); +void __init plat_irq_setup(void); + #endif /* __ASM_SH_HW_IRQ_H */ -- cgit v1.2.3 From 39c7aa9ea9b6175f4313f69ef9f8e0a3a9bba5bb Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 20 Jul 2007 12:10:29 +0900 Subject: sh: intc - add support for 7780 This patch converts the cpu specific 7780 setup code to use the new intc controller. Many new vectors are added and also support for external interrupt sense configuration. So with this patch it is now possible to configure external interrupt pins as edge or level triggered using set_irq_type(). No external interrupts are registered by default. Use plat_irq_setup_pins() to select between IRQ or IRL mode. This patch also fixes the Alarm IRQ for the RTC. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- include/asm-sh/hw_irq.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 92c9efd9276c..8c5e11b3ae30 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -115,4 +115,7 @@ void __init register_intc_controller(struct intc_desc *desc); void __init plat_irq_setup(void); +enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; +void __init plat_irq_setup_pins(int mode); + #endif /* __ASM_SH_HW_IRQ_H */ -- cgit v1.2.3 From 0c99adb0a6dfe292842a8142b48e494d7731f5fe Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 20 Jul 2007 12:27:09 +0900 Subject: sh: Wire up fallocate() syscall. Signed-off-by: Paul Mundt --- include/asm-sh/unistd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h index 77bcb09d6ac8..b182b1cb05fd 100644 --- a/include/asm-sh/unistd.h +++ b/include/asm-sh/unistd.h @@ -332,8 +332,9 @@ #define __NR_signalfd 321 #define __NR_timerfd 322 #define __NR_eventfd 323 +#define __NR_fallocate 324 -#define NR_syscalls 324 +#define NR_syscalls 325 #ifdef __KERNEL__ -- cgit v1.2.3 From f6991b0456416186b578d38717efcda2b012b79c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 20 Jul 2007 13:29:09 +0900 Subject: sh: Implement clk_round_rate() in the clock framework. This is an optional component of the clock framework. However, as we're going to be using this in the cpufreq drivers, add support for it to the framework. Signed-off-by: Paul Mundt --- include/asm-sh/clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h index 386d797d86b7..b550a27a7042 100644 --- a/include/asm-sh/clock.h +++ b/include/asm-sh/clock.h @@ -14,6 +14,7 @@ struct clk_ops { void (*disable)(struct clk *clk); void (*recalc)(struct clk *clk); int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); + long (*round_rate)(struct clk *clk, unsigned long rate); }; struct clk { -- cgit v1.2.3 From 56386f6424f242cff46e2cfd7be44624cd37dce1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 20 Jul 2007 18:44:49 +0900 Subject: sh: intc - add support for SH7750 and its variants This patch converts the cpu specific 7750 setup code to use the new intc controller. Many new vectors are added and multiple processor variants including 7091, 7750, 7750s, 7750r, 7751 and 7751r should all have the correct vectors hooked up. IRLM interrupts can be enabled using ipr_irq_enable_irlm() which now is marked as __init. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- include/asm-sh/hw_irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 8c5e11b3ae30..20d42959f52a 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -44,7 +44,7 @@ void register_ipr_controller(struct ipr_desc *); /* * Enable individual interrupt mode for external IPR IRQs. */ -void ipr_irq_enable_irlm(void); +void __init ipr_irq_enable_irlm(void); typedef unsigned char intc_enum; -- cgit v1.2.3