From 08f01cc1d6e240092a6d9bfa21652622657f38f0 Mon Sep 17 00:00:00 2001 From: Gerald Loacker Date: Thu, 1 Dec 2022 08:22:18 +0100 Subject: iio: add struct declaration for iio types Add struct for iio type arrays such as IIO_AVAIL_LIST which can be used instead of int arrays. Signed-off-by: Gerald Loacker Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221201072220.402585-2-gerald.loacker@wolfvision.net Signed-off-by: Jonathan Cameron --- include/linux/iio/iio.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 8e0afaaa3f75..81413cd3a3e7 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -381,6 +381,11 @@ s64 iio_get_time_ns(const struct iio_dev *indio_dev); #define INDIO_MAX_RAW_ELEMENTS 4 +struct iio_val_int_plus_micro { + int integer; + int micro; +}; + struct iio_trigger; /* forward declaration */ /** -- cgit v1.2.3 From 1f5e408f6a000be980872b8065e547e2dbef6acc Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 7 Dec 2022 21:03:44 +0200 Subject: iio: light: tsl2563: Drop legacy platform data code There is no in-kernel user for legacy platform data. Otherwise, a new one can use software nodes instead. Hence, drop legacy platform data code. Signed-off-by: Andy Shevchenko Tested-by: Ferry Toth Link: https://lore.kernel.org/r/20221207190348.9347-7-andriy.shevchenko@linux.intel.com Signed-off-by: Jonathan Cameron --- include/linux/platform_data/tsl2563.h | 9 --------- 1 file changed, 9 deletions(-) delete mode 100644 include/linux/platform_data/tsl2563.h (limited to 'include') diff --git a/include/linux/platform_data/tsl2563.h b/include/linux/platform_data/tsl2563.h deleted file mode 100644 index 9cf9309c3f24..000000000000 --- a/include/linux/platform_data/tsl2563.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __LINUX_TSL2563_H -#define __LINUX_TSL2563_H - -struct tsl2563_platform_data { - int cover_comp_gain; -}; - -#endif /* __LINUX_TSL2563_H */ -- cgit v1.2.3 From e51c94dd9c7af3d84b19d1753ee118f999c6c8dd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 9 Jan 2023 02:29:32 +0200 Subject: dt-bindings: interconnect: qcom: drop IPA_CORE related defines These interconnects are modeled as clks, not interconnects, therefore remove corresponding defines from the binding as they're unused. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230109002935.244320-10-dmitry.baryshkov@linaro.org Signed-off-by: Georgi Djakov --- include/dt-bindings/interconnect/qcom,sc7180.h | 3 --- include/dt-bindings/interconnect/qcom,sc8180x.h | 3 --- include/dt-bindings/interconnect/qcom,sc8280xp.h | 4 ++-- include/dt-bindings/interconnect/qcom,sdx55.h | 2 -- include/dt-bindings/interconnect/qcom,sm8150.h | 3 --- include/dt-bindings/interconnect/qcom,sm8250.h | 3 --- 6 files changed, 2 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/interconnect/qcom,sc7180.h b/include/dt-bindings/interconnect/qcom,sc7180.h index f9970f6032eb..de5d5867bd67 100644 --- a/include/dt-bindings/interconnect/qcom,sc7180.h +++ b/include/dt-bindings/interconnect/qcom,sc7180.h @@ -108,9 +108,6 @@ #define SLAVE_LLCC 11 #define SLAVE_SERVICE_GEM_NOC 12 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI1 1 diff --git a/include/dt-bindings/interconnect/qcom,sc8180x.h b/include/dt-bindings/interconnect/qcom,sc8180x.h index e84cfec5afdd..0bdc8d6cb401 100644 --- a/include/dt-bindings/interconnect/qcom,sc8180x.h +++ b/include/dt-bindings/interconnect/qcom,sc8180x.h @@ -129,9 +129,6 @@ #define SLAVE_SERVICE_GEM_NOC 16 #define SLAVE_SERVICE_GEM_NOC_1 17 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sc8280xp.h b/include/dt-bindings/interconnect/qcom,sc8280xp.h index a3e5fda7c127..f89f47e99c6d 100644 --- a/include/dt-bindings/interconnect/qcom,sc8280xp.h +++ b/include/dt-bindings/interconnect/qcom,sc8280xp.h @@ -48,11 +48,11 @@ #define SLAVE_SERVICE_A2NOC 19 /* clk_virt */ -#define MASTER_IPA_CORE 0 +/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define MASTER_QUP_CORE_0 1 #define MASTER_QUP_CORE_1 2 #define MASTER_QUP_CORE_2 3 -#define SLAVE_IPA_CORE 4 +/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SLAVE_QUP_CORE_0 5 #define SLAVE_QUP_CORE_1 6 #define SLAVE_QUP_CORE_2 7 diff --git a/include/dt-bindings/interconnect/qcom,sdx55.h b/include/dt-bindings/interconnect/qcom,sdx55.h index bfb6524a2d90..1925f0784ab2 100644 --- a/include/dt-bindings/interconnect/qcom,sdx55.h +++ b/include/dt-bindings/interconnect/qcom,sdx55.h @@ -70,7 +70,5 @@ #define SLAVE_QDSS_STM 48 #define SLAVE_TCU 49 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 #endif diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h index a25684680c42..ef292791f52e 100644 --- a/include/dt-bindings/interconnect/qcom,sm8150.h +++ b/include/dt-bindings/interconnect/qcom,sm8150.h @@ -121,9 +121,6 @@ #define SLAVE_LLCC 15 #define SLAVE_SERVICE_GEM_NOC 16 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h index 1b4d9fbe888d..a4af5cc19271 100644 --- a/include/dt-bindings/interconnect/qcom,sm8250.h +++ b/include/dt-bindings/interconnect/qcom,sm8250.h @@ -115,9 +115,6 @@ #define SLAVE_SERVICE_GEM_NOC_2 15 #define SLAVE_SERVICE_GEM_NOC 16 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 -- cgit v1.2.3 From 338a588e9db3c5ea7a35bb332cb3bdb532fd1f08 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Mon, 16 Jan 2023 12:49:14 +0000 Subject: coresight: trace-id: Add API to dynamically assign Trace ID values The existing mechanism to assign Trace ID values to sources is limited and does not scale for larger multicore / multi trace source systems. The API introduces functions that reserve IDs based on availabilty represented by a coresight_trace_id_map structure. This records the used and free IDs in a bitmap. CPU bound sources such as ETMs use the coresight_trace_id_get_cpu_id coresight_trace_id_put_cpu_id pair of functions. The API will record the ID associated with the CPU. This ensures that the same ID will be re-used while perf events are active on the CPU. The put_cpu_id function will pend release of the ID until all perf cs_etm sessions are complete. For backward compatibility the functions will attempt to use the same CPU IDs as the legacy system would have used if these are still available. Non-cpu sources, such as the STM can use coresight_trace_id_get_system_id / coresight_trace_id_put_system_id. Signed-off-by: Mike Leach [ Fix checkpatch warning in drivers/hwtracing/coresight/coresight-trace-id.c ] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230116124928.5440-2-mike.leach@linaro.org --- include/linux/coresight-pmu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 6c2fd6cc5a98..ffff4e6277e5 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -10,6 +10,16 @@ #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools that may not update at the same time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. -- cgit v1.2.3 From 42708bac18cf7f09c058058cd4564f879c53b900 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Mon, 16 Jan 2023 12:49:20 +0000 Subject: coresight: etmX.X: stm: Remove trace_id() callback CoreSight sources provide a callback (.trace_id) in the standard source ops which returns the ID to the core code. This was used to check that sources all had a unique Trace ID. Uniqueness is now gauranteed by the Trace ID allocation system, and the check code has been removed from the core. This patch removes the unneeded and unused .trace_id source ops from the ops structure and implementations in etm3x, etm4x and stm. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230116124928.5440-8-mike.leach@linaro.org --- include/linux/coresight.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 1554021231f9..e241eb88dfb9 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -314,14 +314,11 @@ struct coresight_ops_link { * Operations available for sources. * @cpu_id: returns the value of the CPU number this component * is associated to. - * @trace_id: returns the value of the component's trace ID as known - * to the HW. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); - int (*trace_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, u32 mode); void (*disable)(struct coresight_device *csdev, -- cgit v1.2.3 From 206bb3858949b6509de75f7d3697303a073cbaa1 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Mon, 16 Jan 2023 12:49:21 +0000 Subject: coresight: trace id: Remove legacy get trace ID function. Removes legacy coresight_get_trace_id() function now its use has been removed from the ETM code. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230116124928.5440-9-mike.leach@linaro.org --- include/linux/coresight-pmu.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'include') diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index ffff4e6277e5..624f4843453e 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -8,7 +8,6 @@ #define _LINUX_CORESIGHT_PMU_H #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 /* * The legacy Trace ID system based on fixed calculation from the cpu @@ -44,15 +43,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif -- cgit v1.2.3 From aa19bb4c35834dd574b36d482cc44c78816e6fcd Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Mon, 16 Jan 2023 12:49:26 +0000 Subject: coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID Use the perf_report_aux_output_id() call to output the CoreSight trace ID and associated CPU as a PERF_RECORD_AUX_OUTPUT_HW_ID record in the perf.data file. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230116124928.5440-14-mike.leach@linaro.org --- include/linux/coresight-pmu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 624f4843453e..51ac441a37c3 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -7,6 +7,8 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" /* @@ -43,4 +45,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif -- cgit v1.2.3 From 0567461a7a6ecb12692e3bbb97e86ff9d39a2837 Mon Sep 17 00:00:00 2001 From: Li Li Date: Wed, 23 Nov 2022 12:16:54 -0800 Subject: binder: return pending info for frozen async txns An async transaction to a frozen process will still be successfully put in the queue. But this pending async transaction won't be processed until the target process is unfrozen at an unspecified time in the future. Pass this important information back to the user space caller by returning BR_TRANSACTION_PENDING_FROZEN. Signed-off-by: Li Li Acked-by: Carlos Llamas Link: https://lore.kernel.org/r/20221123201654.589322-2-dualli@chromium.org Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/android/binder.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/uapi/linux/android/binder.h b/include/uapi/linux/android/binder.h index e72e4de8f452..5f636b5afcd7 100644 --- a/include/uapi/linux/android/binder.h +++ b/include/uapi/linux/android/binder.h @@ -450,7 +450,7 @@ enum binder_driver_return_protocol { BR_FROZEN_REPLY = _IO('r', 18), /* - * The target of the last transaction (either a bcTRANSACTION or + * The target of the last sync transaction (either a bcTRANSACTION or * a bcATTEMPT_ACQUIRE) is frozen. No parameters. */ @@ -460,6 +460,11 @@ enum binder_driver_return_protocol { * asynchronous transaction makes the allocated async buffer size exceed * detection threshold. No parameters. */ + + BR_TRANSACTION_PENDING_FROZEN = _IO('r', 20), + /* + * The target of the last async transaction is frozen. No parameters. + */ }; enum binder_driver_command_protocol { -- cgit v1.2.3 From 81ccf4557105068eff754b5764c44c0f16c3ca66 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 10 Jan 2023 19:51:52 -0500 Subject: dt-bindings: interconnect: add sdm670 interconnects There are controllable interconnects on Snapdragon 670. Add the compatible strings to the documentation and interconnect ID definitions. The device tree header was generated by linux-interconnect-driver-generator and the copyright year was changed. Signed-off-by: Richard Acayan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230111005155.50452-2-mailingradian@gmail.com Signed-off-by: Georgi Djakov --- .../dt-bindings/interconnect/qcom,sdm670-rpmh.h | 136 +++++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sdm670-rpmh.h (limited to 'include') diff --git a/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h b/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h new file mode 100644 index 000000000000..9b516cc360bb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Qualcomm SDM670 interconnect IDs + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_BLSP_1 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_BLSP_2 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3 7 +#define SLAVE_A2NOC_SNOC 8 +#define SLAVE_SERVICE_A2NOC 9 + + +#define MASTER_SPDM 0 +#define MASTER_SNOC_CNOC 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AOP 4 +#define SLAVE_AOSS 5 +#define SLAVE_CAMERA_CFG 6 +#define SLAVE_CLK_CTL 7 +#define SLAVE_CDSP_CFG 8 +#define SLAVE_RBCPR_CX_CFG 9 +#define SLAVE_CRYPTO_0_CFG 10 +#define SLAVE_DCC_CFG 11 +#define SLAVE_CNOC_DDRSS 12 +#define SLAVE_DISPLAY_CFG 13 +#define SLAVE_EMMC_CFG 14 +#define SLAVE_GLM 15 +#define SLAVE_GRAPHICS_3D_CFG 16 +#define SLAVE_IMEM_CFG 17 +#define SLAVE_IPA_CFG 18 +#define SLAVE_CNOC_MNOC_CFG 19 +#define SLAVE_PDM 20 +#define SLAVE_SOUTH_PHY_CFG 21 +#define SLAVE_PIMEM_CFG 22 +#define SLAVE_PRNG 23 +#define SLAVE_QDSS_CFG 24 +#define SLAVE_BLSP_2 25 +#define SLAVE_BLSP_1 26 +#define SLAVE_SDCC_2 27 +#define SLAVE_SDCC_4 28 +#define SLAVE_SNOC_CFG 29 +#define SLAVE_SPDM_WRAPPER 30 +#define SLAVE_TCSR 31 +#define SLAVE_TLMM_NORTH 32 +#define SLAVE_TLMM_SOUTH 33 +#define SLAVE_TSIF 34 +#define SLAVE_UFS_MEM_CFG 35 +#define SLAVE_USB3 36 +#define SLAVE_VENUS_CFG 37 +#define SLAVE_VSENSE_CTRL_CFG 38 +#define SLAVE_CNOC_A2NOC 39 +#define SLAVE_SERVICE_CNOC 40 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GRAPHICS_3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI_CH0 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_APPSS 7 +#define SLAVE_SNOC_CNOC 8 +#define SLAVE_SNOC_MEM_NOC_GC 9 +#define SLAVE_SNOC_MEM_NOC_SF 10 +#define SLAVE_OCIMEM 11 +#define SLAVE_PIMEM 12 +#define SLAVE_SERVICE_SNOC 13 +#define SLAVE_QDSS_STM 14 +#define SLAVE_TCU 15 +#define MASTER_CAMNOC_HF0_UNCOMP 16 +#define MASTER_CAMNOC_HF1_UNCOMP 17 +#define MASTER_CAMNOC_SF_UNCOMP 18 +#define SLAVE_CAMNOC_UNCOMP 19 + +#endif -- cgit v1.2.3 From 2579af94c813d16bfabd81797f492fdfba25d088 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 18 Jan 2023 15:08:24 +0100 Subject: dt-bindings: interconnect: qcom: document the interconnects for sa8775p Add a DT binding document for the RPMh interconnects on Qualcomm sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230118140825.242544-2-brgl@bgdev.pl Signed-off-by: Georgi Djakov --- .../dt-bindings/interconnect/qcom,sa8775p-rpmh.h | 231 +++++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h (limited to 'include') diff --git a/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h b/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h new file mode 100644 index 000000000000..f21c39d0928e --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H + +/* aggre1_noc */ +#define MASTER_QUP_3 0 +#define MASTER_EMAC 1 +#define MASTER_EMAC_1 2 +#define MASTER_SDC 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB2 5 +#define MASTER_USB3_0 6 +#define MASTER_USB3_1 7 +#define SLAVE_A1NOC_SNOC 8 + +/* aggre2_noc */ +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_1 2 +#define MASTER_QUP_2 3 +#define MASTER_CNOC_A2NOC 4 +#define MASTER_CRYPTO_CORE0 5 +#define MASTER_CRYPTO_CORE1 6 +#define MASTER_IPA 7 +#define MASTER_QDSS_ETR_0 8 +#define MASTER_QDSS_ETR_1 9 +#define MASTER_UFS_CARD 10 +#define SLAVE_A2NOC_SNOC 11 + +/* clk_virt */ +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define SLAVE_QUP_CORE_0 4 +#define SLAVE_QUP_CORE_1 5 +#define SLAVE_QUP_CORE_2 6 +#define SLAVE_QUP_CORE_3 7 + +/* config_noc */ +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AHB2PHY_0 2 +#define SLAVE_AHB2PHY_1 3 +#define SLAVE_AHB2PHY_2 4 +#define SLAVE_AHB2PHY_3 5 +#define SLAVE_ANOC_THROTTLE_CFG 6 +#define SLAVE_AOSS 7 +#define SLAVE_APPSS 8 +#define SLAVE_BOOT_ROM 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 12 +#define SLAVE_CLK_CTL 13 +#define SLAVE_CDSP_CFG 14 +#define SLAVE_CDSP1_CFG 15 +#define SLAVE_RBCPR_CX_CFG 16 +#define SLAVE_RBCPR_MMCX_CFG 17 +#define SLAVE_RBCPR_MX_CFG 18 +#define SLAVE_CPR_NSPCX 19 +#define SLAVE_CRYPTO_0_CFG 20 +#define SLAVE_CX_RDPM 21 +#define SLAVE_DISPLAY_CFG 22 +#define SLAVE_DISPLAY_RT_THROTTLE_CFG 23 +#define SLAVE_DISPLAY1_CFG 24 +#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 25 +#define SLAVE_EMAC_CFG 26 +#define SLAVE_EMAC1_CFG 27 +#define SLAVE_GP_DSP0_CFG 28 +#define SLAVE_GP_DSP1_CFG 29 +#define SLAVE_GPDSP0_THROTTLE_CFG 30 +#define SLAVE_GPDSP1_THROTTLE_CFG 31 +#define SLAVE_GPU_TCU_THROTTLE_CFG 32 +#define SLAVE_GFX3D_CFG 33 +#define SLAVE_HWKM 34 +#define SLAVE_IMEM_CFG 35 +#define SLAVE_IPA_CFG 36 +#define SLAVE_IPC_ROUTER_CFG 37 +#define SLAVE_LPASS 38 +#define SLAVE_LPASS_THROTTLE_CFG 39 +#define SLAVE_MX_RDPM 40 +#define SLAVE_MXC_RDPM 41 +#define SLAVE_PCIE_0_CFG 42 +#define SLAVE_PCIE_1_CFG 43 +#define SLAVE_PCIE_RSC_CFG 44 +#define SLAVE_PCIE_TCU_THROTTLE_CFG 45 +#define SLAVE_PCIE_THROTTLE_CFG 46 +#define SLAVE_PDM 47 +#define SLAVE_PIMEM_CFG 48 +#define SLAVE_PKA_WRAPPER_CFG 49 +#define SLAVE_QDSS_CFG 50 +#define SLAVE_QM_CFG 51 +#define SLAVE_QM_MPU_CFG 52 +#define SLAVE_QUP_0 53 +#define SLAVE_QUP_1 54 +#define SLAVE_QUP_2 55 +#define SLAVE_QUP_3 56 +#define SLAVE_SAIL_THROTTLE_CFG 57 +#define SLAVE_SDC1 58 +#define SLAVE_SECURITY 59 +#define SLAVE_SNOC_THROTTLE_CFG 60 +#define SLAVE_TCSR 61 +#define SLAVE_TLMM 62 +#define SLAVE_TSC_CFG 63 +#define SLAVE_UFS_CARD_CFG 64 +#define SLAVE_UFS_MEM_CFG 65 +#define SLAVE_USB2 66 +#define SLAVE_USB3_0 67 +#define SLAVE_USB3_1 68 +#define SLAVE_VENUS_CFG 69 +#define SLAVE_VENUS_CVP_THROTTLE_CFG 70 +#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 71 +#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 72 +#define SLAVE_DDRSS_CFG 73 +#define SLAVE_GPDSP_NOC_CFG 74 +#define SLAVE_CNOC_MNOC_HF_CFG 75 +#define SLAVE_CNOC_MNOC_SF_CFG 76 +#define SLAVE_PCIE_ANOC_CFG 77 +#define SLAVE_SNOC_CFG 78 +#define SLAVE_BOOT_IMEM 79 +#define SLAVE_IMEM 80 +#define SLAVE_PIMEM 81 +#define SLAVE_PCIE_0 82 +#define SLAVE_PCIE_1 83 +#define SLAVE_QDSS_STM 84 +#define SLAVE_TCU 85 + +/* dc_noc */ +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +/* gem_noc */ +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_COMPUTE_NOC_1 5 +#define MASTER_GEM_NOC_CFG 6 +#define MASTER_GPDSP_SAIL 7 +#define MASTER_GFX3D 8 +#define MASTER_MNOC_HF_MEM_NOC 9 +#define MASTER_MNOC_SF_MEM_NOC 10 +#define MASTER_ANOC_PCIE_GEM_NOC 11 +#define MASTER_SNOC_GC_MEM_NOC 12 +#define MASTER_SNOC_SF_MEM_NOC 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_GEM_NOC_PCIE_CNOC 16 +#define SLAVE_SERVICE_GEM_NOC_1 17 +#define SLAVE_SERVICE_GEM_NOC_2 18 +#define SLAVE_SERVICE_GEM_NOC 19 +#define SLAVE_SERVICE_GEM_NOC2 20 + +/* gpdsp_anoc */ +#define MASTER_DSP0 0 +#define MASTER_DSP1 1 +#define SLAVE_GP_DSP_SAIL_NOC 2 + +/* lpass_ag_noc */ +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define MASTER_LPASS_PROC 1 +#define SLAVE_LPASS_CORE_CFG 2 +#define SLAVE_LPASS_LPI_CFG 3 +#define SLAVE_LPASS_MPU_CFG 4 +#define SLAVE_LPASS_TOP_CFG 5 +#define SLAVE_LPASS_SNOC 6 +#define SLAVE_SERVICES_LPASS_AML_NOC 7 +#define SLAVE_SERVICE_LPASS_AG_NOC 8 + +/* mc_virt */ +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +/*mmss_noc */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP0 3 +#define MASTER_MDP1 4 +#define MASTER_MDP_CORE1_0 5 +#define MASTER_MDP_CORE1_1 6 +#define MASTER_CNOC_MNOC_HF_CFG 7 +#define MASTER_CNOC_MNOC_SF_CFG 8 +#define MASTER_VIDEO_P0 9 +#define MASTER_VIDEO_P1 10 +#define MASTER_VIDEO_PROC 11 +#define MASTER_VIDEO_V_PROC 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 +#define SLAVE_SERVICE_MNOC_HF 15 +#define SLAVE_SERVICE_MNOC_SF 16 + +/* nspa_noc */ +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_HCP_A 2 +#define SLAVE_CDSP_MEM_NOC 3 +#define SLAVE_SERVICE_NSP_NOC 4 + +/* nspb_noc */ +#define MASTER_CDSPB_NOC_CFG 0 +#define MASTER_CDSP_PROC_B 1 +#define SLAVE_CDSPB_MEM_NOC 2 +#define SLAVE_HCP_B 3 +#define SLAVE_SERVICE_NSPB_NOC 4 + +/* pcie_anoc */ +#define MASTER_PCIE_0 0 +#define MASTER_PCIE_1 1 +#define SLAVE_ANOC_PCIE_GEM_NOC 2 + +/* system_noc */ +#define MASTER_GIC_AHB 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_LPASS_ANOC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_SERVICE_SNOC 9 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H */ -- cgit v1.2.3 From e3e289fbc0b520cf469469e8cdba84a50424eb65 Mon Sep 17 00:00:00 2001 From: Kai Ye Date: Sat, 19 Nov 2022 07:48:15 +0000 Subject: uacce: supports device isolation feature UACCE adds the hardware error isolation feature. To improve service reliability, some uacce devices that frequently encounter hardware errors are isolated. Therefore, this feature is added. Users can configure the hardware error threshold by 'isolate_strategy' sysfs node. The user space can get the device isolated state by 'isolate' sysfs node. If the number of device errors exceeds the configured error threshold, the device will be isolated. It means the uacce device is unavailable. Signed-off-by: Kai Ye Link: https://lore.kernel.org/r/20221119074817.12063-2-yekai13@huawei.com Signed-off-by: Greg Kroah-Hartman --- include/linux/uacce.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/linux/uacce.h b/include/linux/uacce.h index 9ce88c28b0a8..0a81c3dfd26c 100644 --- a/include/linux/uacce.h +++ b/include/linux/uacce.h @@ -8,6 +8,7 @@ #define UACCE_NAME "uacce" #define UACCE_MAX_REGION 2 #define UACCE_MAX_NAME_SIZE 64 +#define UACCE_MAX_ERR_THRESHOLD 65535 struct uacce_queue; struct uacce_device; @@ -30,6 +31,9 @@ struct uacce_qfile_region { * @is_q_updated: check whether the task is finished * @mmap: mmap addresses of queue to user space * @ioctl: ioctl for user space users of the queue + * @get_isolate_state: get the device state after set the isolate strategy + * @isolate_err_threshold_write: stored the isolate error threshold to the device + * @isolate_err_threshold_read: read the isolate error threshold value from the device */ struct uacce_ops { int (*get_available_instances)(struct uacce_device *uacce); @@ -43,6 +47,9 @@ struct uacce_ops { struct uacce_qfile_region *qfr); long (*ioctl)(struct uacce_queue *q, unsigned int cmd, unsigned long arg); + enum uacce_dev_state (*get_isolate_state)(struct uacce_device *uacce); + int (*isolate_err_threshold_write)(struct uacce_device *uacce, u32 num); + u32 (*isolate_err_threshold_read)(struct uacce_device *uacce); }; /** @@ -57,6 +64,11 @@ struct uacce_interface { const struct uacce_ops *ops; }; +enum uacce_dev_state { + UACCE_DEV_NORMAL, + UACCE_DEV_ISOLATE, +}; + enum uacce_q_state { UACCE_Q_ZOMBIE = 0, UACCE_Q_INIT, -- cgit v1.2.3 From cd0ac51c5760d4eed4981be5de9cad0255976512 Mon Sep 17 00:00:00 2001 From: Kai Ye Date: Sat, 19 Nov 2022 07:48:17 +0000 Subject: crypto: hisilicon/qm - define the device isolation strategy Define the device isolation strategy by the device driver. The user configures a hardware error threshold value by uacce interface. If the number of hardware errors exceeds the value of setting error threshold in one hour. The device will not be available in user space. The VF device use the PF device isolation strategy. All the hardware errors are processed by PF driver. Signed-off-by: Kai Ye Acked-by: Herbert Xu Link: https://lore.kernel.org/r/20221119074817.12063-4-yekai13@huawei.com Signed-off-by: Greg Kroah-Hartman --- include/linux/hisi_acc_qm.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index be3aedaa96dc..d08bff0f87f9 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -272,6 +272,20 @@ struct hisi_qm_poll_data { u16 *qp_finish_id; }; +/** + * struct qm_err_isolate + * @isolate_lock: protects device error log + * @err_threshold: user config error threshold which triggers isolation + * @is_isolate: device isolation state + * @uacce_hw_errs: index into qm device error list + */ +struct qm_err_isolate { + struct mutex isolate_lock; + u32 err_threshold; + bool is_isolate; + struct list_head qm_hw_errs; +}; + struct hisi_qm { enum qm_hw_ver ver; enum qm_fun_type fun_type; @@ -341,6 +355,7 @@ struct hisi_qm { struct qm_shaper_factor *factor; u32 mb_qos; u32 type_rate; + struct qm_err_isolate isolate_data; }; struct hisi_qp_status { -- cgit v1.2.3 From b3c71626a9333b0b29f9921a39cef30b5961766f Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Tue, 17 Jan 2023 06:57:01 -0800 Subject: Coresight: Add coresight TPDM source driver Add driver to support Coresight device TPDM (Trace, Profiling and Diagnostics Monitor). TPDM is a monitor to collect data from different datasets. This change is to add probe/enable/disable functions for tpdm source. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230120095301.30792-1-quic_jinlmao@quicinc.com --- include/linux/coresight.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/coresight.h b/include/linux/coresight.h index e241eb88dfb9..f19a47b9bb5a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, }; enum coresight_dev_subtype_helper { -- cgit v1.2.3 From 6640727fc55b7f0b561e927bc9c5b9d4c459fd8e Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sun, 8 Jan 2023 21:56:52 +0000 Subject: parport_pc: Let chipset drivers mask ECR bits on writes Provide an `ecr_writable' parameter to `__parport_pc_probe_port' so that callers can specify a mask of bits to modify on ECR writes. To avoid the need for separate bit set and bit clear masks always set bit 0 whenever a non-zero mask has been set, as all the currently known cases where a mask is required, that is Oxford Semiconductor devices, do require this bit to be set. If further cases are discovered where the bit is required to be clear, we can update code accordingly, but chances are very low as the bit is supposed to be read-only[1]. Skip ECR probing, which can be problematic as the Oxford Semiconductor OX12PCI840 part has been reported to lock up on setting bit 2, whenever a non-zero mask has been requested by a port subdriver, assuming that the ECR must be there if the subdriver has requested a specific way to access it. References: [1] "Extended Capabilities Port Protocol and ISA Interface Standard", Microsoft Corporation, Revision: 1.14, July 14, 1993, Table 14 "Extended Control Register" Signed-off-by: Maciej W. Rozycki Signed-off-by: Sudip Mukherjee Link: https://lore.kernel.org/r/20230108215656.6433-3-sudipm.mukherjee@gmail.com Signed-off-by: Greg Kroah-Hartman --- include/linux/parport_pc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/parport_pc.h b/include/linux/parport_pc.h index 3d6fc576d6a1..f1ec5c10c3b3 100644 --- a/include/linux/parport_pc.h +++ b/include/linux/parport_pc.h @@ -26,6 +26,9 @@ struct parport_pc_private { /* Whether or not there's an ECR. */ int ecr; + /* Bitmask of writable ECR bits. */ + unsigned char ecr_writable; + /* Number of PWords that FIFO will hold. */ int fifo_depth; -- cgit v1.2.3 From 1ddc7618294084fff8d673217a9479550990ee84 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 23 Jan 2023 12:59:45 +0530 Subject: bus: mhi: ep: Change state_lock to mutex state_lock, the spinlock type is meant to protect race against concurrent MHI state transitions. In mhi_ep_set_m0_state(), while the state_lock is being held, the channels are resumed in mhi_ep_resume_channels() if the previous state was M3. This causes sleeping in atomic bug, since mhi_ep_resume_channels() use mutex internally. Since the state_lock is supposed to be held throughout the state change, it is not ideal to drop the lock before calling mhi_ep_resume_channels(). So to fix this issue, let's change the type of state_lock to mutex. This would also allow holding the lock throughout all state transitions thereby avoiding any potential race. Cc: # 5.19 Fixes: e4b7b5f0f30a ("bus: mhi: ep: Add support for suspending and resuming channels") Reported-by: Dan Carpenter Reviewed-by: Jeffrey Hugo Signed-off-by: Manivannan Sadhasivam --- include/linux/mhi_ep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 478aece17046..f198a8ac7ee7 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -70,8 +70,8 @@ struct mhi_ep_db_info { * @cmd_ctx_cache_phys: Physical address of the host command context cache * @chdb: Array of channel doorbell interrupt info * @event_lock: Lock for protecting event rings - * @list_lock: Lock for protecting state transition and channel doorbell lists * @state_lock: Lock for protecting state transitions + * @list_lock: Lock for protecting state transition and channel doorbell lists * @st_transition_list: List of state transitions * @ch_db_list: List of queued channel doorbells * @wq: Dedicated workqueue for handling rings and state changes @@ -117,8 +117,8 @@ struct mhi_ep_cntrl { struct mhi_ep_db_info chdb[4]; struct mutex event_lock; + struct mutex state_lock; spinlock_t list_lock; - spinlock_t state_lock; struct list_head st_transition_list; struct list_head ch_db_list; -- cgit v1.2.3 From 5e6a51787fef20b849682d8c49ec9c2beed5c373 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 24 Jan 2023 15:38:38 +0200 Subject: uuid: Decouple guid_t and uuid_le types and respective macros The guid_t type and respective macros are being used internally only. The uuid_le has its user outside the kernel. Decouple these types and macros, and make guid_t completely internal type to the kernel. Signed-off-by: Andy Shevchenko Reviewed-by: Christoph Hellwig Link: https://lore.kernel.org/r/20230124133838.22645-1-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- include/linux/uuid.h | 20 ++++++++++++++++---- include/uapi/linux/uuid.h | 12 ++++-------- 2 files changed, 20 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/linux/uuid.h b/include/linux/uuid.h index 8cdc0d3567cd..5be158a49e11 100644 --- a/include/linux/uuid.h +++ b/include/linux/uuid.h @@ -8,15 +8,25 @@ #ifndef _LINUX_UUID_H_ #define _LINUX_UUID_H_ -#include #include #define UUID_SIZE 16 +typedef struct { + __u8 b[UUID_SIZE]; +} guid_t; + typedef struct { __u8 b[UUID_SIZE]; } uuid_t; +#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ +((guid_t) \ +{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) + #define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ ((uuid_t) \ {{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ @@ -97,10 +107,12 @@ extern const u8 uuid_index[16]; int guid_parse(const char *uuid, guid_t *u); int uuid_parse(const char *uuid, uuid_t *u); -/* backwards compatibility, don't use in new code */ -static inline int uuid_le_cmp(const guid_t u1, const guid_t u2) +/* MEI UUID type, don't use anywhere else */ +#include + +static inline int uuid_le_cmp(const uuid_le u1, const uuid_le u2) { - return memcmp(&u1, &u2, sizeof(guid_t)); + return memcmp(&u1, &u2, sizeof(uuid_le)); } #endif diff --git a/include/uapi/linux/uuid.h b/include/uapi/linux/uuid.h index c0f4bd9b040e..96ac684a4b2f 100644 --- a/include/uapi/linux/uuid.h +++ b/include/uapi/linux/uuid.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* DO NOT USE in new code! This is solely for MEI due to legacy reasons */ /* - * UUID/GUID definition + * MEI UUID definition * * Copyright (C) 2010, Intel Corp. * Huang Ying @@ -14,19 +14,15 @@ typedef struct { __u8 b[16]; -} guid_t; +} uuid_le; -#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ -((guid_t) \ +#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ +((uuid_le) \ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ (b) & 0xff, ((b) >> 8) & 0xff, \ (c) & 0xff, ((c) >> 8) & 0xff, \ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) -/* backwards compatibility, don't use in new code */ -typedef guid_t uuid_le; -#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ - GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) #define NULL_UUID_LE \ UUID_LE(0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00) -- cgit v1.2.3 From f5b3c341a46ec55d93332ee5c254a278af902ffe Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 2 Feb 2023 16:54:12 +0200 Subject: mei: Move uuid_le_cmp() to its only user There is only a single user of uuid_le_cmp() API, let's make it private to that user. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230202145412.87569-1-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- include/linux/uuid.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/linux/uuid.h b/include/linux/uuid.h index 5be158a49e11..6b1a3efa1e0b 100644 --- a/include/linux/uuid.h +++ b/include/linux/uuid.h @@ -110,9 +110,4 @@ int uuid_parse(const char *uuid, uuid_t *u); /* MEI UUID type, don't use anywhere else */ #include -static inline int uuid_le_cmp(const uuid_le u1, const uuid_le u2) -{ - return memcmp(&u1, &u2, sizeof(uuid_le)); -} - #endif -- cgit v1.2.3 From 7390609b0121a1b982c5ecdfcd72dc328e5784ee Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 6 Feb 2023 13:43:42 +0000 Subject: net: add helper eth_addr_add() Add a helper to add an offset to a ethernet address. This comes in handy if you have a base ethernet address for multiple interfaces. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn Acked-by: Jakub Kicinski Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-9-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- include/linux/etherdevice.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index a541f0c4f146..224645f17c33 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -507,6 +507,20 @@ static inline void eth_addr_inc(u8 *addr) u64_to_ether_addr(u, addr); } +/** + * eth_addr_add() - Add (or subtract) an offset to/from the given MAC address. + * + * @offset: Offset to add. + * @addr: Pointer to a six-byte array containing Ethernet address to increment. + */ +static inline void eth_addr_add(u8 *addr, long offset) +{ + u64 u = ether_addr_to_u64(addr); + + u += offset; + u64_to_ether_addr(u, addr); +} + /** * is_etherdev_addr - Tell if given Ethernet address belongs to the device. * @dev: Pointer to a device structure -- cgit v1.2.3 From c5d264d4b527c96ae8903376a4b195df47b05203 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 6 Feb 2023 13:43:43 +0000 Subject: of: base: add of_parse_phandle_with_optional_args() Add a new variant of the of_parse_phandle_with_args() which treats the cells name as optional. If it's missing, it is assumed that the phandle has no arguments. Up until now, a nvmem node didn't have any arguments, so all the device trees haven't any '#*-cells' property. But there is a need for an additional argument for the phandle, for which we need a '#*-cells' property. Therefore, we need to support nvmem nodes with and without this property. Signed-off-by: Michael Walle Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-10-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- include/linux/of.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'include') diff --git a/include/linux/of.h b/include/linux/of.h index 8b9f94386dc3..98c252d2d851 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1008,6 +1008,31 @@ static inline int of_parse_phandle_with_fixed_args(const struct device_node *np, index, out_args); } +/** + * of_parse_phandle_with_optional_args() - Find a node pointed by phandle in a list + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * + * Same as of_parse_phandle_with_args() except that if the cells_name property + * is not found, cell_count of 0 is assumed. + * + * This is used to useful, if you have a phandle which didn't have arguments + * before and thus doesn't have a '#*-cells' property but is now migrated to + * having arguments while retaining backwards compatibility. + */ +static inline int of_parse_phandle_with_optional_args(const struct device_node *np, + const char *list_name, + const char *cells_name, + int index, + struct of_phandle_args *out_args) +{ + return __of_parse_phandle_with_args(np, list_name, cells_name, + 0, index, out_args); +} + /** * of_property_count_u8_elems - Count the number of u8 elements in a property * -- cgit v1.2.3 From 5d8e6e6c10a3d37486d263b16ddc15991a7e4a88 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 6 Feb 2023 13:43:46 +0000 Subject: nvmem: core: add an index parameter to the cell Sometimes a cell can represend multiple values. For example, a base ethernet address stored in the NVMEM can be expanded into multiple discreet ones by adding an offset. For this use case, introduce an index parameter which is then used to distiguish between values. This parameter will then be passed to the post process hook which can then use it to create different values during reading. At the moment, there is only support for the device tree path. You can add the index to the phandle, e.g. &net { nvmem-cells = <&base_mac_address 2>; nvmem-cell-names = "mac-address"; }; &nvmem_provider { base_mac_address: base-mac-address@0 { #nvmem-cell-cells = <1>; reg = <0 6>; }; }; Signed-off-by: Michael Walle Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-13-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- include/linux/nvmem-provider.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index bb15c9234e21..55181d837969 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -20,8 +20,8 @@ typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset, typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, void *val, size_t bytes); /* used for vendor specific post processing of cell data */ -typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, unsigned int offset, - void *buf, size_t bytes); +typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, int index, + unsigned int offset, void *buf, size_t bytes); enum nvmem_type { NVMEM_TYPE_UNKNOWN = 0, -- cgit v1.2.3 From fbd03d27776c6121a483921601418e3c8f0ff37e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 6 Feb 2023 13:43:47 +0000 Subject: nvmem: core: move struct nvmem_cell_info to nvmem-provider.h struct nvmem_cell_info is used to describe a cell. Thus this should really be in the nvmem-provider's header. There are two (unused) nvmem access methods which use the nvmem_cell_info to describe the cell to be accesses. One can argue, that they will create a cell before accessing, thus they are both a provider and a consumer. struct nvmem_cell_info will get used more and more by nvmem-providers, don't force them to also include the consumer header, although they are not. Signed-off-by: Michael Walle Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-14-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- include/linux/nvmem-consumer.h | 10 +--------- include/linux/nvmem-provider.h | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h index 980f9c9ac0bc..1f62f7ba71ca 100644 --- a/include/linux/nvmem-consumer.h +++ b/include/linux/nvmem-consumer.h @@ -18,15 +18,7 @@ struct device_node; /* consumer cookie */ struct nvmem_cell; struct nvmem_device; - -struct nvmem_cell_info { - const char *name; - unsigned int offset; - unsigned int bytes; - unsigned int bit_offset; - unsigned int nbits; - struct device_node *np; -}; +struct nvmem_cell_info; /** * struct nvmem_cell_lookup - cell lookup entry diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index 55181d837969..a953a3a59535 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -14,7 +14,6 @@ #include struct nvmem_device; -struct nvmem_cell_info; typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset, void *val, size_t bytes); typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, @@ -47,6 +46,24 @@ struct nvmem_keepout { unsigned char value; }; +/** + * struct nvmem_cell_info - NVMEM cell description + * @name: Name. + * @offset: Offset within the NVMEM device. + * @bytes: Length of the cell. + * @bit_offset: Bit offset if cell is smaller than a byte. + * @nbits: Number of bits. + * @np: Optional device_node pointer. + */ +struct nvmem_cell_info { + const char *name; + unsigned int offset; + unsigned int bytes; + unsigned int bit_offset; + unsigned int nbits; + struct device_node *np; +}; + /** * struct nvmem_config - NVMEM device configuration * -- cgit v1.2.3 From 2ded6830d376d5e7bf43d59f7f7fdf1a59abc676 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 6 Feb 2023 13:43:49 +0000 Subject: nvmem: core: add nvmem_add_one_cell() Add a new function to add exactly one cell. This will be used by the nvmem layout drivers to add custom cells. In contrast to the nvmem_add_cells(), this has the advantage that we don't have to assemble a list of cells on runtime. Signed-off-by: Michael Walle Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-16-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- include/linux/nvmem-provider.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index a953a3a59535..0262b86194eb 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -153,6 +153,9 @@ struct nvmem_device *devm_nvmem_register(struct device *dev, void nvmem_add_cell_table(struct nvmem_cell_table *table); void nvmem_del_cell_table(struct nvmem_cell_table *table); +int nvmem_add_one_cell(struct nvmem_device *nvmem, + const struct nvmem_cell_info *info); + #else static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c) @@ -170,6 +173,11 @@ devm_nvmem_register(struct device *dev, const struct nvmem_config *c) static inline void nvmem_add_cell_table(struct nvmem_cell_table *table) {} static inline void nvmem_del_cell_table(struct nvmem_cell_table *table) {} +static inline int nvmem_add_one_cell(struct nvmem_device *nvmem, + const struct nvmem_cell_info *info) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_NVMEM */ #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ -- cgit v1.2.3