From dc652a33cf08ecd7c9935bf9168a1a27c9a246f0 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Fri, 12 Dec 2025 08:41:42 +0900 Subject: clk: remove round_rate() clk ops The round_rate() clk ops is deprecated, and all in tree drivers have been converted, so let's go ahead and remove any references to the round_rate() clk ops. Signed-off-by: Brian Masney --- include/linux/clk-provider.h | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 630705a47129..1cda2c78dffa 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -136,10 +136,6 @@ struct clk_duty { * 0. Returns the calculated rate. Optional, but recommended - if * this op is not set then clock rate will be initialized to 0. * - * @round_rate: Given a target rate as input, returns the closest rate actually - * supported by the clock. The parent rate is an input/output - * parameter. - * * @determine_rate: Given a target rate as input, returns the closest rate * actually supported by the clock, and optionally the parent clock * that should be used to provide the clock rate. @@ -163,13 +159,13 @@ struct clk_duty { * * @set_rate: Change the rate of this clock. The requested rate is specified * by the second argument, which should typically be the return - * of .round_rate call. The third argument gives the parent rate - * which is likely helpful for most .set_rate implementation. + * of .determine_rate call. The third argument gives the parent + * rate which is likely helpful for most .set_rate implementation. * Returns 0 on success, -EERROR otherwise. * * @set_rate_and_parent: Change the rate and the parent of this clock. The * requested rate is specified by the second argument, which - * should typically be the return of .round_rate call. The + * should typically be the return of clk_round_rate() call. The * third argument gives the parent rate which is likely helpful * for most .set_rate_and_parent implementation. The fourth * argument gives the parent index. This callback is optional (and @@ -244,8 +240,6 @@ struct clk_ops { void (*restore_context)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); - long (*round_rate)(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate); int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req); int (*set_parent)(struct clk_hw *hw, u8 index); @@ -679,7 +673,7 @@ struct clk_div_table { * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements - * .recalc_rate, .set_rate and .round_rate + * .recalc_rate, .set_rate and .determine_rate * * @flags: * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the @@ -1126,7 +1120,7 @@ void of_fixed_factor_clk_setup(struct device_node *node); * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. - * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy + * Implements .recalc_rate, .set_rate, .determine_rate and .recalc_accuracy * * Flags: * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the @@ -1254,7 +1248,7 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); * @lock: register lock * * Clock with an adjustable multiplier affecting its output frequency. - * Implements .recalc_rate, .set_rate and .round_rate + * Implements .recalc_rate, .set_rate and .determine_rate * * @flags: * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read -- cgit v1.2.3 From 4b5231d608d00749a2346a3dd11bd6d05c0662e3 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 8 Jan 2026 16:16:44 -0500 Subject: clk: divider: remove divider_ro_round_rate_parent() There are no remaining users of divider_ro_round_rate_parent(), so let's go ahead and remove it. Signed-off-by: Brian Masney --- include/linux/clk-provider.h | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'include') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1cda2c78dffa..0d31077749fb 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -737,10 +737,6 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags); -long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, - unsigned long rate, unsigned long *prate, - const struct clk_div_table *table, u8 width, - unsigned long flags, unsigned int val); int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, const struct clk_div_table *table, u8 width, unsigned long flags); @@ -1440,17 +1436,6 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, rate, prate, table, width, flags); } -static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate, - const struct clk_div_table *table, - u8 width, unsigned long flags, - unsigned int val) -{ - return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), - rate, prate, table, width, flags, - val); -} - /* * FIXME clock api without lock protection */ -- cgit v1.2.3 From d4851759742c1322f498021dab882d322fc34a1d Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 8 Jan 2026 16:16:45 -0500 Subject: clk: divider: remove divider_round_rate() and divider_round_rate_parent() There are no remaining users of divider_round_rate() and divider_round_rate_parent(), so let's go ahead and remove them. Signed-off-by: Brian Masney --- include/linux/clk-provider.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'include') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 0d31077749fb..4d21602d7dbd 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -733,10 +733,6 @@ extern const struct clk_ops clk_divider_ro_ops; unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val, const struct clk_div_table *table, unsigned long flags, unsigned long width); -long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, - unsigned long rate, unsigned long *prate, - const struct clk_div_table *table, - u8 width, unsigned long flags); int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, const struct clk_div_table *table, u8 width, unsigned long flags); @@ -1427,15 +1423,6 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) dst->core = src->core; } -static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate, - const struct clk_div_table *table, - u8 width, unsigned long flags) -{ - return divider_round_rate_parent(hw, clk_hw_get_parent(hw), - rate, prate, table, width, flags); -} - /* * FIXME clock api without lock protection */ -- cgit v1.2.3 From 4aff230cf28b5f68a62fcd79de341c58245ea8e2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 27 Jan 2026 12:45:49 +0530 Subject: dt-bindings: clock: qcom: document the Glymur GPU Clock Controller Glymur SoC has Qualcomm GX(graphics) clock controller and also the Graphics clock controller. The GX graphics clock controller helps in the recovery of the Graphics subsystem. Add bindings documentation for the Glymur Graphics Clock and Graphics power domain Controller for Glymur SoC. Signed-off-by: Taniya Das Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,glymur-gpucc.h | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,glymur-gpucc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,glymur-gpucc.h b/include/dt-bindings/clock/qcom,glymur-gpucc.h new file mode 100644 index 000000000000..35f5abb848fd --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-gpucc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GPU_SMMU_VOTE_CLK 12 +#define GPU_CC_GX_ACCU_SHIFT_CLK 13 +#define GPU_CC_GX_ACD_AHB_FF_CLK 14 +#define GPU_CC_GX_AHB_FF_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_RCG_AHB_FF_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_CB_BCR 0 +#define GPU_CC_CX_BCR 1 +#define GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_FF_BCR 3 +#define GPU_CC_GMU_BCR 4 +#define GPU_CC_GX_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif -- cgit v1.2.3 From 7c3260327fc874b7c89d7bb230cd569d2e78aff7 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 2 Feb 2026 16:26:50 +0530 Subject: dt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur The global clock controller video axi reset clocks are required by the video SW driver to assert and deassert the clock resets. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-1-8f7d8b4d8edd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,glymur-gcc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h index 10c12b8c51c3..6907653c7992 100644 --- a/include/dt-bindings/clock/qcom,glymur-gcc.h +++ b/include/dt-bindings/clock/qcom,glymur-gcc.h @@ -574,5 +574,6 @@ #define GCC_VIDEO_AXI0_CLK_ARES 89 #define GCC_VIDEO_AXI1_CLK_ARES 90 #define GCC_VIDEO_BCR 91 +#define GCC_VIDEO_AXI0C_CLK_ARES 92 #endif -- cgit v1.2.3 From ed9ca829614735ab0de0c97af9239bd20a618de1 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 2 Feb 2026 16:26:51 +0530 Subject: dt-bindings: clock: qcom: Add video clock controller on Glymur SoC Add compatible string for Glymur video clock controller and the bindings for Glymur Qualcomm SoC. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-2-8f7d8b4d8edd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,glymur-videocc.h | 45 +++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,glymur-videocc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,glymur-videocc.h b/include/dt-bindings/clock/qcom,glymur-videocc.h new file mode 100644 index 000000000000..98c0debef8fa --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-videocc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_FREERUN_CLK 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_FREERUN_CLK 9 +#define VIDEO_CC_MVS0C_SHIFT_CLK 10 +#define VIDEO_CC_MVS1_CLK 11 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 12 +#define VIDEO_CC_MVS1_FREERUN_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_PLL0 15 +#define VIDEO_CC_SLEEP_CLK 16 +#define VIDEO_CC_SLEEP_CLK_SRC 17 +#define VIDEO_CC_XO_CLK 18 +#define VIDEO_CC_XO_CLK_SRC 19 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 +#define VIDEO_CC_MVS1_GDSC 2 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_BCR 2 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 3 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4 +#define VIDEO_CC_MVS1_FREERUN_CLK_ARES 5 +#define VIDEO_CC_XO_CLK_ARES 6 +#define VIDEO_CC_MVS1_BCR 7 +#endif -- cgit v1.2.3 From 6974ae5aa23b7f37182da6b66d7f58313a55a88e Mon Sep 17 00:00:00 2001 From: GyoungBo Min Date: Wed, 29 Oct 2025 18:37:28 +0530 Subject: dt-bindings: clock: Add ARTPEC-9 clock controller Add dt-schema for Axis ARTPEC-9 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS0 - CMU_FSYS1 - CMU_IMEM - CMU_PERI Signed-off-by: GyoungBo Min Reviewed-by: Kyunghwan Kim Signed-off-by: Ravi Patel Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251029130731.51305-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/axis,artpec9-clk.h | 195 +++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 include/dt-bindings/clock/axis,artpec9-clk.h (limited to 'include') diff --git a/include/dt-bindings/clock/axis,artpec9-clk.h b/include/dt-bindings/clock/axis,artpec9-clk.h new file mode 100644 index 000000000000..c6787be8d686 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec9-clk.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + * + * Device Tree binding constants for ARTPEC-9 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H +#define _DT_BINDINGS_CLOCK_ARTPEC9_H + +/* CMU_CMU */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_DOUT_SHARED0_DIV2 2 +#define CLK_DOUT_SHARED0_DIV3 3 +#define CLK_DOUT_SHARED0_DIV4 4 +#define CLK_FOUT_SHARED1_PLL 5 +#define CLK_DOUT_SHARED1_DIV2 6 +#define CLK_DOUT_SHARED1_DIV3 7 +#define CLK_DOUT_SHARED1_DIV4 8 +#define CLK_FOUT_AUDIO_PLL 9 +#define CLK_DOUT_CMU_ADD 10 +#define CLK_DOUT_CMU_BUS 11 +#define CLK_DOUT_CMU_CDC_CORE 12 +#define CLK_DOUT_CMU_CORE_MAIN 13 +#define CLK_DOUT_CMU_CPUCL_SWITCH 14 +#define CLK_DOUT_CMU_DLP_CORE 15 +#define CLK_DOUT_CMU_FSYS0_BUS 16 +#define CLK_DOUT_CMU_FSYS0_IP 17 +#define CLK_DOUT_CMU_FSYS1_BUS 18 +#define CLK_DOUT_CMU_FSYS1_SCAN0 19 +#define CLK_DOUT_CMU_FSYS1_SCAN1 20 +#define CLK_DOUT_CMU_GPU_3D 21 +#define CLK_DOUT_CMU_GPU_2D 22 +#define CLK_DOUT_CMU_IMEM_ACLK 23 +#define CLK_DOUT_CMU_IMEM_CA5 24 +#define CLK_DOUT_CMU_IMEM_JPEG 25 +#define CLK_DOUT_CMU_IMEM_SSS 26 +#define CLK_DOUT_CMU_IPA_CORE 27 +#define CLK_DOUT_CMU_LCPU 28 +#define CLK_DOUT_CMU_MIF_SWITCH 29 +#define CLK_DOUT_CMU_MIF_BUSP 30 +#define CLK_DOUT_CMU_PERI_DISP 31 +#define CLK_DOUT_CMU_PERI_IP 32 +#define CLK_DOUT_CMU_RSP_CORE 33 +#define CLK_DOUT_CMU_TRFM 34 +#define CLK_DOUT_CMU_VIO_CORE_L 35 +#define CLK_DOUT_CMU_VIO_CORE 36 +#define CLK_DOUT_CMU_VIP0 37 +#define CLK_DOUT_CMU_VIP1 38 +#define CLK_DOUT_CMU_VPP_CORE 39 +#define CLK_DOUT_CMU_VIO_AUDIO 40 + +/* CMU_BUS */ +#define CLK_MOUT_BUS_ACLK_USER 1 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_ACLK_USER 1 + +/* CMU_CPUCL */ +#define CLK_FOUT_CPUCL_PLL0 1 +#define CLK_MOUT_CPUCL_PLL0 2 +#define CLK_FOUT_CPUCL_PLL1 3 +#define CLK_MOUT_CPUCL_PLL_SCU 4 +#define CLK_MOUT_CPUCL_SWITCH_SCU_USER 5 +#define CLK_MOUT_CPUCL_SWITCH_USER 6 +#define CLK_DOUT_CPUCL_CPU 7 +#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK 8 +#define CLK_DOUT_CPUCL_CLUSTER_GICCLK 9 +#define CLK_DOUT_CPUCL_CLUSTER_PCLK 10 +#define CLK_DOUT_CPUCL_CMUREF 11 +#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 12 +#define CLK_DOUT_CPUCL_CLUSTER_SCU 13 +#define CLK_DOUT_CPUCL_DBG 14 +#define CLK_GOUT_CPUCL_SHORTSTOP 15 +#define CLK_GOUT_CPUCL_CLUSTER_CPU 16 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 17 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 18 + +/* CMU_FSYS0 */ +#define CLK_MOUT_FSYS0_BUS_USER 1 +#define CLK_MOUT_FSYS0_IP_USER 2 +#define CLK_MOUT_FSYS0_MAIN_USER 3 +#define CLK_DOUT_FSYS0_125 4 +#define CLK_DOUT_FSYS0_ADC 5 +#define CLK_DOUT_FSYS0_BUS_300 6 +#define CLK_DOUT_FSYS0_EQOS0 7 +#define CLK_DOUT_FSYS0_EQOS1 8 +#define CLK_DOUT_FSYS0_MMC_CARD0 9 +#define CLK_DOUT_FSYS0_MMC_CARD1 10 +#define CLK_DOUT_FSYS0_MMC_CARD2 11 +#define CLK_DOUT_FSYS0_QSPI 12 +#define CLK_DOUT_FSYS0_SFMC_NAND 13 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 14 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I 15 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250 16 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK 17 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250 18 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK 19 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I 20 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I 21 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK 22 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK 23 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK 24 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK 25 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK 26 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK 27 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK 28 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK 29 +#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN 30 +#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN 31 +#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN 32 +#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK 33 +#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK 34 +#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND 35 +#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK 36 +#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK 37 +#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK 38 +#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK 39 +#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK 40 +#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 41 + +/* CMU_FSYS1 */ +#define CLK_FOUT_FSYS1_PLL 1 +#define CLK_MOUT_FSYS1_SCAN0_USER 2 +#define CLK_MOUT_FSYS1_SCAN1_USER 3 +#define CLK_MOUT_FSYS1_BUS_USER 4 +#define CLK_DOUT_FSYS1_200 5 +#define CLK_DOUT_FSYS1_BUS_300 6 +#define CLK_DOUT_FSYS1_OTP_MEM 7 +#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL 8 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100 9 +#define CLK_GOUT_FSYS1_UART0_PCLK 10 +#define CLK_GOUT_FSYS1_UART0_SCLK_UART 11 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 12 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 13 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 14 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 15 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 16 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 17 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 18 +#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 19 +#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 20 +#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 21 +#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK 22 + +/* CMU_IMEM */ +#define CLK_MOUT_IMEM_ACLK_USER 1 +#define CLK_MOUT_IMEM_CA5_USER 2 +#define CLK_MOUT_IMEM_SSS_USER 3 +#define CLK_MOUT_IMEM_JPEG_USER 4 +#define CLK_DOUT_IMEM_PCLK 5 +#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK 6 +#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN 7 +#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG 8 +#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK 9 +#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN 10 +#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG 11 +#define CLK_GOUT_IMEM_MCT0_PCLK 12 +#define CLK_GOUT_IMEM_MCT1_PCLK 13 +#define CLK_GOUT_IMEM_MCT2_PCLK 14 +#define CLK_GOUT_IMEM_MCT3_PCLK 15 +#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 16 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_IP_USER 1 +#define CLK_MOUT_PERI_DISP_USER 2 +#define CLK_DOUT_PERI_125 3 +#define CLK_DOUT_PERI_PCLK 4 +#define CLK_DOUT_PERI_SPI 5 +#define CLK_DOUT_PERI_UART1 6 +#define CLK_DOUT_PERI_UART2 7 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 8 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 9 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK 10 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK 11 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK 12 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK 13 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK 14 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK 15 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK 16 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK 17 +#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 18 +#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 19 +#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 20 +#define CLK_GOUT_PERI_SPI0_PCLK 21 +#define CLK_GOUT_PERI_SPI0_SCLK_SPI 22 +#define CLK_GOUT_PERI_UART1_PCLK 23 +#define CLK_GOUT_PERI_UART1_SCLK_UART 24 +#define CLK_GOUT_PERI_UART2_PCLK 25 +#define CLK_GOUT_PERI_UART2_SCLK_UART 26 + +#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */ -- cgit v1.2.3 From 6e5913328102f818303b01e854df37fa9f251a47 Mon Sep 17 00:00:00 2001 From: Raghav Sharma Date: Mon, 2 Feb 2026 16:05:53 +0530 Subject: dt-bindings: clock: exynosautov920: add G3D clock definitions Add device tree clock binding definitions for CMU_G3D Signed-off-by: Raghav Sharma Link: https://patch.msgid.link/20260202103555.2089376-2-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/samsung,exynosautov920.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index 06dec27a8c77..f2628c220b22 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -309,4 +309,10 @@ #define CLK_MOUT_MFD_NOC_USER 1 #define CLK_DOUT_MFD_NOCP 2 +/* CMU_G3D */ +#define FOUT_PLL_G3D 1 +#define CLK_MOUT_G3D_NOC 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_NOCP_USER 4 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ -- cgit v1.2.3 From 8e3a93e7a1a3a788109ba005edf6223d389ab04f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 11 Mar 2026 16:46:31 +0200 Subject: dt-bindings: clock: qcom: document the Eliza Global Clock Controller Add bindings documentation for the Global Clock Controller on Qualcomm Eliza SoC. Reuse the Milos bindings schema since the controller resources are exactly the same, even though the controllers are incompatible between them. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,eliza-gcc.h | 210 +++++++++++++++++++++++++++++ 1 file changed, 210 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,eliza-gcc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,eliza-gcc.h b/include/dt-bindings/clock/qcom,eliza-gcc.h new file mode 100644 index 000000000000..4d27b329ae99 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-gcc.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2 +#define GCC_BOOT_ROM_AHB_CLK 3 +#define GCC_CAM_BIST_MCLK_AHB_CLK 4 +#define GCC_CAMERA_AHB_CLK 5 +#define GCC_CAMERA_HF_AXI_CLK 6 +#define GCC_CAMERA_SF_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 +#define GCC_CNOC_PCIE_SF_AXI_CLK 11 +#define GCC_DDRSS_GPU_AXI_CLK 12 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 13 +#define GCC_DISP_AHB_CLK 14 +#define GCC_DISP_HF_AXI_CLK 15 +#define GCC_GP1_CLK 16 +#define GCC_GP1_CLK_SRC 17 +#define GCC_GP2_CLK 18 +#define GCC_GP2_CLK_SRC 19 +#define GCC_GP3_CLK 20 +#define GCC_GP3_CLK_SRC 21 +#define GCC_GPLL0 22 +#define GCC_GPLL0_OUT_EVEN 23 +#define GCC_GPLL4 24 +#define GCC_GPLL7 25 +#define GCC_GPLL8 26 +#define GCC_GPLL9 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GEMNOC_GFX_CLK 29 +#define GCC_GPU_GPLL0_CPH_CLK_SRC 30 +#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 31 +#define GCC_GPU_SMMU_VOTE_CLK 32 +#define GCC_MMU_TCU_VOTE_CLK 33 +#define GCC_PCIE_0_AUX_CLK 34 +#define GCC_PCIE_0_AUX_CLK_SRC 35 +#define GCC_PCIE_0_CFG_AHB_CLK 36 +#define GCC_PCIE_0_MSTR_AXI_CLK 37 +#define GCC_PCIE_0_PHY_RCHNG_CLK 38 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 39 +#define GCC_PCIE_0_PIPE_CLK 40 +#define GCC_PCIE_0_PIPE_CLK_SRC 41 +#define GCC_PCIE_0_PIPE_DIV2_CLK 42 +#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 43 +#define GCC_PCIE_0_SLV_AXI_CLK 44 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 +#define GCC_PCIE_1_AUX_CLK 46 +#define GCC_PCIE_1_AUX_CLK_SRC 47 +#define GCC_PCIE_1_CFG_AHB_CLK 48 +#define GCC_PCIE_1_MSTR_AXI_CLK 49 +#define GCC_PCIE_1_PHY_RCHNG_CLK 50 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51 +#define GCC_PCIE_1_PIPE_CLK 52 +#define GCC_PCIE_1_PIPE_CLK_SRC 53 +#define GCC_PCIE_1_PIPE_DIV2_CLK 54 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 55 +#define GCC_PCIE_1_SLV_AXI_CLK 56 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 58 +#define GCC_PCIE_RSCC_XO_CLK 59 +#define GCC_PDM2_CLK 60 +#define GCC_PDM2_CLK_SRC 61 +#define GCC_PDM_AHB_CLK 62 +#define GCC_PDM_XO4_CLK 63 +#define GCC_QMIP_CAMERA_CMD_AHB_CLK 64 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 65 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 66 +#define GCC_QMIP_GPU_AHB_CLK 67 +#define GCC_QMIP_PCIE_AHB_CLK 68 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 71 +#define GCC_QUPV3_WRAP1_CORE_CLK 72 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 73 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S0_CLK 75 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S1_CLK 77 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S2_CLK 79 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 80 +#define GCC_QUPV3_WRAP1_S3_CLK 81 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 82 +#define GCC_QUPV3_WRAP1_S4_CLK 83 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 84 +#define GCC_QUPV3_WRAP1_S5_CLK 85 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 86 +#define GCC_QUPV3_WRAP1_S6_CLK 87 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 88 +#define GCC_QUPV3_WRAP1_S7_CLK 89 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 90 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 91 +#define GCC_QUPV3_WRAP2_CORE_CLK 92 +#define GCC_QUPV3_WRAP2_S0_CLK 93 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 94 +#define GCC_QUPV3_WRAP2_S1_CLK 95 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 96 +#define GCC_QUPV3_WRAP2_S2_CLK 97 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 98 +#define GCC_QUPV3_WRAP2_S3_CLK 99 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 100 +#define GCC_QUPV3_WRAP2_S4_CLK 101 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 102 +#define GCC_QUPV3_WRAP2_S5_CLK 103 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 104 +#define GCC_QUPV3_WRAP2_S6_CLK 105 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 106 +#define GCC_QUPV3_WRAP2_S7_CLK 107 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 108 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 109 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 110 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 111 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 112 +#define GCC_SDCC1_AHB_CLK 113 +#define GCC_SDCC1_APPS_CLK 114 +#define GCC_SDCC1_APPS_CLK_SRC 115 +#define GCC_SDCC1_ICE_CORE_CLK 116 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 117 +#define GCC_SDCC2_AHB_CLK 118 +#define GCC_SDCC2_APPS_CLK 119 +#define GCC_SDCC2_APPS_CLK_SRC 120 +#define GCC_UFS_PHY_AHB_CLK 121 +#define GCC_UFS_PHY_AXI_CLK 122 +#define GCC_UFS_PHY_AXI_CLK_SRC 123 +#define GCC_UFS_PHY_ICE_CORE_CLK 124 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 125 +#define GCC_UFS_PHY_PHY_AUX_CLK 126 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 127 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 128 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 129 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 130 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 131 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 132 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 133 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135 +#define GCC_USB30_PRIM_ATB_CLK 136 +#define GCC_USB30_PRIM_MASTER_CLK 137 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 138 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 139 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 140 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 141 +#define GCC_USB30_PRIM_SLEEP_CLK 142 +#define GCC_USB3_PRIM_PHY_AUX_CLK 143 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 146 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147 +#define GCC_VIDEO_AHB_CLK 148 +#define GCC_VIDEO_AXI0_CLK 149 +#define GCC_VIDEO_AXI1_CLK 150 +#define GCC_VIDEO_XO_CLK 151 + +/* GCC power domains */ +#define GCC_PCIE_0_GDSC 0 +#define GCC_PCIE_0_PHY_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_UFS_MEM_PHY_GDSC 4 +#define GCC_UFS_PHY_GDSC 5 +#define GCC_USB30_PRIM_GDSC 6 +#define GCC_USB3_PHY_GDSC 7 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PCIE_RSCC_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUPV3_WRAPPER_2_BCR 19 +#define GCC_QUSB2PHY_PRIM_BCR 20 +#define GCC_QUSB2PHY_SEC_BCR 21 +#define GCC_SDCC1_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_UFS_PHY_BCR 24 +#define GCC_USB30_PRIM_BCR 25 +#define GCC_USB3_DP_PHY_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_SEC_BCR 27 +#define GCC_USB3_PHY_PRIM_BCR 28 +#define GCC_USB3_PHY_SEC_BCR 29 +#define GCC_USB3PHY_PHY_PRIM_BCR 30 +#define GCC_USB3PHY_PHY_SEC_BCR 31 +#define GCC_VIDEO_AXI0_CLK_ARES 32 +#define GCC_VIDEO_AXI1_CLK_ARES 33 +#define GCC_VIDEO_BCR 34 + +#endif -- cgit v1.2.3 From b7518e0d1c0f4da4c0cc7940eed4679a5ff69a2e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 11 Mar 2026 16:46:32 +0200 Subject: dt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller Add bindings documentation for TCSR Clock Controller for Eliza SoC. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-2-453c4cf657a2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,eliza-tcsr.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,eliza-tcsr.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,eliza-tcsr.h b/include/dt-bindings/clock/qcom,eliza-tcsr.h new file mode 100644 index 000000000000..aeb5e2b1a47b --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-tcsr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H + +/* TCSR_CC clocks */ +#define TCSR_HDMI_CLKREF_EN 0 +#define TCSR_PCIE_0_CLKREF_EN 1 +#define TCSR_PCIE_1_CLKREF_EN 2 +#define TCSR_UFS_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif -- cgit v1.2.3 From a5c7b4fc8405846c613e7a01805a77d2e0cb75bd Mon Sep 17 00:00:00 2001 From: Val Packett Date: Tue, 3 Mar 2026 00:41:20 -0300 Subject: dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets Add the missing defines for MDSS resets, which are necessary to reset the display subsystem in order to avoid issues caused by state left over from the bootloader. While here, align comment style with other SoCs. Acked-by: Krzysztof Kozlowski Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20260303034847.13870-2-val@packett.cool Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,sm6115-dispcc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h index d1a6c45b5029..ab8d312ade37 100644 --- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H -/* DISP_CC clocks */ +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_MAIN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -30,7 +30,10 @@ #define DISP_CC_SLEEP_CLK 20 #define DISP_CC_SLEEP_CLK_SRC 21 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif -- cgit v1.2.3 From 0221b14be8aae98d687efab066133a114bea02d8 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Tue, 3 Mar 2026 00:41:21 -0300 Subject: dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets Add the missing defines for MDSS resets, which are necessary to reset the display subsystem in order to avoid issues caused by state left over from the bootloader. While here, align comment style with other SoCs. Acked-by: Krzysztof Kozlowski Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20260303034847.13870-3-val@packett.cool Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,dispcc-sm6125.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6125.h b/include/dt-bindings/clock/qcom,dispcc-sm6125.h index 4ff974f4fcc3..f58b85d2c814 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm6125.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm6125.h @@ -6,6 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_MDSS_AHB_CLK 1 #define DISP_CC_MDSS_AHB_CLK_SRC 2 @@ -35,7 +36,10 @@ #define DISP_CC_MDSS_VSYNC_CLK_SRC 26 #define DISP_CC_XO_CLK 27 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif -- cgit v1.2.3 From 20a107bca2a16c8aa20d62631d4fc45828607664 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Wed, 18 Mar 2026 14:09:43 +0530 Subject: dt-bindings: clock: add Qualcomm IPQ5210 GCC Add binding for the Qualcomm IPQ5210 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 ++++++++++++++++++++++++++ include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +++++++++++++++++++++++++++ 2 files changed, 253 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,ipq5210-gcc.h create mode 100644 include/dt-bindings/reset/qcom,ipq5210-gcc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,ipq5210-gcc.h b/include/dt-bindings/clock/qcom,ipq5210-gcc.h new file mode 100644 index 000000000000..84116f34ee4d --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-gcc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_CMN_12GPLL_AHB_CLK 2 +#define GCC_CMN_12GPLL_SYS_CLK 3 +#define GCC_CNOC_LPASS_CFG_CLK 4 +#define GCC_CNOC_PCIE0_1LANE_S_CLK 5 +#define GCC_CNOC_PCIE1_2LANE_S_CLK 6 +#define GCC_CNOC_USB_CLK 7 +#define GCC_GEPHY_SYS_CLK 8 +#define GCC_LPASS_AXIM_CLK_SRC 9 +#define GCC_LPASS_CORE_AXIM_CLK 10 +#define GCC_LPASS_SWAY_CLK 11 +#define GCC_LPASS_SWAY_CLK_SRC 12 +#define GCC_MDIO_AHB_CLK 13 +#define GCC_MDIO_GEPHY_AHB_CLK 14 +#define GCC_NSS_TS_CLK 15 +#define GCC_NSS_TS_CLK_SRC 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_PCIE0_AHB_CLK 31 +#define GCC_PCIE0_AUX_CLK 32 +#define GCC_PCIE0_AXI_M_CLK 33 +#define GCC_PCIE0_AXI_M_CLK_SRC 34 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 +#define GCC_PCIE0_AXI_S_CLK 36 +#define GCC_PCIE0_AXI_S_CLK_SRC 37 +#define GCC_PCIE0_PIPE_CLK 38 +#define GCC_PCIE0_PIPE_CLK_SRC 39 +#define GCC_PCIE0_RCHNG_CLK 40 +#define GCC_PCIE0_RCHNG_CLK_SRC 41 +#define GCC_PCIE1_AHB_CLK 42 +#define GCC_PCIE1_AUX_CLK 43 +#define GCC_PCIE1_AXI_M_CLK 44 +#define GCC_PCIE1_AXI_M_CLK_SRC 45 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 +#define GCC_PCIE1_AXI_S_CLK 47 +#define GCC_PCIE1_AXI_S_CLK_SRC 48 +#define GCC_PCIE1_PIPE_CLK 49 +#define GCC_PCIE1_PIPE_CLK_SRC 50 +#define GCC_PCIE1_RCHNG_CLK 51 +#define GCC_PCIE1_RCHNG_CLK_SRC 52 +#define GCC_PCIE_AUX_CLK_SRC 53 +#define GCC_PCNOC_BFDCD_CLK_SRC 54 +#define GCC_PON_APB_CLK 55 +#define GCC_PON_TM_CLK 56 +#define GCC_PON_TM2X_CLK 57 +#define GCC_PON_TM2X_CLK_SRC 58 +#define GCC_QDSS_AT_CLK 59 +#define GCC_QDSS_AT_CLK_SRC 60 +#define GCC_QDSS_DAP_CLK 61 +#define GCC_QDSS_TSCTR_CLK_SRC 62 +#define GCC_QPIC_AHB_CLK 63 +#define GCC_QPIC_CLK 64 +#define GCC_QPIC_CLK_SRC 65 +#define GCC_QPIC_IO_MACRO_CLK 66 +#define GCC_QPIC_IO_MACRO_CLK_SRC 67 +#define GCC_QRNG_AHB_CLK 68 +#define GCC_QUPV3_AHB_MST_CLK 69 +#define GCC_QUPV3_AHB_SLV_CLK 70 +#define GCC_QUPV3_WRAP_SE0_CLK 71 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 +#define GCC_QUPV3_WRAP_SE1_CLK 73 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 +#define GCC_QUPV3_WRAP_SE2_CLK 75 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 +#define GCC_QUPV3_WRAP_SE3_CLK 77 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 +#define GCC_QUPV3_WRAP_SE4_CLK 79 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 +#define GCC_QUPV3_WRAP_SE5_CLK 81 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 +#define GCC_SDCC1_AHB_CLK 83 +#define GCC_SDCC1_APPS_CLK 84 +#define GCC_SDCC1_APPS_CLK_SRC 85 +#define GCC_SDCC1_ICE_CORE_CLK 86 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 87 +#define GCC_SLEEP_CLK_SRC 88 +#define GCC_SNOC_LPASS_CLK 89 +#define GCC_SNOC_PCIE0_AXI_M_CLK 90 +#define GCC_SNOC_PCIE1_AXI_M_CLK 91 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 +#define GCC_UNIPHY0_AHB_CLK 93 +#define GCC_UNIPHY0_SYS_CLK 94 +#define GCC_UNIPHY1_AHB_CLK 95 +#define GCC_UNIPHY1_SYS_CLK 96 +#define GCC_UNIPHY2_AHB_CLK 97 +#define GCC_UNIPHY2_SYS_CLK 98 +#define GCC_UNIPHY_SYS_CLK_SRC 99 +#define GCC_USB0_AUX_CLK 100 +#define GCC_USB0_AUX_CLK_SRC 101 +#define GCC_USB0_MASTER_CLK 102 +#define GCC_USB0_MASTER_CLK_SRC 103 +#define GCC_USB0_MOCK_UTMI_CLK 104 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 105 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 +#define GCC_USB0_PHY_CFG_AHB_CLK 107 +#define GCC_USB0_PIPE_CLK 108 +#define GCC_USB0_PIPE_CLK_SRC 109 +#define GCC_USB0_SLEEP_CLK 110 +#define GCC_XO_CLK_SRC 111 +#define GPLL0_MAIN 112 +#define GPLL0 113 +#define GPLL2_MAIN 114 +#define GPLL2 115 +#define GPLL4_MAIN 116 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq5210-gcc.h b/include/dt-bindings/reset/qcom,ipq5210-gcc.h new file mode 100644 index 000000000000..09890a09087c --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5210-gcc.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3 +#define GCC_APSS_AHB_ARES 4 +#define GCC_APSS_ATB_ARES 5 +#define GCC_APSS_AXI_ARES 6 +#define GCC_APSS_TS_ARES 7 +#define GCC_BOOT_ROM_AHB_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_GEPHY_BCR 10 +#define GCC_GEPHY_SYS_ARES 11 +#define GCC_GP1_ARES 12 +#define GCC_GP2_ARES 13 +#define GCC_GP3_ARES 14 +#define GCC_MDIO_AHB_ARES 15 +#define GCC_MDIO_BCR 16 +#define GCC_MDIO_GEPHY_AHB_ARES 17 +#define GCC_NSS_BCR 18 +#define GCC_NSS_TS_ARES 19 +#define GCC_NSSCC_ARES 20 +#define GCC_NSSCFG_ARES 21 +#define GCC_NSSNOC_ATB_ARES 22 +#define GCC_NSSNOC_MEMNOC_1_ARES 23 +#define GCC_NSSNOC_MEMNOC_ARES 24 +#define GCC_NSSNOC_NSSCC_ARES 25 +#define GCC_NSSNOC_PCNOC_1_ARES 26 +#define GCC_NSSNOC_QOSGEN_REF_ARES 27 +#define GCC_NSSNOC_SNOC_1_ARES 28 +#define GCC_NSSNOC_SNOC_ARES 29 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 30 +#define GCC_NSSNOC_XO_DCD_ARES 31 +#define GCC_PCIE0_AHB_ARES 32 +#define GCC_PCIE0_AUX_ARES 33 +#define GCC_PCIE0_AXI_M_ARES 34 +#define GCC_PCIE0_AXI_S_BRIDGE_ARES 35 +#define GCC_PCIE0_AXI_S_ARES 36 +#define GCC_PCIE0_BCR 37 +#define GCC_PCIE0_LINK_DOWN_BCR 38 +#define GCC_PCIE0_PHY_BCR 39 +#define GCC_PCIE0_PIPE_ARES 40 +#define GCC_PCIE0PHY_PHY_BCR 41 +#define GCC_PCIE1_AHB_ARES 42 +#define GCC_PCIE1_AUX_ARES 43 +#define GCC_PCIE1_AXI_M_ARES 44 +#define GCC_PCIE1_AXI_S_BRIDGE_ARES 45 +#define GCC_PCIE1_AXI_S_ARES 46 +#define GCC_PCIE1_BCR 47 +#define GCC_PCIE1_LINK_DOWN_BCR 48 +#define GCC_PCIE1_PHY_BCR 49 +#define GCC_PCIE1_PIPE_ARES 50 +#define GCC_PCIE1PHY_PHY_BCR 51 +#define GCC_QRNG_AHB_ARES 52 +#define GCC_QRNG_BCR 53 +#define GCC_QUPV3_2X_CORE_ARES 54 +#define GCC_QUPV3_AHB_MST_ARES 55 +#define GCC_QUPV3_AHB_SLV_ARES 56 +#define GCC_QUPV3_BCR 57 +#define GCC_QUPV3_CORE_ARES 58 +#define GCC_QUPV3_WRAP_SE0_ARES 59 +#define GCC_QUPV3_WRAP_SE0_BCR 60 +#define GCC_QUPV3_WRAP_SE1_ARES 61 +#define GCC_QUPV3_WRAP_SE1_BCR 62 +#define GCC_QUPV3_WRAP_SE2_ARES 63 +#define GCC_QUPV3_WRAP_SE2_BCR 64 +#define GCC_QUPV3_WRAP_SE3_ARES 65 +#define GCC_QUPV3_WRAP_SE3_BCR 66 +#define GCC_QUPV3_WRAP_SE4_ARES 67 +#define GCC_QUPV3_WRAP_SE4_BCR 68 +#define GCC_QUPV3_WRAP_SE5_ARES 69 +#define GCC_QUPV3_WRAP_SE5_BCR 70 +#define GCC_QUSB2_0_PHY_BCR 71 +#define GCC_SDCC1_AHB_ARES 72 +#define GCC_SDCC1_APPS_ARES 73 +#define GCC_SDCC1_ICE_CORE_ARES 74 +#define GCC_SDCC_BCR 75 +#define GCC_TLMM_AHB_ARES 76 +#define GCC_TLMM_ARES 77 +#define GCC_TLMM_BCR 78 +#define GCC_UNIPHY0_AHB_ARES 79 +#define GCC_UNIPHY0_BCR 80 +#define GCC_UNIPHY0_SYS_ARES 81 +#define GCC_UNIPHY1_AHB_ARES 82 +#define GCC_UNIPHY1_BCR 83 +#define GCC_UNIPHY1_SYS_ARES 84 +#define GCC_UNIPHY2_AHB_ARES 85 +#define GCC_UNIPHY2_BCR 86 +#define GCC_UNIPHY2_SYS_ARES 87 +#define GCC_USB0_AUX_ARES 88 +#define GCC_USB0_MASTER_ARES 89 +#define GCC_USB0_MOCK_UTMI_ARES 90 +#define GCC_USB0_PHY_BCR 91 +#define GCC_USB0_PHY_CFG_AHB_ARES 92 +#define GCC_USB0_PIPE_ARES 93 +#define GCC_USB0_SLEEP_ARES 94 +#define GCC_USB3PHY_0_PHY_BCR 95 +#define GCC_USB_BCR 96 +#define GCC_PCIE0_PIPE_RESET 97 +#define GCC_PCIE0_CORE_STICKY_RESET 98 +#define GCC_PCIE0_AXI_S_STICKY_RESET 99 +#define GCC_PCIE0_AXI_S_RESET 100 +#define GCC_PCIE0_AXI_M_STICKY_RESET 101 +#define GCC_PCIE0_AXI_M_RESET 102 +#define GCC_PCIE0_AUX_RESET 103 +#define GCC_PCIE0_AHB_RESET 104 +#define GCC_PCIE1_PIPE_RESET 105 +#define GCC_PCIE1_CORE_STICKY_RESET 106 +#define GCC_PCIE1_AXI_S_STICKY_RESET 107 +#define GCC_PCIE1_AXI_S_RESET 108 +#define GCC_PCIE1_AXI_M_STICKY_RESET 109 +#define GCC_PCIE1_AXI_M_RESET 110 +#define GCC_PCIE1_AUX_RESET 111 +#define GCC_PCIE1_AHB_RESET 112 +#define GCC_UNIPHY0_XPCS_ARES 113 +#define GCC_UNIPHY1_XPCS_ARES 114 +#define GCC_UNIPHY2_XPCS_ARES 115 +#define GCC_QDSS_BCR 116 + +#endif -- cgit v1.2.3 From 76404ffbf07f28a5ec04748e18fce3dac2e78ef6 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Thu, 12 Mar 2026 08:12:06 -0300 Subject: dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs There are 5 more GDSCs that we were ignoring and not putting to sleep, which are listed in downstream DTS. Add them. Signed-off-by: Val Packett Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260312112321.370983-2-val@packett.cool Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-sc8180x.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h index b9d8438a15ff..9ed7b794aacc 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -322,5 +322,10 @@ #define USB30_MP_GDSC 8 #define USB30_PRIM_GDSC 9 #define USB30_SEC_GDSC 10 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 11 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 12 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 13 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 14 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 15 #endif -- cgit v1.2.3 From a4f78912aec5092ed8ddc09d987e296c01c77353 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 19 Mar 2026 12:49:42 +0100 Subject: dt-bindings: clock: qcom,eliza-dispcc: Add Eliza SoC display CC Add bindings for Qualcomm Eliza SoC display clock controller (dispcc), which is very similar to one in SM8750, except new HDMI-related clocks and additional clock input from HDMI PHY PLL. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,eliza-dispcc.h | 118 ++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,eliza-dispcc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,eliza-dispcc.h b/include/dt-bindings/clock/qcom,eliza-dispcc.h new file mode 100644 index 000000000000..30c6d856fa98 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-dispcc.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_PLL1 1 +#define DISP_CC_PLL2 2 +#define DISP_CC_ESYNC0_CLK 3 +#define DISP_CC_ESYNC0_CLK_SRC 4 +#define DISP_CC_ESYNC1_CLK 5 +#define DISP_CC_ESYNC1_CLK_SRC 6 +#define DISP_CC_MDSS_ACCU_SHIFT_CLK 7 +#define DISP_CC_MDSS_AHB1_CLK 8 +#define DISP_CC_MDSS_AHB_CLK 9 +#define DISP_CC_MDSS_AHB_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE0_CLK 11 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 12 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 13 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 14 +#define DISP_CC_MDSS_BYTE1_CLK 15 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 16 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 17 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 18 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 19 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 20 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 21 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 22 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 23 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 25 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 26 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 27 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 28 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 29 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 30 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 31 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 33 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 34 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 35 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 36 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 37 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 38 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 39 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 40 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 42 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 43 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 44 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 45 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 46 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 47 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 54 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 55 +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 56 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 57 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 60 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 61 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 62 +#define DISP_CC_MDSS_ESC0_CLK 63 +#define DISP_CC_MDSS_ESC0_CLK_SRC 64 +#define DISP_CC_MDSS_ESC1_CLK 65 +#define DISP_CC_MDSS_ESC1_CLK_SRC 66 +#define DISP_CC_MDSS_HDMI_AHBM_CLK 67 +#define DISP_CC_MDSS_HDMI_APP_CLK 68 +#define DISP_CC_MDSS_HDMI_APP_CLK_SRC 69 +#define DISP_CC_MDSS_HDMI_CRYPTO_CLK 70 +#define DISP_CC_MDSS_HDMI_INTF_CLK 71 +#define DISP_CC_MDSS_HDMI_PCLK_CLK 72 +#define DISP_CC_MDSS_HDMI_PCLK_CLK_SRC 73 +#define DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC 74 +#define DISP_CC_MDSS_MDP1_CLK 75 +#define DISP_CC_MDSS_MDP_CLK 76 +#define DISP_CC_MDSS_MDP_CLK_SRC 77 +#define DISP_CC_MDSS_MDP_LUT1_CLK 78 +#define DISP_CC_MDSS_MDP_LUT_CLK 79 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 80 +#define DISP_CC_MDSS_PCLK0_CLK 81 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 82 +#define DISP_CC_MDSS_PCLK1_CLK 83 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 84 +#define DISP_CC_MDSS_PCLK2_CLK 85 +#define DISP_CC_MDSS_PCLK2_CLK_SRC 86 +#define DISP_CC_MDSS_RSCC_AHB_CLK 87 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 88 +#define DISP_CC_MDSS_VSYNC1_CLK 89 +#define DISP_CC_MDSS_VSYNC_CLK 90 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 91 +#define DISP_CC_OSC_CLK 92 +#define DISP_CC_OSC_CLK_SRC 93 +#define DISP_CC_SLEEP_CLK 94 +#define DISP_CC_SLEEP_CLK_SRC 95 +#define DISP_CC_XO_CLK 96 +#define DISP_CC_XO_CLK_SRC 97 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 +#define MDSS_INT2_GDSC 1 + +#endif -- cgit v1.2.3 From 5d6c477687aeb158df9ec95580270146778f6af1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 24 Feb 2026 12:17:18 +0100 Subject: clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Reviewed-by: Brian Masney Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Signed-off-by: Andy Shevchenko Acked-by: Rob Herring (Arm) Reviewed-by: Randy Dunlap Signed-off-by: Stephen Boyd --- include/dt-bindings/clock/bt1-ccu.h | 48 ------------------------------------- 1 file changed, 48 deletions(-) delete mode 100644 include/dt-bindings/clock/bt1-ccu.h (limited to 'include') diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h deleted file mode 100644 index 5f166d27a00a..000000000000 --- a/include/dt-bindings/clock/bt1-ccu.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC - * - * Baikal-T1 CCU clock indices - */ -#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H -#define __DT_BINDINGS_CLOCK_BT1_CCU_H - -#define CCU_CPU_PLL 0 -#define CCU_SATA_PLL 1 -#define CCU_DDR_PLL 2 -#define CCU_PCIE_PLL 3 -#define CCU_ETH_PLL 4 - -#define CCU_AXI_MAIN_CLK 0 -#define CCU_AXI_DDR_CLK 1 -#define CCU_AXI_SATA_CLK 2 -#define CCU_AXI_GMAC0_CLK 3 -#define CCU_AXI_GMAC1_CLK 4 -#define CCU_AXI_XGMAC_CLK 5 -#define CCU_AXI_PCIE_M_CLK 6 -#define CCU_AXI_PCIE_S_CLK 7 -#define CCU_AXI_USB_CLK 8 -#define CCU_AXI_HWA_CLK 9 -#define CCU_AXI_SRAM_CLK 10 - -#define CCU_SYS_SATA_REF_CLK 0 -#define CCU_SYS_APB_CLK 1 -#define CCU_SYS_GMAC0_TX_CLK 2 -#define CCU_SYS_GMAC0_PTP_CLK 3 -#define CCU_SYS_GMAC1_TX_CLK 4 -#define CCU_SYS_GMAC1_PTP_CLK 5 -#define CCU_SYS_XGMAC_REF_CLK 6 -#define CCU_SYS_XGMAC_PTP_CLK 7 -#define CCU_SYS_USB_CLK 8 -#define CCU_SYS_PVT_CLK 9 -#define CCU_SYS_HWA_CLK 10 -#define CCU_SYS_UART_CLK 11 -#define CCU_SYS_I2C1_CLK 12 -#define CCU_SYS_I2C2_CLK 13 -#define CCU_SYS_GPIO_CLK 14 -#define CCU_SYS_TIMER0_CLK 15 -#define CCU_SYS_TIMER1_CLK 16 -#define CCU_SYS_TIMER2_CLK 17 -#define CCU_SYS_WDT_CLK 18 - -#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ -- cgit v1.2.3 From fc6e29d42872680dca017f2e5169eefe971f8d89 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jan 2026 12:19:25 +0100 Subject: dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets The MDSS resets have so far been left undescribed. Fix that. Fixes: 75616da71291 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings") Signed-off-by: Konrad Dybcio Reviewed-by: Taniya Das Acked-by: Krzysztof Kozlowski Tested-by: Val Packett # sc7180-ecs-liva-qc710 Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,dispcc-sc7180.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bindings/clock/qcom,dispcc-sc7180.h index b9b51617a335..070510306074 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sc7180.h +++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h @@ -6,6 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_EVEN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -40,7 +41,11 @@ #define DISP_CC_MDSS_VSYNC_CLK_SRC 31 #define DISP_CC_XO_CLK 32 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +/* GDSCs */ #define MDSS_GDSC 0 #endif -- cgit v1.2.3 From bf9462c82721e42f49e4a62efe96ef7b41a5e42e Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Fri, 20 Mar 2026 21:15:13 +0000 Subject: dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock Add a constant for APM-to-AP mailbox clock. This clock is needed to access this mailbox registers. Signed-off-by: Alexey Klimov Link: https://patch.msgid.link/20260320-exynos850-ap2apm-mailbox-v1-1-983eb3f296fc@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos850.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 80dacda57229..95285589615a 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -126,6 +126,7 @@ #define CLK_GOUT_GPIO_ALIVE_PCLK 22 #define CLK_GOUT_PMU_ALIVE_PCLK 23 #define CLK_GOUT_SYSREG_APM_PCLK 24 +#define CLK_GOUT_MAILBOX_APM_AP_PCLK 25 /* CMU_AUD */ #define CLK_DOUT_AUD_AUDIF 1 -- cgit v1.2.3 From a57666004f49fa5031d6bf388834213e6f961922 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 11 Mar 2026 19:39:38 +0100 Subject: dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018 The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking subsystem. Add the related compatible for IPQ6018 to the ipq9574-cmn-pll generic schema. Signed-off-by: John Crispin Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h new file mode 100644 index 000000000000..28d325beb073 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ6018_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ6018. */ +#define IPQ6018_BIAS_PLL_CC_CLK 1 +#define IPQ6018_BIAS_PLL_NSS_NOC_CLK 2 +#endif -- cgit v1.2.3 From 7156c65030006e6930dd99c5b8c5e84e69ca5f0b Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 11 Mar 2026 19:39:40 +0100 Subject: dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking subsystem. Add the related compatible for IPQ8074 to the ipq9574-cmn-pll generic schema. Signed-off-by: John Crispin Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h new file mode 100644 index 000000000000..354258a481c2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ8074_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ8074. */ +#define IPQ8074_BIAS_PLL_CC_CLK 1 +#define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2 +#endif -- cgit v1.2.3 From 4aeadf8a18dbbe4fbe2f8e6f03f48f3492c8d1d1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 5 Mar 2026 16:10:08 +0530 Subject: dt-bindings: clock: qcom: Add SM8750 GPU clocks The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. GPU_CC block requires the MX and CX rail control and thus add the corresponding power-domains and require-opps. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Update the bindings to accommodate for SM8750 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,sm8750-gpucc.h | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8750-gpucc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 000000000000..e2143d905fec --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +#endif -- cgit v1.2.3 From 31fcf6995e74117fe235a7a07a6e13077070b4a2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 3 Apr 2026 16:10:49 +0200 Subject: dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller The Nord SoC TCSR block provides CLKREF clocks for DP, PCIe, UFS, SGMII and USB. Signed-off-by: Taniya Das [Shawn: Use compatible qcom,nord-tcsrcc rather than qcom,nord-tcsr] Signed-off-by: Shawn Guo Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260403-nord-clks-v1-1-018af14979fd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,nord-tcsrcc.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,nord-tcsrcc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h new file mode 100644 index 000000000000..3f0e2ff7acc7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H + +/* TCSR_CC clocks */ +#define TCSR_DP_RX_0_CLKREF_EN 0 +#define TCSR_DP_RX_1_CLKREF_EN 1 +#define TCSR_DP_TX_0_CLKREF_EN 2 +#define TCSR_DP_TX_1_CLKREF_EN 3 +#define TCSR_DP_TX_2_CLKREF_EN 4 +#define TCSR_DP_TX_3_CLKREF_EN 5 +#define TCSR_PCIE_CLKREF_EN 6 +#define TCSR_UFS_CLKREF_EN 7 +#define TCSR_USB2_0_CLKREF_EN 8 +#define TCSR_USB2_1_CLKREF_EN 9 +#define TCSR_USB2_2_CLKREF_EN 10 +#define TCSR_USB3_0_CLKREF_EN 11 +#define TCSR_USB3_1_CLKREF_EN 12 +#define TCSR_UX_SGMII_0_CLKREF_EN 13 +#define TCSR_UX_SGMII_1_CLKREF_EN 14 + +#endif -- cgit v1.2.3 From 06498d59bb4e10032b1495762a999d640fe4a8dc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 3 Apr 2026 16:10:51 +0200 Subject: dt-bindings: clock: qcom: Add Nord Global Clock Controller Add device tree bindings for the global clock controller on Qualcomm Nord platform. The global clock controller on Nord SoC is divided into multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of the bindings to define the clock controllers. Signed-off-by: Taniya Das Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260403-nord-clks-v1-3-018af14979fd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,nord-gcc.h | 147 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-negcc.h | 124 +++++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-nwgcc.h | 69 +++++++++++++ include/dt-bindings/clock/qcom,nord-segcc.h | 98 +++++++++++++++++++ 4 files changed, 438 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,nord-gcc.h create mode 100644 include/dt-bindings/clock/qcom,nord-negcc.h create mode 100644 include/dt-bindings/clock/qcom,nord-nwgcc.h create mode 100644 include/dt-bindings/clock/qcom,nord-segcc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h new file mode 100644 index 000000000000..8fbde162c859 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gcc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H + +/* GCC clocks */ +#define GCC_BOOT_ROM_AHB_CLK 0 +#define GCC_GP1_CLK 1 +#define GCC_GP1_CLK_SRC 2 +#define GCC_GP2_CLK 3 +#define GCC_GP2_CLK_SRC 4 +#define GCC_GPLL0 5 +#define GCC_GPLL0_OUT_EVEN 6 +#define GCC_MMU_0_TCU_VOTE_CLK 7 +#define GCC_PCIE_A_AUX_CLK 8 +#define GCC_PCIE_A_AUX_CLK_SRC 9 +#define GCC_PCIE_A_CFG_AHB_CLK 10 +#define GCC_PCIE_A_DTI_QTC_CLK 11 +#define GCC_PCIE_A_MSTR_AXI_CLK 12 +#define GCC_PCIE_A_PHY_AUX_CLK 13 +#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14 +#define GCC_PCIE_A_PHY_RCHNG_CLK 15 +#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16 +#define GCC_PCIE_A_PIPE_CLK 17 +#define GCC_PCIE_A_PIPE_CLK_SRC 18 +#define GCC_PCIE_A_SLV_AXI_CLK 19 +#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20 +#define GCC_PCIE_B_AUX_CLK 21 +#define GCC_PCIE_B_AUX_CLK_SRC 22 +#define GCC_PCIE_B_CFG_AHB_CLK 23 +#define GCC_PCIE_B_DTI_QTC_CLK 24 +#define GCC_PCIE_B_MSTR_AXI_CLK 25 +#define GCC_PCIE_B_PHY_AUX_CLK 26 +#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27 +#define GCC_PCIE_B_PHY_RCHNG_CLK 28 +#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29 +#define GCC_PCIE_B_PIPE_CLK 30 +#define GCC_PCIE_B_PIPE_CLK_SRC 31 +#define GCC_PCIE_B_SLV_AXI_CLK 32 +#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33 +#define GCC_PCIE_C_AUX_CLK 34 +#define GCC_PCIE_C_AUX_CLK_SRC 35 +#define GCC_PCIE_C_CFG_AHB_CLK 36 +#define GCC_PCIE_C_DTI_QTC_CLK 37 +#define GCC_PCIE_C_MSTR_AXI_CLK 38 +#define GCC_PCIE_C_PHY_AUX_CLK 39 +#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40 +#define GCC_PCIE_C_PHY_RCHNG_CLK 41 +#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_C_PIPE_CLK 43 +#define GCC_PCIE_C_PIPE_CLK_SRC 44 +#define GCC_PCIE_C_SLV_AXI_CLK 45 +#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46 +#define GCC_PCIE_D_AUX_CLK 47 +#define GCC_PCIE_D_AUX_CLK_SRC 48 +#define GCC_PCIE_D_CFG_AHB_CLK 49 +#define GCC_PCIE_D_DTI_QTC_CLK 50 +#define GCC_PCIE_D_MSTR_AXI_CLK 51 +#define GCC_PCIE_D_PHY_AUX_CLK 52 +#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53 +#define GCC_PCIE_D_PHY_RCHNG_CLK 54 +#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55 +#define GCC_PCIE_D_PIPE_CLK 56 +#define GCC_PCIE_D_PIPE_CLK_SRC 57 +#define GCC_PCIE_D_SLV_AXI_CLK 58 +#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59 +#define GCC_PCIE_LINK_AHB_CLK 60 +#define GCC_PCIE_LINK_XO_CLK 61 +#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62 +#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63 +#define GCC_PCIE_NOC_M_CFG_CLK 64 +#define GCC_PCIE_NOC_M_PDB_CLK 65 +#define GCC_PCIE_NOC_MSTR_AXI_CLK 66 +#define GCC_PCIE_NOC_PWRCTL_CLK 67 +#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68 +#define GCC_PCIE_NOC_REFGEN_CLK 69 +#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70 +#define GCC_PCIE_NOC_S_CFG_CLK 71 +#define GCC_PCIE_NOC_S_PDB_CLK 72 +#define GCC_PCIE_NOC_SAFETY_CLK 73 +#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74 +#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75 +#define GCC_PCIE_NOC_TSCTR_CLK 76 +#define GCC_PCIE_NOC_XO_CLK 77 +#define GCC_PDM2_CLK 78 +#define GCC_PDM2_CLK_SRC 79 +#define GCC_PDM_AHB_CLK 80 +#define GCC_PDM_XO4_CLK 81 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82 +#define GCC_QUPV3_WRAP3_CORE_CLK 83 +#define GCC_QUPV3_WRAP3_M_CLK 84 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86 +#define GCC_QUPV3_WRAP3_S0_CLK 87 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88 +#define GCC_QUPV3_WRAP3_S_AHB_CLK 89 +#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90 + +/* GCC power domains */ +#define GCC_PCIE_A_GDSC 0 +#define GCC_PCIE_A_PHY_GDSC 1 +#define GCC_PCIE_B_GDSC 2 +#define GCC_PCIE_B_PHY_GDSC 3 +#define GCC_PCIE_C_GDSC 4 +#define GCC_PCIE_C_PHY_GDSC 5 +#define GCC_PCIE_D_GDSC 6 +#define GCC_PCIE_D_PHY_GDSC 7 +#define GCC_PCIE_NOC_GDSC 8 + +/* GCC resets */ +#define GCC_PCIE_A_BCR 0 +#define GCC_PCIE_A_LINK_DOWN_BCR 1 +#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2 +#define GCC_PCIE_A_PHY_BCR 3 +#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4 +#define GCC_PCIE_A_PHY_COM_BCR 5 +#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_B_BCR 7 +#define GCC_PCIE_B_LINK_DOWN_BCR 8 +#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_B_PHY_BCR 10 +#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11 +#define GCC_PCIE_B_PHY_COM_BCR 12 +#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_C_BCR 14 +#define GCC_PCIE_C_LINK_DOWN_BCR 15 +#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_C_PHY_BCR 17 +#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18 +#define GCC_PCIE_C_PHY_COM_BCR 19 +#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20 +#define GCC_PCIE_D_BCR 21 +#define GCC_PCIE_D_LINK_DOWN_BCR 22 +#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23 +#define GCC_PCIE_D_PHY_BCR 24 +#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25 +#define GCC_PCIE_D_PHY_COM_BCR 26 +#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27 +#define GCC_PCIE_NOC_BCR 28 +#define GCC_PDM_BCR 29 +#define GCC_QUPV3_WRAPPER_3_BCR 30 +#define GCC_TCSR_PCIE_BCR 31 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h new file mode 100644 index 000000000000..95f333d8e1aa --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-negcc.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H + +/* NE_GCC clocks */ +#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0 +#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1 +#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2 +#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3 +#define NE_GCC_AHB2PHY_CLK 4 +#define NE_GCC_CNOC_USB2_AXI_CLK 5 +#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6 +#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7 +#define NE_GCC_FRQ_MEASURE_REF_CLK 8 +#define NE_GCC_GP1_CLK 9 +#define NE_GCC_GP1_CLK_SRC 10 +#define NE_GCC_GP2_CLK 11 +#define NE_GCC_GP2_CLK_SRC 12 +#define NE_GCC_GPLL0 13 +#define NE_GCC_GPLL0_OUT_EVEN 14 +#define NE_GCC_GPLL2 15 +#define NE_GCC_GPU_2_CFG_CLK 16 +#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17 +#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18 +#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19 +#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20 +#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21 +#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22 +#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23 +#define NE_GCC_QUPV3_WRAP2_S0_CLK 24 +#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25 +#define NE_GCC_QUPV3_WRAP2_S1_CLK 26 +#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27 +#define NE_GCC_QUPV3_WRAP2_S2_CLK 28 +#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29 +#define NE_GCC_QUPV3_WRAP2_S3_CLK 30 +#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31 +#define NE_GCC_QUPV3_WRAP2_S4_CLK 32 +#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33 +#define NE_GCC_QUPV3_WRAP2_S5_CLK 34 +#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35 +#define NE_GCC_QUPV3_WRAP2_S6_CLK 36 +#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37 +#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38 +#define NE_GCC_SDCC4_APPS_CLK 39 +#define NE_GCC_SDCC4_APPS_CLK_SRC 40 +#define NE_GCC_SDCC4_AXI_CLK 41 +#define NE_GCC_UFS_PHY_AHB_CLK 42 +#define NE_GCC_UFS_PHY_AXI_CLK 43 +#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56 +#define NE_GCC_USB20_MASTER_CLK 57 +#define NE_GCC_USB20_MASTER_CLK_SRC 58 +#define NE_GCC_USB20_MOCK_UTMI_CLK 59 +#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60 +#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61 +#define NE_GCC_USB20_SLEEP_CLK 62 +#define NE_GCC_USB31_PRIM_ATB_CLK 63 +#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64 +#define NE_GCC_USB31_PRIM_MASTER_CLK 65 +#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define NE_GCC_USB31_PRIM_SLEEP_CLK 70 +#define NE_GCC_USB31_SEC_ATB_CLK 71 +#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72 +#define NE_GCC_USB31_SEC_MASTER_CLK 73 +#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76 +#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77 +#define NE_GCC_USB31_SEC_SLEEP_CLK 78 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80 +#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85 +#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88 + +/* NE_GCC power domains */ +#define NE_GCC_UFS_MEM_PHY_GDSC 0 +#define NE_GCC_UFS_PHY_GDSC 1 +#define NE_GCC_USB20_PRIM_GDSC 2 +#define NE_GCC_USB31_PRIM_GDSC 3 +#define NE_GCC_USB31_SEC_GDSC 4 +#define NE_GCC_USB3_PHY_GDSC 5 +#define NE_GCC_USB3_SEC_PHY_GDSC 6 + +/* NE_GCC resets */ +#define NE_GCC_GPU_2_BCR 0 +#define NE_GCC_QUPV3_WRAPPER_2_BCR 1 +#define NE_GCC_SDCC4_BCR 2 +#define NE_GCC_UFS_PHY_BCR 3 +#define NE_GCC_USB20_PRIM_BCR 4 +#define NE_GCC_USB31_PRIM_BCR 5 +#define NE_GCC_USB31_SEC_BCR 6 +#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7 +#define NE_GCC_USB3_DP_PHY_SEC_BCR 8 +#define NE_GCC_USB3_PHY_PRIM_BCR 9 +#define NE_GCC_USB3_PHY_SEC_BCR 10 +#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11 +#define NE_GCC_USB3PHY_PHY_SEC_BCR 12 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h new file mode 100644 index 000000000000..b6253dd2aa85 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H + +/* NW_GCC clocks */ +#define NW_GCC_ACMU_MUX_CLK 0 +#define NW_GCC_CAMERA_AHB_CLK 1 +#define NW_GCC_CAMERA_HF_AXI_CLK 2 +#define NW_GCC_CAMERA_SF_AXI_CLK 3 +#define NW_GCC_CAMERA_TRIG_CLK 4 +#define NW_GCC_CAMERA_XO_CLK 5 +#define NW_GCC_DISP_0_AHB_CLK 6 +#define NW_GCC_DISP_0_HF_AXI_CLK 7 +#define NW_GCC_DISP_0_TRIG_CLK 8 +#define NW_GCC_DISP_1_AHB_CLK 9 +#define NW_GCC_DISP_1_HF_AXI_CLK 10 +#define NW_GCC_DISP_1_TRIG_CLK 11 +#define NW_GCC_DPRX0_AXI_HF_CLK 12 +#define NW_GCC_DPRX0_CFG_AHB_CLK 13 +#define NW_GCC_DPRX1_AXI_HF_CLK 14 +#define NW_GCC_DPRX1_CFG_AHB_CLK 15 +#define NW_GCC_EVA_AHB_CLK 16 +#define NW_GCC_EVA_AXI0_CLK 17 +#define NW_GCC_EVA_AXI0C_CLK 18 +#define NW_GCC_EVA_TRIG_CLK 19 +#define NW_GCC_EVA_XO_CLK 20 +#define NW_GCC_FRQ_MEASURE_REF_CLK 21 +#define NW_GCC_GP1_CLK 22 +#define NW_GCC_GP1_CLK_SRC 23 +#define NW_GCC_GP2_CLK 24 +#define NW_GCC_GP2_CLK_SRC 25 +#define NW_GCC_GPLL0 26 +#define NW_GCC_GPLL0_OUT_EVEN 27 +#define NW_GCC_GPU_2_CFG_AHB_CLK 28 +#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29 +#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30 +#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31 +#define NW_GCC_GPU_CFG_AHB_CLK 32 +#define NW_GCC_GPU_GPLL0_CLK_SRC 33 +#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34 +#define NW_GCC_GPU_HSCNOC_GFX_CLK 35 +#define NW_GCC_GPU_SMMU_VOTE_CLK 36 +#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37 +#define NW_GCC_HSCNOC_GPU_AXI_CLK 38 +#define NW_GCC_MMU_1_TCU_VOTE_CLK 39 +#define NW_GCC_VIDEO_AHB_CLK 40 +#define NW_GCC_VIDEO_AXI0_CLK 41 +#define NW_GCC_VIDEO_AXI0C_CLK 42 +#define NW_GCC_VIDEO_AXI1_CLK 43 +#define NW_GCC_VIDEO_XO_CLK 44 + +/* NW_GCC power domains */ + +/* NW_GCC resets */ +#define NW_GCC_CAMERA_BCR 0 +#define NW_GCC_DISPLAY_0_BCR 1 +#define NW_GCC_DISPLAY_1_BCR 2 +#define NW_GCC_DPRX0_BCR 3 +#define NW_GCC_DPRX1_BCR 4 +#define NW_GCC_EVA_BCR 5 +#define NW_GCC_GPU_2_BCR 6 +#define NW_GCC_GPU_BCR 7 +#define NW_GCC_VIDEO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h new file mode 100644 index 000000000000..f0f7422af692 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-segcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H + +/* SE_GCC clocks */ +#define SE_GCC_EEE_EMAC0_CLK 0 +#define SE_GCC_EEE_EMAC0_CLK_SRC 1 +#define SE_GCC_EEE_EMAC1_CLK 2 +#define SE_GCC_EEE_EMAC1_CLK_SRC 3 +#define SE_GCC_EMAC0_AXI_CLK 4 +#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5 +#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6 +#define SE_GCC_EMAC0_PHY_AUX_CLK 7 +#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8 +#define SE_GCC_EMAC0_PTP_CLK 9 +#define SE_GCC_EMAC0_PTP_CLK_SRC 10 +#define SE_GCC_EMAC0_RGMII_CLK 11 +#define SE_GCC_EMAC0_RGMII_CLK_SRC 12 +#define SE_GCC_EMAC0_RPCS_RX_CLK 13 +#define SE_GCC_EMAC0_RPCS_TX_CLK 14 +#define SE_GCC_EMAC0_XGXS_RX_CLK 15 +#define SE_GCC_EMAC0_XGXS_TX_CLK 16 +#define SE_GCC_EMAC1_AXI_CLK 17 +#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18 +#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19 +#define SE_GCC_EMAC1_PHY_AUX_CLK 20 +#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21 +#define SE_GCC_EMAC1_PTP_CLK 22 +#define SE_GCC_EMAC1_PTP_CLK_SRC 23 +#define SE_GCC_EMAC1_RGMII_CLK 24 +#define SE_GCC_EMAC1_RGMII_CLK_SRC 25 +#define SE_GCC_EMAC1_RPCS_RX_CLK 26 +#define SE_GCC_EMAC1_RPCS_TX_CLK 27 +#define SE_GCC_EMAC1_XGXS_RX_CLK 28 +#define SE_GCC_EMAC1_XGXS_TX_CLK 29 +#define SE_GCC_FRQ_MEASURE_REF_CLK 30 +#define SE_GCC_GP1_CLK 31 +#define SE_GCC_GP1_CLK_SRC 32 +#define SE_GCC_GP2_CLK 33 +#define SE_GCC_GP2_CLK_SRC 34 +#define SE_GCC_GPLL0 35 +#define SE_GCC_GPLL0_OUT_EVEN 36 +#define SE_GCC_GPLL2 37 +#define SE_GCC_GPLL4 38 +#define SE_GCC_GPLL5 39 +#define SE_GCC_MMU_2_TCU_VOTE_CLK 40 +#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41 +#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42 +#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43 +#define SE_GCC_QUPV3_WRAP0_S0_CLK 44 +#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45 +#define SE_GCC_QUPV3_WRAP0_S1_CLK 46 +#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47 +#define SE_GCC_QUPV3_WRAP0_S2_CLK 48 +#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49 +#define SE_GCC_QUPV3_WRAP0_S3_CLK 50 +#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51 +#define SE_GCC_QUPV3_WRAP0_S4_CLK 52 +#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53 +#define SE_GCC_QUPV3_WRAP0_S5_CLK 54 +#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55 +#define SE_GCC_QUPV3_WRAP0_S6_CLK 56 +#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57 +#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58 +#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59 +#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60 +#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61 +#define SE_GCC_QUPV3_WRAP1_S0_CLK 62 +#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63 +#define SE_GCC_QUPV3_WRAP1_S1_CLK 64 +#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65 +#define SE_GCC_QUPV3_WRAP1_S2_CLK 66 +#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67 +#define SE_GCC_QUPV3_WRAP1_S3_CLK 68 +#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69 +#define SE_GCC_QUPV3_WRAP1_S4_CLK 70 +#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71 +#define SE_GCC_QUPV3_WRAP1_S5_CLK 72 +#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73 +#define SE_GCC_QUPV3_WRAP1_S6_CLK 74 +#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75 +#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76 + +/* SE_GCC power domains */ +#define SE_GCC_EMAC0_GDSC 0 +#define SE_GCC_EMAC1_GDSC 1 + +/* SE_GCC resets */ +#define SE_GCC_EMAC0_BCR 0 +#define SE_GCC_EMAC1_BCR 1 +#define SE_GCC_QUPV3_WRAPPER_0_BCR 2 +#define SE_GCC_QUPV3_WRAPPER_1_BCR 3 + +#endif -- cgit v1.2.3