From 8bf478163e69e42973c7070179a11815139e5bf0 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Tue, 21 Jul 2015 10:41:21 +0200 Subject: iommu/vt-d: Split up iommu->domains array This array is indexed by the domain-id and contains the pointers to the domains attached to this iommu. Modern systems support 65536 domain ids, so that this array has a size of 512kb, per iommu. This is a huge waste of space, as the array is usually sparsely populated. This patch makes the array two-dimensional and allocates the memory for the domain pointers on-demand. Signed-off-by: Joerg Roedel --- include/linux/intel-iommu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index d9a366d24e3b..6240063bdcac 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -344,7 +344,7 @@ struct intel_iommu { #ifdef CONFIG_INTEL_IOMMU unsigned long *domain_ids; /* bitmap of domains */ - struct dmar_domain **domains; /* ptr to domains */ + struct dmar_domain ***domains; /* ptr to domains */ spinlock_t lock; /* protect context, domain ids */ struct root_entry *root_entry; /* virtual address */ -- cgit v1.2.3 From 4b3c7d10765403ab19628fb7d530b8ce1c50b81d Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 27 Jul 2015 13:29:36 +0100 Subject: iommu/tegra-smmu: Move flush_dcache to tegra-smmu.c Drivers should not be using __cpuc_* functions nor outer_cache_flush() directly. This change partly cleans up tegra-smmu.c. The only difference between cache handling of the tegra variants is Denver, which omits the call to outer_cache_flush(). This is due to Denver being an ARM64 CPU, and the ARM64 architecture does not provide this function. (This, in itself, is a good reason why these should not be used.) Signed-off-by: Russell King [treding@nvidia.com: fix build failure on 64-bit ARM] Signed-off-by: Thierry Reding --- include/soc/tegra/mc.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include') diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1ab2813273cd..d6c3190ec852 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -51,11 +51,6 @@ struct tegra_smmu_swgroup { unsigned int reg; }; -struct tegra_smmu_ops { - void (*flush_dcache)(struct page *page, unsigned long offset, - size_t size); -}; - struct tegra_smmu_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -67,8 +62,6 @@ struct tegra_smmu_soc { bool supports_request_limit; unsigned int num_asids; - - const struct tegra_smmu_ops *ops; }; struct tegra_mc; -- cgit v1.2.3 From 11cec15bf3fb498206ef63b1fa26c27689e02d0e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2015 14:20:31 +0200 Subject: iommu/tegra-smmu: Parameterize number of TLB lines The number of TLB lines was increased from 16 on Tegra30 to 32 on Tegra114 and later. Parameterize the value so that the initial default can be set accordingly. On Tegra30, initializing the value to 32 would effectively disable the TLB and hence cause massive latencies for memory accesses translated through the SMMU. This is especially noticeable for isochronuous clients such as display, whose FIFOs would continuously underrun. Fixes: 891846516317 ("memory: Add NVIDIA Tegra memory controller support") Signed-off-by: Thierry Reding --- include/soc/tegra/mc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d6c3190ec852..8cb3a7ecd6f8 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -61,6 +61,7 @@ struct tegra_smmu_soc { bool supports_round_robin_arbitration; bool supports_request_limit; + unsigned int num_tlb_lines; unsigned int num_asids; }; -- cgit v1.2.3