From 9dab4aed8913ef176779cd5616b5bd36275ddf35 Mon Sep 17 00:00:00 2001 From: Erik Lilliebjerg Date: Thu, 16 Feb 2012 17:59:32 -0700 Subject: media: common camera headers Bug 852480 Change-Id: If7d74d81f29d325846f8744c957f007e9c0f153a Signed-off-by: Erik Lilliebjerg Reviewed-on: http://git-master/r/84419 Reviewed-by: Bharat Nihalani --- include/media/nvc.h | 56 +++++++++++++- include/media/nvc_image.h | 191 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 243 insertions(+), 4 deletions(-) create mode 100644 include/media/nvc_image.h (limited to 'include') diff --git a/include/media/nvc.h b/include/media/nvc.h index c1be3473ecf9..7fd4bf2da6ac 100644 --- a/include/media/nvc.h +++ b/include/media/nvc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011 NVIDIA Corporation. +/* Copyright (C) 2012 NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -112,7 +112,7 @@ struct nvc_param { * algorithms. * The PM actions: * _PWR_ERR = Non-valid state. - * _PWR_OFF_DELAYED = _PWR_OFF is called after a period of time. + * _PWR_OFF_FORCE = _PWR_OFF is forced regardless of standby mechanisms. * _PWR_OFF = Device, regulators, clocks, etc is turned off. The longest * transition time to _PWR_ON is from this state. * _PWR_STDBY_OFF = Device is useless but powered. No communication possible. @@ -122,11 +122,10 @@ struct nvc_param { * _PWR_COMM = Device is powered enough to communicate with the device. * _PWR_ON = Device is at full power with active output. * - * The kernel drivers treat these calls as guaranteed level of service. + * The kernel drivers treat these calls as Guaranteed Level Of Service. */ #define NVC_PWR_ERR 0 -#define NVC_PWR_OFF_DELAYED 1 /* obsolete - never used */ #define NVC_PWR_OFF_FORCE 1 #define NVC_PWR_OFF 2 #define NVC_PWR_STDBY_OFF 3 @@ -140,6 +139,55 @@ struct nvc_regulator { const char *vreg_name; }; +/* The GPIO mechanism uses the _gpio_type in the device's header file as a key + * to define all the possible GPIO's the device will need. The key is used to + * combine the GPIO's defined in the platform board file using the + * nvc_gpio_pdata structure with the nvc_gpio structure in the nvc kernel + * driver. + */ +struct nvc_gpio_pdata { + /* use a _gpio_type enum from the device's header file */ + unsigned gpio_type; + /* the GPIO system number */ + unsigned gpio; + /* init_en is typically set to true for all GPIO's used by the driver. + * However, some GPIO's are used by multiple drivers (CSI MUX, reset, + * etc.). In this case, this is set true for only one of the drivers + * that uses the GPIO and false for the others. If the platform board + * file initializes the GPIO, then this is false for all of the drivers + * using the GPIO. + */ + bool init_en; + /* this defines the assert level for the general purpose GPIO's + * (_GPIO_TYPE_GPx, etc.). The _GPIO_TYPE_GPx can be used for a GPIO + * that the driver doesn't know about but is needed in order for the + * device to work (CSI select, regulator, etc.). The driver will + * blindly assert the GPIO when the device is operational and deassert + * when the device is turned off. + */ + bool active_high; +}; + +struct nvc_gpio_init { + /* key to match in nvc_gpio_pdata */ + unsigned gpio_type; + /* same as in gpio.h */ + unsigned long flags; + /* same as in gpio.h */ + const char *label; + /* used instead of nvc_gpio_pdata.active_high if use_flags true */ + bool active_high; + /* false if nvc_gpio_pdata.active_high used else flags is used */ + bool use_flags; +}; + +struct nvc_gpio { + unsigned gpio; /* system GPIO number */ + bool own; /* gets set if driver initializes */ + bool active_high; /* used for GP GPIOs */ + bool flag; /* scratch flag for driver implementation */ +}; + #endif /* __KERNEL__ */ #endif /* __NVC_H__ */ diff --git a/include/media/nvc_image.h b/include/media/nvc_image.h new file mode 100644 index 000000000000..f4af497c2ad0 --- /dev/null +++ b/include/media/nvc_image.h @@ -0,0 +1,191 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_IMAGE_H__ +#define __NVC_IMAGE_H__ + +#include + +#define NVC_IMAGER_API_CAPS_VER 2 +#define NVC_IMAGER_API_STATIC_VER 1 +#define NVC_IMAGER_API_DYNAMIC_VER 1 +#define NVC_IMAGER_API_BAYER_VER 1 + +#define NVC_IMAGER_PARAM_BAYER 0xE100 + +#define NVC_IMAGER_TEST_NONE 0 +#define NVC_IMAGER_TEST_COLORBARS 1 +#define NVC_IMAGER_TEST_CHECKERBOARD 2 +#define NVC_IMAGER_TEST_WALKING1S 3 + +#define NVC_IMAGER_CROPMODE_NONE 1 +#define NVC_IMAGER_CROPMODE_PARTIAL 2 + +#define NVC_IMAGER_TYPE_HUH 0 +#define NVC_IMAGER_TYPE_RAW 1 +#define NVC_IMAGER_TYPE_SOC 2 + +#define NVC_IMAGER_INTERFACE_MIPI_A 3 +#define NVC_IMAGER_INTERFACE_MIPI_B 4 +#define NVC_IMAGER_INTERFACE_MIPI_AB 5 + +#define NVC_IMAGER_IDENTIFIER_MAX 32 +#define NVC_IMAGER_FORMAT_MAX 4 +#define NVC_IMAGER_CLOCK_PROFILE_MAX 2 +#define NVC_IMAGER_CAPABILITIES_END ((0x3434 << 16) | \ + NVC_IMAGER_API_CAPS_VER) + +#define NVC_IMAGER_INT2FLOAT_DIVISOR 1000 + +#define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF)) +#define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF)) + + +struct nvc_imager_static_nvc { + __u32 api_version; + __u32 sensor_type; + __u32 sensor_id; + __u32 sensor_id_minor; + __u32 focal_len; + __u32 max_aperture; + __u32 fnumber; + __u32 view_angle_h; + __u32 view_angle_v; + __u32 stereo_cap; + __u32 res_chg_wait_time; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_dynamic_nvc { + __u32 api_version; + __s32 region_start_x; + __s32 region_start_y; + __u32 x_scale; + __u32 y_scale; + __u32 bracket_caps; + __u32 flush_count; + __u32 init_intra_frame_skip; + __u32 ss_intra_frame_skip; + __u32 ss_frame_number; + __u32 coarse_time; + __u32 max_coarse_diff; + __u32 min_exposure_course; + __u32 max_exposure_course; + __u32 diff_integration_time; + __u32 line_length; + __u32 frame_length; + __u32 min_frame_length; + __u32 max_frame_length; + __u32 min_gain; + __u32 max_gain; + __u32 inherent_gain; + __u32 inherent_gain_bin_en; + __u8 support_bin_control; + __u8 support_fast_mode; + __u8 align2; + __u8 align3; + __u32 pll_mult; + __u32 pll_div; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_bayer { + __u32 api_version; + __s32 res_x; + __s32 res_y; + __u32 frame_length; + __u32 coarse_time; + __u32 gain; + __u8 bin_en; + __u8 align1; + __u8 align2; + __u8 align3; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_mode { + __s32 res_x; + __s32 res_y; + __s32 active_start_x; + __s32 active_stary_y; + __u32 peak_frame_rate; + __u32 pixel_aspect_ratio; + __u32 pll_multiplier; + __u32 crop_mode; +} __packed; + +struct nvc_imager_dnvc { + __s32 res_x; + __s32 res_y; + struct nvc_imager_mode *p_mode; + struct nvc_imager_dynamic_nvc *p_dnvc; +} __packed; + +struct nvc_imager_mode_list { + struct nvc_imager_mode *p_modes; + __u32 *p_num_mode; +} __packed; + +struct nvc_clock_profile { + __u32 external_clock_khz; + __u32 clock_multiplier; +} __packed; + +struct nvc_imager_cap { + char identifier[NVC_IMAGER_IDENTIFIER_MAX]; + __u32 sensor_nvc_interface; + __u32 pixel_types[NVC_IMAGER_FORMAT_MAX]; + __u32 orientation; + __u32 direction; + __u32 initial_clock_rate_khz; + struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX]; + __u32 h_sync_edge; + __u32 v_sync_edge; + __u32 mclk_on_vgp0; + __u8 csi_port; + __u8 data_lanes; + __u8 virtual_channel_id; + __u8 discontinuous_clk_mode; + __u8 cil_threshold_settle; + __u8 align1; + __u8 align2; + __u8 align3; + __s32 min_blank_time_width; + __s32 min_blank_time_height; + __u32 preferred_mode_index; + __u64 focuser_guid; + __u64 torch_guid; + __u32 cap_end; + __u32 align4; +} __packed; + +#define NVC_IOCTL_CAPS_RD _IOWR('o', 106, struct nvc_imager_cap) +#define NVC_IOCTL_MODE_WR _IOW('o', 107, struct nvc_imager_bayer) +#define NVC_IOCTL_MODE_RD _IOWR('o', 108, struct nvc_imager_mode_list) +#define NVC_IOCTL_STATIC_RD _IOWR('o', 109, struct nvc_imager_static_nvc) +#define NVC_IOCTL_DYNAMIC_RD _IOWR('o', 110, struct nvc_imager_dnvc) + +#endif /* __NVC_IMAGE_H__ */ -- cgit v1.2.3