From e2797ad31fb40f4ff59ebc4314d6f000d713bad9 Mon Sep 17 00:00:00 2001 From: Krzysztof Wilczynski Date: Tue, 27 Aug 2019 11:49:49 +0200 Subject: PCI/ACPI: Rename _HPX structs from hpp_* to hpx_* The names of the hpp_type0, hpp_type1 and hpp_type2 structs suggest that they're related to _HPP, when in fact they're related to _HPX. The struct hpp_type0 denotes an _HPX Type 0 setting record that supersedes the _HPP setting record, and it has been used interchangeably for _HPP as per the ACPI specification (see version 6.3, section 6.2.9.1) which states that it should be applied to PCI, PCI-X and PCI Express devices, with settings being ignored if they are not applicable. Rename them to hpx_type0, hpx_type1 and hpx_type2 to reflect their relation to _HPX rather than _HPP. Link: https://lore.kernel.org/r/20190827094951.10613-2-kw@linux.com Signed-off-by: Krzysztof Wilczynski Signed-off-by: Bjorn Helgaas --- include/linux/pci_hotplug.h | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index f694eb2ca978..247a49ee27b3 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -86,25 +86,25 @@ void pci_hp_deregister(struct hotplug_slot *slot); #define pci_hp_initialize(slot, bus, nr, name) \ __pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME) -/* PCI Setting Record (Type 0) */ -struct hpp_type0 { - u32 revision; - u8 cache_line_size; - u8 latency_timer; +/* _HPX PCI Setting Record (Type 0); same as _HPP */ +struct hpx_type0 { + u32 revision; /* Not present in _HPP */ + u8 cache_line_size; /* Not applicable to PCIe */ + u8 latency_timer; /* Not applicable to PCIe */ u8 enable_serr; u8 enable_perr; }; -/* PCI-X Setting Record (Type 1) */ -struct hpp_type1 { +/* _HPX PCI-X Setting Record (Type 1) */ +struct hpx_type1 { u32 revision; u8 max_mem_read; u8 avg_max_split; u16 tot_max_split; }; -/* PCI Express Setting Record (Type 2) */ -struct hpp_type2 { +/* _HPX PCI Express Setting Record (Type 2) */ +struct hpx_type2 { u32 revision; u32 unc_err_mask_and; u32 unc_err_mask_or; @@ -124,9 +124,7 @@ struct hpp_type2 { u32 sec_unc_err_mask_or; }; -/* - * _HPX PCI Express Setting Record (Type 3) - */ +/* _HPX PCI Express Setting Record (Type 3) */ struct hpx_type3 { u16 device_type; u16 function_type; @@ -145,10 +143,10 @@ struct hpx_type3 { }; struct hotplug_program_ops { - void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp); - void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp); - void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp); - void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp); + void (*program_type0)(struct pci_dev *dev, struct hpx_type0 *hpx); + void (*program_type1)(struct pci_dev *dev, struct hpx_type1 *hpx); + void (*program_type2)(struct pci_dev *dev, struct hpx_type2 *hpx); + void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpx); }; enum hpx_type3_dev_type { -- cgit v1.2.3 From 8c3aac6e1b6146ce771b1cabd78e593136d3e5f2 Mon Sep 17 00:00:00 2001 From: Krzysztof Wilczynski Date: Tue, 27 Aug 2019 11:49:50 +0200 Subject: PCI/ACPI: Move _HPP & _HPX functions to pci-acpi.c Move program_hpx_type0(), program_hpx_type1(), etc., and enums hpx_type3_dev_type, hpx_type3_fn_type and hpx_type3_cfg_loc to drivers/pci/pci-acpi.c as these functions and enums are ACPI-specific. Move structs hpx_type0, hpx_type1, hpx_type2 and hpx_type3 to drivers/pci/pci.h as these are shared between drivers/pci/pci-acpi.c and drivers/pci/probe.c. Link: https://lore.kernel.org/r/20190827094951.10613-3-kw@linux.com Signed-off-by: Krzysztof Wilczynski Signed-off-by: Bjorn Helgaas --- include/linux/pci_hotplug.h | 98 --------------------------------------------- 1 file changed, 98 deletions(-) (limited to 'include') diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index 247a49ee27b3..b482e42d7153 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -86,112 +86,14 @@ void pci_hp_deregister(struct hotplug_slot *slot); #define pci_hp_initialize(slot, bus, nr, name) \ __pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME) -/* _HPX PCI Setting Record (Type 0); same as _HPP */ -struct hpx_type0 { - u32 revision; /* Not present in _HPP */ - u8 cache_line_size; /* Not applicable to PCIe */ - u8 latency_timer; /* Not applicable to PCIe */ - u8 enable_serr; - u8 enable_perr; -}; - -/* _HPX PCI-X Setting Record (Type 1) */ -struct hpx_type1 { - u32 revision; - u8 max_mem_read; - u8 avg_max_split; - u16 tot_max_split; -}; - -/* _HPX PCI Express Setting Record (Type 2) */ -struct hpx_type2 { - u32 revision; - u32 unc_err_mask_and; - u32 unc_err_mask_or; - u32 unc_err_sever_and; - u32 unc_err_sever_or; - u32 cor_err_mask_and; - u32 cor_err_mask_or; - u32 adv_err_cap_and; - u32 adv_err_cap_or; - u16 pci_exp_devctl_and; - u16 pci_exp_devctl_or; - u16 pci_exp_lnkctl_and; - u16 pci_exp_lnkctl_or; - u32 sec_unc_err_sever_and; - u32 sec_unc_err_sever_or; - u32 sec_unc_err_mask_and; - u32 sec_unc_err_mask_or; -}; - -/* _HPX PCI Express Setting Record (Type 3) */ -struct hpx_type3 { - u16 device_type; - u16 function_type; - u16 config_space_location; - u16 pci_exp_cap_id; - u16 pci_exp_cap_ver; - u16 pci_exp_vendor_id; - u16 dvsec_id; - u16 dvsec_rev; - u16 match_offset; - u32 match_mask_and; - u32 match_value; - u16 reg_offset; - u32 reg_mask_and; - u32 reg_mask_or; -}; - -struct hotplug_program_ops { - void (*program_type0)(struct pci_dev *dev, struct hpx_type0 *hpx); - void (*program_type1)(struct pci_dev *dev, struct hpx_type1 *hpx); - void (*program_type2)(struct pci_dev *dev, struct hpx_type2 *hpx); - void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpx); -}; - -enum hpx_type3_dev_type { - HPX_TYPE_ENDPOINT = BIT(0), - HPX_TYPE_LEG_END = BIT(1), - HPX_TYPE_RC_END = BIT(2), - HPX_TYPE_RC_EC = BIT(3), - HPX_TYPE_ROOT_PORT = BIT(4), - HPX_TYPE_UPSTREAM = BIT(5), - HPX_TYPE_DOWNSTREAM = BIT(6), - HPX_TYPE_PCI_BRIDGE = BIT(7), - HPX_TYPE_PCIE_BRIDGE = BIT(8), -}; - -enum hpx_type3_fn_type { - HPX_FN_NORMAL = BIT(0), - HPX_FN_SRIOV_PHYS = BIT(1), - HPX_FN_SRIOV_VIRT = BIT(2), -}; - -enum hpx_type3_cfg_loc { - HPX_CFG_PCICFG = 0, - HPX_CFG_PCIE_CAP = 1, - HPX_CFG_PCIE_CAP_EXT = 2, - HPX_CFG_VEND_CAP = 3, - HPX_CFG_DVSEC = 4, - HPX_CFG_MAX, -}; - #ifdef CONFIG_ACPI #include -int pci_acpi_program_hp_params(struct pci_dev *dev, - const struct hotplug_program_ops *hp_ops); bool pciehp_is_native(struct pci_dev *bridge); int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge); bool shpchp_is_native(struct pci_dev *bridge); int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle); int acpi_pci_detect_ejectable(acpi_handle handle); #else -static inline int pci_acpi_program_hp_params(struct pci_dev *dev, - const struct hotplug_program_ops *hp_ops) -{ - return -ENODEV; -} - static inline int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge) { return 0; -- cgit v1.2.3 From ca78410403dd64ac0ee0e3cc8646b38335271bfd Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 22 Aug 2019 11:55:53 +0300 Subject: PCI: Get rid of dev->has_secondary_link flag In some systems, the Device/Port Type in the PCI Express Capabilities register incorrectly identifies upstream ports as downstream ports. d0751b98dfa3 ("PCI: Add dev->has_secondary_link to track downstream PCIe links") addressed this by adding pci_dev.has_secondary_link, which is set for downstream ports. But this is confusing because pci_pcie_type() sometimes gives the wrong answer, and it's not obvious that we should use pci_dev.has_secondary_link instead. Reduce the confusion by correcting the type of the port itself so that pci_pcie_type() returns the actual type regardless of what the Device/Port Type register claims it is. Update the users to call pci_pcie_type() and pcie_downstream_port() accordingly, and remove pci_dev.has_secondary_link completely. Link: https://lore.kernel.org/linux-pci/20190703133953.GK128603@google.com/ Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20190822085553.62697-2-mika.westerberg@linux.intel.com Signed-off-by: Mika Westerberg Signed-off-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko --- include/linux/pci.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index 9e700d9f9f28..0153ede227e5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -418,7 +418,6 @@ struct pci_dev { unsigned int broken_intx_masking:1; /* INTx masking can't be used */ unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ unsigned int irq_managed:1; - unsigned int has_secondary_link:1; unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ unsigned int is_probed:1; /* Device probing in progress */ unsigned int link_active_reporting:1;/* Device capable of reporting link active */ -- cgit v1.2.3