From b5d93fa1b7ac3f1173dfb9ba32fe6143b22fddf7 Mon Sep 17 00:00:00 2001 From: Ira Weiny Date: Sun, 11 Oct 2026 07:54:53 +0900 Subject: cxl/mem: Read dynamic capacity configuration from the device Devices which support Dynamic Capacity (DC) are configured via mailbox commands. CXL r4.0 section 9.13.3 describes the use of the Get DC Configuration command in order to obtain DCD partition characteristics. Implement the DC mailbox commands as specified in CXL 4.0 section 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration information. Disable DCD if an invalid configuration is found. Initial enablement for Linux only supports one dynamic capacity partition. Read all the partitions the device reports but validate only the first, and configure it as 'dynamic ram'. The specification requires that volatile capacity starts at DPA 0 and pmem starts at the DPA immediately following it, but DC partitions only need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1 Table 8-347. So a device could leave a gap between ram/pmem (static) capacity and its first DC partition, or between one DC partition and the next. However, Linux chooses not to support gaps between static and dynamic capacity, and requires the first DC partition to begin at the DPA immediately following static capacity. Based on an original patch by Navneet Singh. [ dj: Fixed up output line wrapping. (Jonathan) ] [ dj: Fixed up cleanup declaration. (Jonathan) ] [ dj: Remove start_partition in cxl_get_dc_config. (Jonathan) ] Signed-off-by: Ira Weiny Co-developed-by: Anisa Su Signed-off-by: Anisa Su Tested-by: Wonjae Lee Tested-by: Junhee Park Tested-by: Heesoo Kim Reviewed-by: Jonathan Cameron Link: https://patch.msgid.link/20261010225852.10727-3-anisa.su@samsung.com Signed-off-by: Dave Jiang --- include/cxl/cxl.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 802b143de83d..e07360849344 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -133,6 +133,7 @@ struct cxl_dpa_perf { enum cxl_partition_mode { CXL_PARTMODE_RAM, CXL_PARTMODE_PMEM, + CXL_PARTMODE_DYNAMIC_RAM, }; /** @@ -147,7 +148,7 @@ struct cxl_dpa_partition { enum cxl_partition_mode mode; }; -#define CXL_NR_PARTITIONS_MAX 2 +#define CXL_NR_PARTITIONS_MAX 3 /** * struct cxl_dev_state - The driver device state -- cgit v1.2.3 From a7d2b5e9c4f51a17912c1a4470a24e038c944067 Mon Sep 17 00:00:00 2001 From: Ira Weiny Date: Sun, 11 Oct 2026 07:54:54 +0900 Subject: cxl/cdat: Gather DSMAS data for DCD partitions Additional DCD partition (AKA region) information is contained in the DSMAS CDAT tables, including performance, shareable and read-only attributes. Match DCD partitions with DSMAS tables and store the meta data. A DCD shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3), so if the CDAT is absent, fails to parse, or has no entry matching the DC partition, disable DCD rather than run with unknown attributes. DSLBIS is optional, but cxl_cdat_endpoint_process() treated zero DSLBIS entries as a parse failure, which would now disable DCD on a device with a valid DSMAS. Accept an empty DSLBIS, and skip DSMAS entries with no DSLBIS coordinates. Signed-off-by: Ira Weiny Co-developed-by: Anisa Su Signed-off-by: Anisa Su Tested-by: Wonjae Lee Tested-by: Junhee Park Tested-by: Heesoo Kim Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron Link: https://patch.msgid.link/20261010225852.10727-4-anisa.su@samsung.com Signed-off-by: Dave Jiang --- include/cxl/cxl.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index e07360849344..728decda57fd 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -141,11 +141,17 @@ enum cxl_partition_mode { * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res) * @perf: performance attributes of the partition from CDAT * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic... + * @handle: DSMAS handle that represents this partition + * @shareable: Is the partition shareable (from its CDAT DSMAS entry) + * @read_only: Is the partition read-only (from its CDAT DSMAS entry) */ struct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; + u8 handle; + bool shareable; + bool read_only; }; #define CXL_NR_PARTITIONS_MAX 3 -- cgit v1.2.3 From c801107605f39b5a8632fbc835e0da65a6fb6b51 Mon Sep 17 00:00:00 2001 From: Ira Weiny Date: Sun, 11 Oct 2026 07:54:58 +0900 Subject: cxl/core: Enforce partition order/simplify partition calls Device partitions share one flat DPA space in a fixed order: static volatile capacity at DPA 0, static persistent capacity immediately above it, and dynamic capacity above all static capacity. The static pair is mandated by CXL r4.0 8.2.10.9.2.1 "Get Partition Info", Table 8-310: the device "shall provide this volatile capacity starting at DPA 0" and "shall provide this persistent capacity starting at the DPA immediately following the volatile capacity". Dynamic capacity has no such rule. Table 8-347 only requires the region base to be 256M aligned, so placing it directly above static capacity is a Linux requirement, enforced by cxl_configure_dcd(). DPA 0 end +---------------+---------------+---------------------------+ | ram | pmem | dynamic_ram_1 | +---------------+---------------+---------------------------+ part[0] part[1] part[2] Signed-off-by: Ira Weiny Co-developed-by: Anisa Su Signed-off-by: Anisa Su Tested-by: Wonjae Lee Tested-by: Junhee Park Tested-by: Heesoo Kim Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20261010225852.10727-8-anisa.su@samsung.com Signed-off-by: Dave Jiang --- include/cxl/cxl.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'include') diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 728decda57fd..1c04a7823f64 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -130,6 +130,26 @@ struct cxl_dpa_perf { int qos_class; }; +/* + * Partitions share one flat DPA space in a fixed order: + * + * DPA 0 end + * +---------------+---------------+---------------------------+ + * | ram | pmem | dynamic_ram_1 | + * +---------------+---------------+---------------------------+ + * part[0] part[1] part[2] + * + * The static ram and pmem partition order is mandated by CXL r4.0 + * 8.2.10.9.2.1 "Get Partition Info" (opcode 4100h), Table 8-310: volatile + * capacity starts at DPA 0 and persistent capacity starts at the DPA + * immediately following it. A dynamic partition has no such + * requirement -- 8.2.10.9.9.1 "Get Dynamic Capacity Configuration" + * (opcode 4800h), Table 8-347, only requires the DC Region Base to be + * 256MB aligned -- but Linux follows that precedent and requires it to + * start at the DPA immediately following static capacity: after pmem, + * after ram on a device with no pmem, or at DPA 0 on a device with no + * static capacity at all. cxl_configure_dcd() enforces it. + */ enum cxl_partition_mode { CXL_PARTMODE_RAM, CXL_PARTMODE_PMEM, -- cgit v1.2.3