From 97bb163197f3dc3405af90b5159e0f6b8a302586 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 11 Dec 2012 15:36:08 +0800 Subject: ENGR00216076-2: DCU: Update DCU driver for PM and blending issue Fix layers blending and reinitialization issue for DCU driver. Update power management part for DCU driver. Signed-off-by: Alison Wang --- include/linux/Kbuild | 1 + include/linux/mvf-fb.h | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 include/linux/mvf-fb.h (limited to 'include') diff --git a/include/linux/Kbuild b/include/linux/Kbuild index c65d1b9eb546..947d36f054e5 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -35,6 +35,7 @@ header-y += mxc_si4702.h header-y += mxc_sim_interface.h header-y += mxc_v4l2.h header-y += mxcfb.h +header-y += mvf-fb.h header-y += pmic_adc.h header-y += pmic_battery.h header-y += pmic_external.h diff --git a/include/linux/mvf-fb.h b/include/linux/mvf-fb.h new file mode 100644 index 000000000000..836767697d76 --- /dev/null +++ b/include/linux/mvf-fb.h @@ -0,0 +1,74 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Freescale DCU Frame Buffer device driver ioctls + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MVF_FB_H__ +#define __MVF_FB_H__ + +#include + +/* ioctls */ + +#define MFB_SET_ALPHA 0x80014d00 +#define MFB_GET_ALPHA 0x40014d00 +#define MFB_SET_LAYER 0x80084d04 +#define MFB_GET_LAYER 0x40084d04 + +#define FBIOGET_GWINFO 0x46E0 +#define FBIOPUT_GWINFO 0x46E1 + +#ifndef u32 +#define u32 unsigned int +#endif + +struct mfb_alpha { + int enable; + int alpha; +}; + +struct layer_display_offset { + int x_layer_d; + int y_layer_d; +}; + +/* + * These are the fields of control descriptor for every layer + */ +struct dcu_layer_desc { + u32 layer_num; + u32 width; + u32 height; + u32 posx; + u32 posy; + u32 addr; + u32 blend; + u32 chroma_key_en; + u32 lut_offset; + u32 rle_en; + u32 bpp; + u32 trans; + u32 safety_en; + u32 data_sel_clut; + u32 tile_en; + u32 en; + u32 ck_r_min; + u32 ck_r_max; + u32 ck_g_min; + u32 ck_g_max; + u32 ck_b_min; + u32 ck_b_max; + u32 tile_width; + u32 tile_height; + u32 trans_fgcolor; + u32 trans_bgcolor; +} __packed; + +#endif -- cgit v1.2.3 From 6dedc932b4d43948145f8d3a0e56f7b3e7b65354 Mon Sep 17 00:00:00 2001 From: Jingchang Lu Date: Wed, 5 Dec 2012 13:19:53 +0800 Subject: ENGR00216087-1: ASRC support for Vybrid The ASRC driver supports stereo audio streams resample, the ASRCK1 serial clock using audio external clock source can not support 44.1K sample rate due to divider and prescaler restriction. Signed-off-by: Jingchang Lu --- include/linux/mxc_asrc.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/linux/mxc_asrc.h b/include/linux/mxc_asrc.h index f0136f0502f0..d860dccb5374 100644 --- a/include/linux/mxc_asrc.h +++ b/include/linux/mxc_asrc.h @@ -47,13 +47,17 @@ enum asrc_pair_index { enum asrc_inclk { INCLK_NONE = 0x03, INCLK_ESAI_RX = 0x00, + INCLK_SSI0_RX = 0x06, INCLK_SSI1_RX = 0x01, INCLK_SSI2_RX = 0x02, + INCLK_SSI3_RX = 0x07, INCLK_SPDIF_RX = 0x04, INCLK_MLB_CLK = 0x05, INCLK_ESAI_TX = 0x08, + INCLK_SSI0_TX = 0xd, INCLK_SSI1_TX = 0x09, INCLK_SSI2_TX = 0x0a, + INCLK_SSI3_TX = 0x0b, INCLK_SPDIF_TX = 0x0c, INCLK_ASRCK1_CLK = 0x0f, }; @@ -61,13 +65,17 @@ enum asrc_inclk { enum asrc_outclk { OUTCLK_NONE = 0x03, OUTCLK_ESAI_TX = 0x00, + OUTCLK_SSI0_TX = 0x06, OUTCLK_SSI1_TX = 0x01, OUTCLK_SSI2_TX = 0x02, + OUTCLK_SSI3_TX = 0x0d, OUTCLK_SPDIF_TX = 0x04, OUTCLK_MLB_CLK = 0x05, OUTCLK_ESAI_RX = 0x08, + OUTCLK_SSI0_RX = 0x07, OUTCLK_SSI1_RX = 0x09, OUTCLK_SSI2_RX = 0x0a, + OUTCLK_SSI3_RX = 0x0b, OUTCLK_SPDIF_RX = 0x0c, OUTCLK_ASRCK1_CLK = 0x0f, }; @@ -162,6 +170,15 @@ enum asrc_error_status { #define ASRC_ASRIDRLC_REG 0x94 #define ASRC_ASR76K_REG 0x98 #define ASRC_ASR56K_REG 0x9C +#define ASRC_ASRMCRA_REG 0xA0 +#define ASRC_ASRFSTA_REG 0xA4 +#define ASRC_ASRMCRB_REG 0xA8 +#define ASRC_ASRFSTB_REG 0xAC +#define ASRC_ASRMCRC_REG 0xB0 +#define ASRC_ASRFSTC_REG 0xB4 +#define ASRC_ASRMCR1A_REG 0xC0 +#define ASRC_ASRMCR1B_REG 0xC4 +#define ASRC_ASRMCR1C_REG 0xC8 struct dma_block { unsigned int index; @@ -183,8 +200,13 @@ struct asrc_pair_params { unsigned int output_counter; unsigned int input_queue_empty; unsigned int output_queue_empty; +#ifdef CONFIG_ARCH_MVF + unsigned long input_dma_channel; + unsigned long output_dma_channel; +#else struct dma_chan *input_dma_channel; struct dma_chan *output_dma_channel; +#endif unsigned int input_buffer_size; unsigned int output_buffer_size; unsigned int buffer_num; -- cgit v1.2.3 From b358081d3db11e4f4582bea7658b93a7eef539d3 Mon Sep 17 00:00:00 2001 From: Wang Xiaojun Date: Mon, 10 Dec 2012 18:05:18 +0800 Subject: ENGR00181365-2: ADC: Add driver support for ADC Vybrid Add driver support for ADC Vybrid. Signed-off-by: Wang Xiaojun --- include/linux/mvf_adc.h | 204 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 204 insertions(+) create mode 100644 include/linux/mvf_adc.h (limited to 'include') diff --git a/include/linux/mvf_adc.h b/include/linux/mvf_adc.h new file mode 100644 index 000000000000..26562531afe0 --- /dev/null +++ b/include/linux/mvf_adc.h @@ -0,0 +1,204 @@ +/* Copyright 2012 Freescale Semiconductor, Inc. + * + * Freescale Faraday Quad ADC driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#ifndef MVF_ADC_H +#define MVF_ADC_H + +#define ADC_CFG 0x14 /* Configuration Register */ + +/* Input Clock Select 1-0, Divide ratio 6-5 */ +#define CLEAR_CLK_BIT 0x63 +#define BUSCLK_SEL 0x00 +#define BUSCLK2_SEL 0x01 +#define ALTCLK_SEL 0x02 +#define ADACK_SEL 0x03 +#define CLK_DIV2 0x20 +#define CLK_DIV4 0x40 +#define CLK_DIV8 0x60 +/* Conversion RES Mode Selection 3-2 */ +#define CLEAR_MODE_BIT 0xC +#define BIT8 0x00 +#define BIT10 0x01 +#define BIT12 0x10 +/* Low-Power Configuration 7 */ +#define CLEAR_ADLPC_BIT 0x80 +#define ADLPC_EN 0x80 +/* Long/Short Sample Time Configuration 4,9-8 */ +#define CLEAR_LSTC_BIT 0x310 +#define ADLSMP_LONG 0x10 +#define ADSTS_SHORT 0x100 +#define ADSTS_NORMAL 0x200 +#define ADSTS_LONG 0x300 +/* High speed operation 10 */ +#define CLEAR_ADHSC_BIT 0x400 +#define ADHSC_EN 0x400 +/* Voltage Reference Selection 12-11 */ +#define CLEAR_REFSEL_BIT 0x1800 +#define REFSEL_VALT 0x100 +#define REFSEL_VBG 0x1000 +/* Conversion Trigger Select 13 */ +#define CLEAR_ADTRG_BIT 0x2000 +#define ADTRG_HARD 0x2000 +/* Hardware Average select 15-14 */ +#define CLEAR_AVGS_BIT 0xC000 +#define AVGS_8 0x4000 +#define AVGS_16 0x8000 +#define AVGS_32 0xC000 +/* Data Overwrite Enable 16 */ +#define CLEAR_OVWREN_BIT 0x10000 +#define OVWREN 0x10000 + +#define ADC_GC 0x18 /* General control register */ + +/* Asynchronous clock output 0 */ +#define CLEAR_ADACKEN_BIT 0x1 +#define ADACKEN 0x1 +/* DMA Enable 1 */ +#define CLEAR_DMAEN_BIT 0x2 +#define DMAEN 0x2 +/* Compare Function Rang Enable 2*/ +#define CLEAR_ACREN_BIT 0x4 +#define ACREN 0x4 +/* Compare Function Greater Than Enable 3 */ +#define CLEAR_ACFGT_BIT 0x8 +#define ACFGT 0x8 +/* Enable compare function 4 */ +#define CLEAR_ACFE_BIT 0x10 +#define ACFE 0x10 +/* Hardware Average Enable 5 */ +#define CLEAR_AVGE_BIT 0x20 +#define AVGEN 0x20 +/* Continue Conversion Enable 6 */ +#define CLEAR_ADCO_BIT 0x40 +#define ADCON 0x40 + + +#define ADC_HC0 0x00/* Control register for hardware triggers 0 */ +#define ADC_HC1 0x04/* Control register for hardware triggers 1 */ + +#define IRQ_EN 0x80 +#define ADCHC0(x) ((x)&0xF) +#define AIEN1 0x00000080 +#define COCOA 0x00000000 + +#define ADC_HS 0x08/* Status register for HW triggers */ + +#define ADC_R0 0x0c/* Data result register for HW triggers */ +#define ADC_R1 0x10/* Data result register for HW triggers */ + +#define ADC_GS 0x1c/* General status register (ADC0_GS) */ +#define ADC_CV 0x20/* Compare value register (ADC0_CV) */ +/* Offset correction value register (ADC0_OFS) */ +#define ADC_OFS 0x24 +#define ADC_CAL 0x28/* Calibration value register (ADC0_CAL) */ +#define ADC_PCTL 0x30/* Pin control register (ADC0_PCTL) */ + +/* init */ +#define CLECFG16 0x1ffff +#define SETCFG 0x10098 + +#define CLEHC0 0xff +#define SETHC0 0x85 + +#define CLEPCTL23 0xffffff +#define SETPCTL5 0x20 + +#define ADC_INIT _IO('p', 0xb1) +#define ADC_CONVERT _IO('p', 0xb2) +#define ADC_CONFIGURATION _IOWR('p', 0xb3, struct adc_feature) +#define ADC_REG_CLIENT _IOWR('p', 0xb4, struct adc_feature) + +enum clk_sel { + ADCIOC_BUSCLK_SET, + ADCIOC_ALTCLK_SET, + ADCIOC_ADACK_SET, +}; + + +#define ADCIOC_LPOFF_SET 0 +#define ADCIOC_LPON_SET 1 + +#define ADCIOC_HSON_SET 1 +#define ADCIOC_HSOFF_SET 0 + +enum vol_ref { + ADCIOC_VR_VREF_SET, + ADCIOC_VR_VALT_SET, + ADCIOC_VR_VBG_SET, +}; + +#define ADCIOC_SOFTTS_SET 0 +#define ADCIOC_HARDTS_SET 1 + +#define ADCIOC_HA_DIS 0 +#define ADCIOC_HA_SET 1 + +#define ADCIOC_DOEON_SET 1 +#define ADCIOC_DOEOFF_SET 0 + +#define ADCIOC_ADACKENON_SET 1 +#define ADCIOC_ADACKENOFF_SET 0 + +#define ADCIDC_DMAON_SET 1 +#define ADCIDC_DMAOFF_SET 0 + +#define ADCIOC_CCEOFF_SET 0 +#define ADCIOC_CCEON_SET 1 + +#define ADCIOC_ACFEON_SET 1 +#define ADCIOC_ACFEOFF_SET 0 + +#define ADCIOC_ACFGTON_SET 1 +#define ADCIOC_ACFGTOFF_SET 0 + +#define ADCIOC_ACRENON_SET 1 +#define ADCIOC_ACRENOFF_SET 0 + +enum adc_channel { + ADC0, + ADC1, + ADC2, + ADC3, + ADC4, + ADC5, + ADC6, + ADC7, + ADC8, + ADC9, + ADC10, + ADC11, + ADC12, + ADC13, + ADC14, + ADC15, +}; + +struct adc_feature { + enum adc_channel channel; + enum clk_sel clk_sel;/* clock select */ + int clk_div_num;/* clock divide number*/ + int res_mode;/* resolution sample */ + int sam_time;/* sample time */ + int lp_con;/* low power configuration */ + int hs_oper;/* high speed operation */ + enum vol_ref vol_ref;/* voltage reference */ + int tri_sel;/* trigger select */ + int ha_sel;/* hardware average select */ + int ha_sam;/* hardware average sample */ + int do_ena;/* data overwrite enable */ + int ac_ena;/* Asynchronous clock output enable */ + int dma_ena;/* DMA enable */ + int cc_ena;/* continue converdion enable */ + int compare_func_ena;/* enable compare function */ + int range_ena;/* range enable */ + int greater_ena;/* greater than enable */ + unsigned int result0, result1; +}; + +#endif -- cgit v1.2.3