From 9c6344b3fa547ce7ec78da95134d92d9f9309b31 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 30 Apr 2014 18:54:05 +0800 Subject: ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only The clock mux for the Freescale S/PDIF controller has eight clock sources while most of them are from other moudles and even system clocks that do not allow a rate-changing operation. So we here only allow the clk_set_rate() and clk_round_rate() happened to spdif root clock, the private clock for S/PDIF controller. Signed-off-by: Nicolin Chen Signed-off-by: Mark Brown --- sound/soc/fsl/fsl_spdif.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sound/soc/fsl/fsl_spdif.h') diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h index b1266790d117..18bf8cdc579e 100644 --- a/sound/soc/fsl/fsl_spdif.h +++ b/sound/soc/fsl/fsl_spdif.h @@ -157,6 +157,8 @@ enum spdif_gainsel { #define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK) #define STC_TXCLK_SRC_MAX 8 +#define STC_TXCLK_SPDIF_ROOT 1 + /* SPDIF tx rate */ enum spdif_txrate { SPDIF_TXRATE_32000 = 0, -- cgit v1.2.3