From 02f2735702118a80b3beb9626de5d14de0e32d73 Mon Sep 17 00:00:00 2001 From: Viorel Suman Date: Mon, 2 Nov 2020 09:39:57 +0200 Subject: MLK-24965: ASoC: fsl_xcvr: bit and timestamp counters Add support for bit and timestamp counters. Signed-off-by: Viorel Suman Reviewed-by: Shengjiu Wang --- sound/soc/fsl/fsl_xcvr.c | 87 +++++++++++++++++++++++++++++++----------------- 1 file changed, 56 insertions(+), 31 deletions(-) (limited to 'sound/soc/fsl/fsl_xcvr.c') diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index d82de4f220b0..47a33ef139a8 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -8,41 +8,11 @@ #include #include #include -#include -#include -#include -#include #include #include "fsl_xcvr.h" #include "imx-pcm.h" -#define FSL_XCVR_CAPDS_SIZE 256 - -struct fsl_xcvr_soc_data { - const char *fw_name; -}; - -struct fsl_xcvr { - const struct fsl_xcvr_soc_data *soc_data; - struct platform_device *pdev; - struct regmap *regmap; - struct clk *ipg_clk; - struct clk *pll_ipg_clk; - struct clk *phy_clk; - struct clk *spba_clk; - struct reset_control *reset; - u8 streams; - u32 mode; - u32 arc_mode; - void __iomem *ram_addr; - struct snd_dmaengine_dai_dma_data dma_prms_rx; - struct snd_dmaengine_dai_dma_data dma_prms_tx; - struct snd_aes_iec958 rx_iec958; - struct snd_aes_iec958 tx_iec958; - u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; -}; - static const struct fsl_xcvr_pll_conf { u8 mfi; /* min=0x18, max=0x38 */ u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ @@ -926,6 +896,14 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = { { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00002C89 }, { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00002C89 }, { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00002C89 }, + { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, + { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, + { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, + { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, + { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, + { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, + { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, + { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, @@ -936,6 +914,14 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = { { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, + { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, + { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, + { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, + { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, + { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, + { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, + { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, + { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, }; @@ -967,6 +953,14 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) case FSL_XCVR_RX_DPTH_CTRL_SET: case FSL_XCVR_RX_DPTH_CTRL_CLR: case FSL_XCVR_RX_DPTH_CTRL_TOG: + case FSL_XCVR_RX_DPTH_CNTR_CTRL: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_RX_DPTH_TSCR: + case FSL_XCVR_RX_DPTH_BCR: + case FSL_XCVR_RX_DPTH_BCTR: + case FSL_XCVR_RX_DPTH_BCRR: case FSL_XCVR_TX_DPTH_CTRL: case FSL_XCVR_TX_DPTH_CTRL_SET: case FSL_XCVR_TX_DPTH_CTRL_CLR: @@ -977,6 +971,14 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) case FSL_XCVR_TX_CS_DATA_3: case FSL_XCVR_TX_CS_DATA_4: case FSL_XCVR_TX_CS_DATA_5: + case FSL_XCVR_TX_DPTH_CNTR_CTRL: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_TX_DPTH_TSCR: + case FSL_XCVR_TX_DPTH_BCR: + case FSL_XCVR_TX_DPTH_BCTR: + case FSL_XCVR_TX_DPTH_BCRR: case FSL_XCVR_DEBUG_REG_0: case FSL_XCVR_DEBUG_REG_1: return true; @@ -1009,6 +1011,10 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) case FSL_XCVR_RX_DPTH_CTRL_SET: case FSL_XCVR_RX_DPTH_CTRL_CLR: case FSL_XCVR_RX_DPTH_CTRL_TOG: + case FSL_XCVR_RX_DPTH_CNTR_CTRL: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: case FSL_XCVR_TX_DPTH_CTRL_SET: case FSL_XCVR_TX_DPTH_CTRL_CLR: case FSL_XCVR_TX_DPTH_CTRL_TOG: @@ -1018,6 +1024,10 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) case FSL_XCVR_TX_CS_DATA_3: case FSL_XCVR_TX_CS_DATA_4: case FSL_XCVR_TX_CS_DATA_5: + case FSL_XCVR_TX_DPTH_CNTR_CTRL: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: return true; default: return false; @@ -1229,12 +1239,26 @@ static int fsl_xcvr_probe(struct platform_device *pdev) } ret = imx_pcm_platform_register(dev); - if (ret) + if (ret) { dev_err(dev, "failed to pcm register\n"); + return ret; + } + + ret = sysfs_create_group(&pdev->dev.kobj, fsl_xcvr_get_attr_grp()); + if (ret) + dev_err(&pdev->dev, "fail to create sys group\n"); return ret; } +static int fsl_xcvr_remove(struct platform_device *pdev) +{ + sysfs_remove_group(&pdev->dev.kobj, fsl_xcvr_get_attr_grp()); + pm_runtime_disable(&pdev->dev); + + return 0; +} + static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev) { struct fsl_xcvr *xcvr = dev_get_drvdata(dev); @@ -1346,6 +1370,7 @@ static const struct dev_pm_ops fsl_xcvr_pm_ops = { static struct platform_driver fsl_xcvr_driver = { .probe = fsl_xcvr_probe, + .remove = fsl_xcvr_remove, .driver = { .name = "fsl,imx8mp-audio-xcvr", .pm = &fsl_xcvr_pm_ops, -- cgit v1.2.3