* Freescale enhanced Direct Memory Access(eDMA-v3) Controller

  The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated
  on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by
  programmble memory-mapped registers. Specific DMA request source has fixed channel.

* eDMA Controller
Required properties:
- compatible :
	- "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC
	- "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM
	- "fsl,imx8ulp-edma" for eDMA used on i.MX8ULP
	- "fsl,imx93-edma" for eDMA used on i.MX93
- reg : Specifies base physical address(s) and size of the eDMA channel registers.
	Each eDMA channel has separated register's address and size. The first one
	is Manage Page address space.
- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
- interrupt-names : Should contain below template:
	"edmaX-chanX-Xx"
	     |     | |---> receive/transmit, r or t
	     |     |---> channel id, the max number is 32
	     |---> edma controller instance, 0, 1, 2,..etc

- #dma-cells : Must be <3>.
	The 1st cell specifies the channel ID, but source/event id on i.mx8ulp
	The 2nd cell specifies the channel priority.
	The 3rd cell specifies the channel attributes which include below:
	BIT(0): transmit or receive:
		0: transmit, 1: receive.
	BIT(1): local or remote access:
		0: local, 1: remote.
	BIT(2): dualfifo case or not(only in Audio cyclic now):
		0: not dual fifo case, 1: dualfifo case.
	See the SoC's reference manual for all the supported request sources.
- dma-channels : Number of channels supported by the controller

Optional properties :
- power-domains : Power domains for edma channel used.
- power-domain-names : Power domains name for edma channel used.
- clocks : A list of phandle and clock-specifier pairs, one for each entry in
	clock-names. The first one is for Manage Page
- clock-names : A list of channel clock names.
- fsl,edma-axi : The bus type is AXI.

Examples:
edma0: dma-controller@40018000 {
	compatible = "fsl,imx8qm-edma";
	reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
	      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
	      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
	      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
	#dma-cells = <3>;
	dma-channels = <4>;
	interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
			  "edma0-chan14-rx", "edma0-chan15-tx";
	power-domains = <&pd IMX_SC_R_DMA_0_CH12>,
			<&pd IMX_SC_R_DMA_0_CH13>,
			<&pd IMX_SC_R_DMA_0_CH14>,
			<&pd IMX_SC_R_DMA_0_CH15>;
	power-domain-names = "edma0-chan12", "edma0-chan13",
			     "edma0-chan14", "edma0-chan15";
	status = "okay";
};

or i.mx8ulp:
	edma1: dma-controller@29010000 {
		compatible = "fsl,imx8ulp-edma";
		reg = <0x29010000 0x10000>,
		      <0x29020000 0x10000>,
		      <0x29030000 0x10000>;
		#dma-cells = <3>;
		dma-channels = <2>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma1-chan0-tx",
				  "edma1-chan1-tx";
		clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
			 <&pcc3 IMX8ULP_CLK_DMA1_CH0>,
			 <&pcc3 IMX8ULP_CLK_DMA1_CH1>;
		clock-names = "edma-mp-clk",
			      "edma1-chan0-clk",
			      "edma1-chan1-clk";
		status = "okay";
	};

* DMA clients
DMA client drivers that uses the DMA function must use the format described
in the dma.txt file, using a three-cell specifier for each channel: the 1st
specifies the channel number, the 2nd specifies the priority, and the 3rd
specifies the channel type is for transmit or receive: 0: transmit, 1: receive.

Examples:
lpuart1: serial@5a070000 {
	compatible = "fsl,imx8qm-lpuart";
	reg = <0x0 0x5a070000 0x0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	clocks = <&clk IMX8QM_UART1_CLK>;
	clock-names = "ipg";
	assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
	assigned-clock-rates = <80000000>;
	power-domains = <&pd IMX_SC_R_UART_1>,
	power-domain-names = "uart";
	dma-names = "tx","rx";
	dmas = <&edma0 15 0 0>,
		<&edma0 14 0 1>;
	status = "disabled";
};

or i.mx8ulp:
lpuart5: serial@293a0000 {
	compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
	reg = <0x293a0000 0x1000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
	clock-names = "ipg";
	assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
	assigned-clock-parents = <&cgc1 IMX8ULP_CLK_LPOSC>;
	assigned-clock-rates = <24000000>;
	dmas = <&edma1 58 0 0>, <&edma1 57 0 1>;
	dma-names = "tx","rx";

	status = "okay";
};