# SPDX-License-Identifier: GPL-2.0
# Copyright 2020 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8mp-lvds-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8MP LVDS PHY Device Tree Bindings

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  LVDS PHY found on i.MX8MP SoC.  The IP block contains two PHYs, each of
  which supports a four data lane LVDS channel.

properties:
  compatible:
    enum:
      - fsl,imx8mp-lvds-phy

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  gpr:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to block control syscon

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: apb

  port@0:
    type: object
    description: A port node pointing to the PHY instance0's port node
    properties:
      reg:
        maxItems: 1
        description: PHY instance number.
      "#phy-cells":
        const: 0

    required:
      - reg
      - "#phy-cells"

  port@1:
    type: object
    description: A port node pointing to the PHY instance1's port node
    properties:
      reg:
        maxItems: 1
        description: PHY instance number
      "#phy-cells":
        const: 0

    required:
      - reg
      - "#phy-cells"

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - gpr
  - port@0
  - port@1

additionalProperties: false

examples:
  - |
    ldb_phy: phy@32ec0128 {
        compatible = "fsl,imx8mp-lvds-phy";
        #address-cells = <1>;
        #size-cells = <0>;
        gpr = <&mediamix_blk_ctl>;
        clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
        clock-names = "apb";

        ldb_phy1: port@0 {
            reg = <0>;
            #phy-cells = <0>;
        };

        ldb_phy2: port@1 {
            reg = <1>;
            #phy-cells = <0>;
        };
    };

...