/*
 * Copyright (C) 2017 Toradex AG
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "imx6ull.dtsi"

/ {
	aliases {
		ethernet0 = &fec2;
		ethernet1 = &fec1;
	};

	memory {
		reg = <0x80000000 0x10000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x08000000>;
			linux,cma-default;
		};
	};

	cpus {
		cpu0: cpu@0 {
			arm-supply = <&reg_arm>;
			soc-supply = <&reg_soc>;
			dc-supply = <&reg_soc_in>;
		};
	};

	bl: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	pxp_v4l2_out {
		compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", \
			     "fsl,imx6sl-pxp-v4l2";
		status = "okay";
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_sd1_vmmc: regulator@1 {
		compatible = "regulator-gpio";
		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_reg_sd>;
		regulator-always-on;
		regulator-name = "V3.3_1.8_SD";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		states = <1800000 0x1 3300000 0x0>;
		vin-supply = <&reg_module_3v3>;
	};

	reg_soc_in: regulator-soc-in {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <1275000>;
		regulator-max-microvolt = <1275000>;
		regulator-name = "soc_in";
		regulator-type = "voltage";
		vin-supply = <&reg_module_3v3>;
	};

	reg_eth_phy: regulator-eth-phy {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "eth_phy";
		regulator-type = "voltage";
		vin-supply = <&reg_module_3v3>;
		clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
		startup-delay-us = <150000>;
	};
};

&adc1 {
	num-channels = <10>;
	vref-supply = <&reg_module_3v3_avdd>;
};


/* Colibri SPI */
&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};

&fec2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet2>;
	pinctrl-1 = <&pinctrl_enet2_sleep>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_eth_phy>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			max-speed = <100>;
			reg = <2>;
		};
	};
};

&gpc {
	fsl,cpu_pupscr_sw2iso = <0x1>;
	fsl,cpu_pupscr_sw = <0x0>;
	fsl,cpu_pdnscr_iso2sw = <0x1>;
	fsl,cpu_pdnscr_iso = <0x1>;
	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
	status = "okay";
	nand-on-flash-bbt;

	nand-ecc-mode = "hw";
};

&i2c2 {
	/* use low frequency to compensate for the high pull up values */
	clock-frequency = <40000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
	scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
	status = "okay";
	ad7879@2c {
		compatible = "adi,ad7879-1";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
		reg = <0x2c>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-max-pressure = <4096>;
		adi,resistance-plate-x = <120>;
		adi,first-conversion-delay = /bits/ 8 <3>;
		adi,acquisition-time = /bits/ 8 <1>;
		adi,median-filter-size = /bits/ 8 <2>;
		adi,averaging = /bits/ 8 <1>;
		adi,conversion-interval = /bits/ 8 <255>;
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
};

&pwm1 {
	status = "disabled";
};

&pwm2 {
	status = "disabled";
};

&pwm3 {
	status = "disabled";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "disabled";
};

&pwm5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm5>;
	status = "disabled";
};

&pwm6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm6>;
	status = "disabled";
};

&pwm7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm7>;
	status = "disabled";
};

&pwm8 {
	status = "disabled";
};

&iomuxc {
	imx6ull-colibri {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0X14 /* SODIMM 77 */
				MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x14 /* SODIMM 99 */
				MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x14 /* SODIMM 133 */
				MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x14 /* SODIMM 135 */
				MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x14 /* SODIMM 100 */
				MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x14 /* SODIMM 102 */
				MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07	0x14 /* SODIMM 104 */
				MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x14 /* SODIMM 186 */
			>;
		};

		pinctrl_hog_2: hoggrp-2 { /* Camera */
			fsl,pins = <
				MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x74 /* SODIMM 69 */
				MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x14 /* SODIMM 75 */
				MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x14 /* SODIMM 85 */
				MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x14 /* SODIMM 96 */
				MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x14 /* SODIMM 98 */
			>;
		};

		pinctrl_hog_3: hoggrp-3 { /* CAN2 */
			fsl,pins = <
				MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02	0x14 /* SODIMM 178 */
				MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03	0x14 /* SODIMM 188 */
			>;
		};

		pinctrl_hog_4: hoggrp-4 {
			fsl,pins = <
				MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x74 /* SODIMM 65 */
			>;
		};

		pinctrl_hog_5: hoggrp-5 { /* ATMEL MXT TOUCH */
			fsl,pins = <
				MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x74 /* SODIMM 106 */
			>;
		};

		pinctrl_hog_6: hoggrp-6 { /* Wifi pins */
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x14 /* SODIMM 89 */
				MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x14 /* SODIMM 79 */
				MX6UL_PAD_CSI_VSYNC__GPIO4_IO19		0x14 /* SODIMM 81 */
				MX6UL_PAD_CSI_DATA03__GPIO4_IO24	0x14 /* SODIMM 97 */
				MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x14 /* SODIMM 101 */
				MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x14 /* SODIMM 103 */
				MX6UL_PAD_CSI_HSYNC__GPIO4_IO20		0x14 /* SODIMM 94 */
			>;
		};

		pinctrl_hog_7: hoggrp-7 { /* CAN1 */
			fsl,pins = <
				MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
				MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01	0x74 /* SODIMM 63 */
			>;
		};

		pinctrl_can_int: canintgrp {
			fsl,pins = <
				MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14 /* SODIMM 73 */
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			>;
		};

		pinctrl_enet2_sleep: enet2sleepgrp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO06__GPIO1_IO06	0x0
				MX6UL_PAD_GPIO1_IO07__GPIO1_IO07	0x0
				MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x0
				MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x0
				MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x0
				MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x0
				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
				MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x0
				MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12	0x0
				MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x0
			>;
		};

		pinctrl_ecspi1_cs: ecspi1_cs_grp {
			fsl,pins = <
				MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
				MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
				MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
			>;
		};

		pinctrl_flexcan1: flexcan1grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX	0x1b020
				MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX	0x1b020
			>;
		};

		pinctrl_flexcan2: flexcan2grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
				MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
			>;
		};

		pinctrl_gpio_bl_on: gpio-bl-on {
			fsl,pins = <
				MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
			>;
		};

		pinctrl_gpmi_nand_1: gpmi-nand-1 {
			fsl,pins = <
				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x100a9
				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x100a9
				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x100a9
				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x100a9
				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x100a9
				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x100a9
				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x100a9
				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x100a9
				MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x100a9
				MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x100a9
				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x100a9
				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x100a9
				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x100a9
				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x100a9
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
			>;
		};

		pinctrl_i2c1_gpio: i2c1-gpio-grp {
			fsl,pins = <
				MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
				MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
				MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
			>;
		};

		pinctrl_i2c2_gpio: i2c2-gpio-grp {
			fsl,pins = <
				MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
				MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
			>;
		};


		pinctrl_lcdif_dat: lcdifdatgrp {
			fsl,pins = <
				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
			>;
		};

		pinctrl_lcdif_ctrl: lcdifctrlgrp {
			fsl,pins = <
				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x00079
				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
			>;
		};

		pinctrl_pwm4: pwm4grp {
			fsl,pins = <
				MX6UL_PAD_NAND_WP_B__PWM4_OUT	0x00079
			>;
		};

		pinctrl_pwm5: pwm5grp {
			fsl,pins = <
				MX6UL_PAD_NAND_DQS__PWM5_OUT	0x00079
			>;
		};

		pinctrl_pwm6: pwm6grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_TX_EN__PWM6_OUT	0x00079
			>;
		};

		pinctrl_pwm7: pwm7grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x00079
			>;
		};

		pinctrl_uart1: uart1-grp {
			fsl,pins = <
				MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX	0x1b0b1
				MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX	0x1b0b1
				MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS	0x1b0b1
				MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS	0x1b0b1
			>;
		};

		pinctrl_uart1_ctrl1: uart1-ctrlgrp1 { /* Additional DTR, DCD */
			fsl,pins = <
				MX6UL_PAD_JTAG_TDI__GPIO1_IO13		0x1b0b1 /* DCD */
				MX6UL_PAD_LCD_DATA18__GPIO3_IO23	0x1b0b1 /* DSR */
				MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x1b0b1 /* DTR */
				MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1
				MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1
				MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS	0x1b0b1
				MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS	0x1b0b1
			>;
		};
		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX	0x1b0b1
				MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX	0x1b0b1
			>;
		};

		pinctrl_usbh1_reg: gpio_usbh_reg {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x1b0b1 /* SODIMM 129 USBH PEN */
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
				MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x10059
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
			fsl,pins = <
				MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x170b9
				MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x100b9
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
			fsl,pins = <
				MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x170f9
				MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x100f9
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
				MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
				MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
				MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
				MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
				MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x17059

				MX6UL_PAD_GPIO1_IO03__REF_CLK_32K	0x14
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
			>;
		};
	};
};

&iomuxc_snvs {
	imx6ull-colibri {
		pinctrl_snvs_hog_1: snvs-hoggrp-1 {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x14 /* SODIMM 93 */
				MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x14 /* SODIMM 95 */
				MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10	0x74 /* SODIMM 105 */
				MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x14 /* SODIMM 131 USBH OC */
				MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x74 /* SODIMM 138 */
			>;
		};

		pinctrl_snvs_hog_2: snvs-hoggrp-2 { /* ATMEL MXT TOUCH */
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x74 /* SODIMM 107 */
			>;
		};

		pinctrl_snvs_hog_3: snvs-hoggrp-3 { /* Wifi pins */
			fsl,pins = <
				MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x14 /* SODIMM 127 */
			>;
		};

		pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x100b0
			>;
		};

		pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x400100b0
			>;
		};

		pinctrl_snvs_usbc_det: snvs-gpio_usbc_det {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x130b0
			>;
		};

		pinctrl_snvs_gpiokeys: snvs-gpiokeysgrp {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x130b0
			>;
		};

		pinctrl_snvs_cd_usdhc1: snvs-usdhc1-cd-grp {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* CD */
			>;
		};

		pinctrl_snvs_cd_usdhc1_sleep: snvs-usdhc1-cd-grp-slp {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x0
			>;
		};

		pinctrl_wifi_pdn: wifi-pdn {
			fsl,pins = <
				MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x14
			>;
		};
	};
};

&pxp {
	status = "okay";
};

&sdma {
	status = "okay";
};

&snvs_pwrkey {
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
	fsl,uart-has-rtscts;
	fsl,dte-mode;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	fsl,uart-has-rtscts;
	fsl,dte-mode;
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	fsl,dte-mode;
};

&usbotg1 {
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
};


&usbotg2 {
	dr_mode = "host";
};

&usdhc1 {
	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
	assigned-clock-rates = <0>, <198000000>;
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
};