/* * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #include #define PHYFLEX_CLKO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \ PAD_CTL_SRE_FAST) #define PHYFLEX_PAD_GPIO_5__CCM_CLKO \ (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(PHYFLEX_CLKO_PAD_CTRL)) #define PHYFLEX_CLK1_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \ PAD_CTL_SRE_FAST) #define PHYFLEX_PAD_NANDF_CS2__CCM_CLKO2 \ (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(PHYFLEX_CLK1_PAD_CTRL)) /* Common pads for PhyFlex board */ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = { /* GPIOs for revision control */ MX6Q_PAD_SD4_DAT4__GPIO_2_12, MX6Q_PAD_SD4_DAT5__GPIO_2_13, MX6Q_PAD_SD4_DAT6__GPIO_2_14, MX6Q_PAD_SD4_DAT7__GPIO_2_15, /* User LEDs */ MX6Q_PAD_ENET_TXD0__GPIO_1_30, // Led Green MX6Q_PAD_EIM_EB3__GPIO_2_31, // Led Red MX6Q_PAD_EIM_CS1__GPIO_2_24, // User Led -> HW Changed to Second TS Interrupt MX6Q_PAD_EIM_D25__UART3_RXD, MX6Q_PAD_EIM_D24__UART3_TXD, MX6Q_PAD_EIM_D30__UART3_CTS, MX6Q_PAD_EIM_D31__UART3_RTS, /* UART4 */ MX6Q_PAD_KEY_COL0__UART4_TXD, MX6Q_PAD_KEY_ROW0__UART4_RXD, MX6Q_PAD_ENET_MDIO__ENET_MDIO, MX6Q_PAD_ENET_MDC__ENET_MDC, MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK, MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK, MX6Q_PAD_ENET_RX_ER__GPIO_1_24, MX6Q_PAD_ENET_TX_EN__ENET_TX_EN, MX6Q_PAD_ENET_RXD1__MLB_MLBSIG, MX6Q_PAD_ENET_TXD0__GPIO_1_30, MX6Q_PAD_ENET_TXD1__MLB_MLBCLK, //MX6Q_PAD_ENET_RXD1__ENET_RDATA_1, //MX6Q_PAD_ENET_TXD1__ENET_TDATA_1, //MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC, MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC, MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0, MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1, MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2, MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3, MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC, MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0, MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1, MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2, MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3, MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL, MX6Q_PAD_EIM_D23__GPIO_3_23, // ethernet PHY reset /* SD1 */ MX6Q_PAD_SD1_CLK__USDHC1_CLK, MX6Q_PAD_SD1_CMD__USDHC1_CMD, MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, MX6Q_PAD_SD1_DAT1__USDHC1_DAT1, MX6Q_PAD_SD1_DAT2__USDHC1_DAT2, MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, /* SD2 */ MX6Q_PAD_SD2_CLK__USDHC2_CLK, MX6Q_PAD_SD2_CMD__USDHC2_CMD, MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, MX6Q_PAD_SD2_DAT1__USDHC2_DAT1, MX6Q_PAD_SD2_DAT2__USDHC2_DAT2, MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, /* SD2_CD and SD2_WP */ MX6Q_PAD_GPIO_2__GPIO_1_2, MX6Q_PAD_GPIO_4__GPIO_1_4, /* SD3 */ MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ, MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ, MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ, MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ, MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ, MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ, MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ, MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ, MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ, MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ, MX6Q_PAD_SD3_RST__GPIO_7_8, /* SD3_CD and SD3_WP */ MX6Q_PAD_ENET_RXD0__GPIO_1_27, MX6Q_PAD_ENET_TXD1__GPIO_1_29, /* SPI3 */ MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK, MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI, MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO, MX6Q_PAD_DISP0_DAT3__GPIO_4_24, /*SS0*/ MX6Q_PAD_DISP0_DAT4__GPIO_4_25, /*SS1*/ MX6Q_PAD_DISP0_DAT5__GPIO_4_26, /*SS2*/ MX6Q_PAD_DISP0_DAT6__GPIO_4_27, /*SS3*/ MX6Q_PAD_EIM_D29__GPIO_3_29, /* GPIOS */ MX6Q_PAD_DISP0_DAT14__GPIO_5_8, /* Interrupt for LCD017 */ MX6Q_PAD_DISP0_DAT13__GPIO_5_7, MX6Q_PAD_DI0_PIN2__GPIO_4_18, MX6Q_PAD_DI0_PIN3__GPIO_4_19, MX6Q_PAD_GPIO_6__GPIO_1_6, MX6Q_PAD_GPIO_9__GPIO_1_9, MX6Q_PAD_GPIO_17__GPIO_7_12, /* Interrupt for LCD018 */ MX6Q_PAD_GPIO_18__GPIO_7_13, MX6Q_PAD_GPIO_19__GPIO_4_5, MX6Q_PAD_EIM_CS0__GPIO_2_23, /* ESAI */ // MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT, // MX6Q_PAD_NANDF_CS2__ESAI1_TX0, // MX6Q_PAD_NANDF_CS3__ESAI1_TX1, /* I2C1 */ MX6Q_PAD_EIM_D28__I2C1_SDA, MX6Q_PAD_EIM_D21__I2C1_SCL, /* I2C2 */ MX6Q_PAD_EIM_EB2__I2C2_SCL, MX6Q_PAD_EIM_D16__I2C2_SDA, /* I2C3 */ MX6Q_PAD_EIM_D17__I2C3_SCL, MX6Q_PAD_EIM_D18__I2C3_SDA, /* DISPLAY */ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4, MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, /* LVDS0 BACKLIGHT ENABLE */ MX6Q_PAD_GPIO_8__GPIO_1_8, MX6Q_PAD_EIM_OE__GPIO_2_25, /* PWM1 */ MX6Q_PAD_DISP0_DAT8__PWM1_PWMO, MX6Q_PAD_DISP0_DAT9__PWM2_PWMO, /* HDMI */ MX6Q_PAD_KEY_COL3__GPIO_4_12, /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */ MX6Q_PAD_KEY_ROW3__GPIO_4_13, /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */ MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE, /* USBOTG ID pin */ MX6Q_PAD_GPIO_1__USBOTG_ID, MX6Q_PAD_KEY_ROW4__GPIO_4_15, /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */ MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC, MX6Q_PAD_GPIO_0__GPIO_1_0, MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC, /* MX6Q_PAD_GPIO_3__GPIO_1_3 */ /* CAN1 */ MX6Q_PAD_KEY_COL2__CAN1_TXCAN, MX6Q_PAD_KEY_ROW2__CAN1_RXCAN, /* HW Introspection / 1-Wire interface data pin */ MX6Q_PAD_EIM_D20__GPIO_3_20, /* AUDIO PADS */ MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC, MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD, MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS, MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD, /* ipu1 csi0 */ MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC, MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK, MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC, MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20, PHYFLEX_PAD_GPIO_5__CCM_CLKO, // conflict with interrupt ts 1 soc1362.0 MX6Q_PAD_ENET_RX_ER__GPIO_1_24, MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10, MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11, MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12, MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13, MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14, MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15, MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16, MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17, MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18, MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19, /* ipu2 csi1 */ MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK, MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC, MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC, MX6Q_PAD_EIM_DA10__GPIO_3_10, MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0, MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1, MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2, MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3, MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4, MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5, MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6, MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7, MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8, MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9, MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10, MX6Q_PAD_EIM_EB0__GPIO_2_28, MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12, MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13, MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14, MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15, MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16, MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17, MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18, MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19, /* Enable CAM1 clocking only if it is needed for camera 1 lvds */ PHYFLEX_PAD_NANDF_CS2__CCM_CLKO2, /* PCIE_WAKE */ MX6Q_PAD_GPIO_7__GPIO_1_7, /* Default high speed pin settings for sd-cards */ MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ, MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ, MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ, MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ, MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ, MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ, MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ, MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ, MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ, MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ, MX6Q_PAD_SD2_CLK__USDHC2_CLK_200MHZ, MX6Q_PAD_SD2_CMD__USDHC2_CMD_200MHZ, MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_200MHZ, MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ, MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ, MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ, }; /* This iomux array is for phyFLEX-i.MX6 modules Rev. 1 */ static iomux_v3_cfg_t mx6q_phytec_rev1_pads[] = { /* PMIC interrupt */ MX6Q_PAD_DI0_PIN15__GPIO_4_17, /* PCIE_PRSNT */ MX6Q_PAD_SD1_DAT3__GPIO_1_21, }; /* This iomux array is for phyFLEX-i.MX6 modules Rev. 2 */ static iomux_v3_cfg_t mx6q_phytec_rev2_pads[] = { /* PMIC interrupt */ MX6Q_PAD_SD4_DAT1__GPIO_2_9, /* PCIE_PRSNT */ MX6Q_PAD_DI0_PIN15__GPIO_4_17, /* CMIC Wake */ MX6Q_PAD_SD4_DAT3__GPIO_2_11, };