/* * Copyright (c) 2009 NVIDIA Corporation. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of the NVIDIA Corporation nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ // // DO NOT EDIT - generated by simspec! // #ifndef ___ARPWFM_H_INC_ #define ___ARPWFM_H_INC_ // Register PWM_CONTROLLER_PWM_CSR_0_0 #define PWM_CONTROLLER_PWM_CSR_0_0 _MK_ADDR_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_WORD_COUNT 0x1 #define PWM_CONTROLLER_PWM_CSR_0_0_RESET_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_RESET_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_READ_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_0_0_WRITE_MASK _MK_MASK_CONST(0x80ff1fff) // Enable Pulse width modulator #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT _MK_SHIFT_CONST(31) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_FIELD (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_RANGE 31:31 #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT_MASK _MK_MASK_CONST(0x1) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DISABLE _MK_ENUM_CONST(0) #define PWM_CONTROLLER_PWM_CSR_0_0_ENB_ENABLE _MK_ENUM_CONST(1) // pulse width thats needs to be programmed. //0=Always low 1=1/256 Pulse high 2=2/256 Pulse High .N=N/256 Pulse high #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT _MK_SHIFT_CONST(16) #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_FIELD (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT) #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_RANGE 23:16 #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT_MASK _MK_MASK_CONST(0xff) #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Frequency divider that needs to be Programmed. #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT _MK_SHIFT_CONST(0) #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_FIELD (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT) #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_RANGE 12:0 #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT_MASK _MK_MASK_CONST(0x1fff) #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Reserved address 4 [0x4] // Reserved address 8 [0x8] // Reserved address 12 [0xc] // Register PWM_CONTROLLER_PWM_CSR_1_0 #define PWM_CONTROLLER_PWM_CSR_1_0 _MK_ADDR_CONST(0x10) #define PWM_CONTROLLER_PWM_CSR_1_0_WORD_COUNT 0x1 #define PWM_CONTROLLER_PWM_CSR_1_0_RESET_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_RESET_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_READ_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_1_0_WRITE_MASK _MK_MASK_CONST(0x80ff1fff) // Enable pulse width modulator #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SHIFT _MK_SHIFT_CONST(31) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_FIELD (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_1_0_ENB_SHIFT) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_RANGE 31:31 #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DEFAULT_MASK _MK_MASK_CONST(0x1) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DISABLE _MK_ENUM_CONST(0) #define PWM_CONTROLLER_PWM_CSR_1_0_ENB_ENABLE _MK_ENUM_CONST(1) // pulse width that needs to be programmed // 0=Always low 1=1/256 Pulse high 2=2/256 Pulse High .N=N/256 Pulse high #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SHIFT _MK_SHIFT_CONST(16) #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_FIELD (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SHIFT) #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_RANGE 23:16 #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_DEFAULT_MASK _MK_MASK_CONST(0xff) #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Frequency divider that needs to be Programmed. #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SHIFT _MK_SHIFT_CONST(0) #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_FIELD (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SHIFT) #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_RANGE 12:0 #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_DEFAULT_MASK _MK_MASK_CONST(0x1fff) #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Reserved address 20 [0x14] // Reserved address 24 [0x18] // Reserved address 28 [0x1c] // Register PWM_CONTROLLER_PWM_CSR_2_0 #define PWM_CONTROLLER_PWM_CSR_2_0 _MK_ADDR_CONST(0x20) #define PWM_CONTROLLER_PWM_CSR_2_0_WORD_COUNT 0x1 #define PWM_CONTROLLER_PWM_CSR_2_0_RESET_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_RESET_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_READ_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_2_0_WRITE_MASK _MK_MASK_CONST(0x80ff1fff) // Enable pulse width modulator #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SHIFT _MK_SHIFT_CONST(31) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_FIELD (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_2_0_ENB_SHIFT) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_RANGE 31:31 #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DEFAULT_MASK _MK_MASK_CONST(0x1) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DISABLE _MK_ENUM_CONST(0) #define PWM_CONTROLLER_PWM_CSR_2_0_ENB_ENABLE _MK_ENUM_CONST(1) // Pulse Width that needs to be programmed. // 0=Always low 1=1/256 Pulse high 2=2/256 Pulse High .N=N/256 Pulse high #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SHIFT _MK_SHIFT_CONST(16) #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_FIELD (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SHIFT) #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_RANGE 23:16 #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_DEFAULT_MASK _MK_MASK_CONST(0xff) #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Frequency divider that needs to be Programmed. #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SHIFT _MK_SHIFT_CONST(0) #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_FIELD (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SHIFT) #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_RANGE 12:0 #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_DEFAULT_MASK _MK_MASK_CONST(0x1fff) #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Reserved address 36 [0x24] // Reserved address 40 [0x28] // Reserved address 44 [0x2c] // Register PWM_CONTROLLER_PWM_CSR_3_0 #define PWM_CONTROLLER_PWM_CSR_3_0 _MK_ADDR_CONST(0x30) #define PWM_CONTROLLER_PWM_CSR_3_0_WORD_COUNT 0x1 #define PWM_CONTROLLER_PWM_CSR_3_0_RESET_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_RESET_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_READ_MASK _MK_MASK_CONST(0x80ff1fff) #define PWM_CONTROLLER_PWM_CSR_3_0_WRITE_MASK _MK_MASK_CONST(0x80ff1fff) // Enable pulse width modulator #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SHIFT _MK_SHIFT_CONST(31) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_FIELD (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_3_0_ENB_SHIFT) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_RANGE 31:31 #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DEFAULT_MASK _MK_MASK_CONST(0x1) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DISABLE _MK_ENUM_CONST(0) #define PWM_CONTROLLER_PWM_CSR_3_0_ENB_ENABLE _MK_ENUM_CONST(1) // pulse width that needs to be programmed // 0=Always low 1=1/256 Pulse high 2=2/256 Pulse High .N=N/256 Pulse high #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SHIFT _MK_SHIFT_CONST(16) #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_FIELD (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SHIFT) #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_RANGE 23:16 #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_DEFAULT_MASK _MK_MASK_CONST(0xff) #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // Frequency divider that needs to be Programmed. #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SHIFT _MK_SHIFT_CONST(0) #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_FIELD (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SHIFT) #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_RANGE 12:0 #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_WOFFSET 0x0 #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_DEFAULT_MASK _MK_MASK_CONST(0x1fff) #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SW_DEFAULT _MK_MASK_CONST(0x0) #define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // // REGISTER LIST // #define LIST_ARPWFM_REGS(_op_) \ _op_(PWM_CONTROLLER_PWM_CSR_0_0) \ _op_(PWM_CONTROLLER_PWM_CSR_1_0) \ _op_(PWM_CONTROLLER_PWM_CSR_2_0) \ _op_(PWM_CONTROLLER_PWM_CSR_3_0) // // ADDRESS SPACES // #define BASE_ADDRESS_PWM_CONTROLLER 0x00000000 // // ARPWFM REGISTER BANKS // #define PWM_CONTROLLER0_FIRST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0 #define PWM_CONTROLLER0_LAST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0 #define PWM_CONTROLLER1_FIRST_REG 0x0010 // PWM_CONTROLLER_PWM_CSR_1_0 #define PWM_CONTROLLER1_LAST_REG 0x0010 // PWM_CONTROLLER_PWM_CSR_1_0 #define PWM_CONTROLLER2_FIRST_REG 0x0020 // PWM_CONTROLLER_PWM_CSR_2_0 #define PWM_CONTROLLER2_LAST_REG 0x0020 // PWM_CONTROLLER_PWM_CSR_2_0 #define PWM_CONTROLLER3_FIRST_REG 0x0030 // PWM_CONTROLLER_PWM_CSR_3_0 #define PWM_CONTROLLER3_LAST_REG 0x0030 // PWM_CONTROLLER_PWM_CSR_3_0 #ifndef _MK_SHIFT_CONST #define _MK_SHIFT_CONST(_constant_) _constant_ #endif #ifndef _MK_MASK_CONST #define _MK_MASK_CONST(_constant_) _constant_ #endif #ifndef _MK_ENUM_CONST #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) #endif #ifndef _MK_ADDR_CONST #define _MK_ADDR_CONST(_constant_) _constant_ #endif #endif // ifndef ___ARPWFM_H_INC_