/* * Copyright (c) 2009 NVIDIA Corporation. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of the NVIDIA Corporation nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ // // DO NOT EDIT - generated by simspec! // #ifndef ___ARTIMERUS_H_INC_ #define ___ARTIMERUS_H_INC_ // Register TIMERUS_CNTR_1US_0 #define TIMERUS_CNTR_1US_0 _MK_ADDR_CONST(0x0) #define TIMERUS_CNTR_1US_0_WORD_COUNT 0x1 #define TIMERUS_CNTR_1US_0_RESET_VAL _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_RESET_MASK _MK_MASK_CONST(0xffffffff) #define TIMERUS_CNTR_1US_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_READ_MASK _MK_MASK_CONST(0xffffffff) #define TIMERUS_CNTR_1US_0_WRITE_MASK _MK_MASK_CONST(0x0) // Elapsed time in micro-second #define TIMERUS_CNTR_1US_0_HIGH_VALUE_SHIFT _MK_SHIFT_CONST(16) #define TIMERUS_CNTR_1US_0_HIGH_VALUE_FIELD (_MK_MASK_CONST(0xffff) << TIMERUS_CNTR_1US_0_HIGH_VALUE_SHIFT) #define TIMERUS_CNTR_1US_0_HIGH_VALUE_RANGE 31:16 #define TIMERUS_CNTR_1US_0_HIGH_VALUE_WOFFSET 0x0 #define TIMERUS_CNTR_1US_0_HIGH_VALUE_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_HIGH_VALUE_DEFAULT_MASK _MK_MASK_CONST(0xffff) #define TIMERUS_CNTR_1US_0_HIGH_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_HIGH_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_HIGH_VALUE_INIT_ENUM x // Elapsed time in micro-second #define TIMERUS_CNTR_1US_0_LOW_VALUE_SHIFT _MK_SHIFT_CONST(0) #define TIMERUS_CNTR_1US_0_LOW_VALUE_FIELD (_MK_MASK_CONST(0xffff) << TIMERUS_CNTR_1US_0_LOW_VALUE_SHIFT) #define TIMERUS_CNTR_1US_0_LOW_VALUE_RANGE 15:0 #define TIMERUS_CNTR_1US_0_LOW_VALUE_WOFFSET 0x0 #define TIMERUS_CNTR_1US_0_LOW_VALUE_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_LOW_VALUE_DEFAULT_MASK _MK_MASK_CONST(0xffff) #define TIMERUS_CNTR_1US_0_LOW_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_LOW_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define TIMERUS_CNTR_1US_0_LOW_VALUE_INIT_ENUM x // Register TIMERUS_USEC_CFG_0 #define TIMERUS_USEC_CFG_0 _MK_ADDR_CONST(0x4) #define TIMERUS_USEC_CFG_0_WORD_COUNT 0x1 #define TIMERUS_USEC_CFG_0_RESET_VAL _MK_MASK_CONST(0xc) #define TIMERUS_USEC_CFG_0_RESET_MASK _MK_MASK_CONST(0xffff) #define TIMERUS_USEC_CFG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) #define TIMERUS_USEC_CFG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) #define TIMERUS_USEC_CFG_0_READ_MASK _MK_MASK_CONST(0xffff) #define TIMERUS_USEC_CFG_0_WRITE_MASK _MK_MASK_CONST(0xffff) // usec dividend. #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SHIFT _MK_SHIFT_CONST(8) #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_FIELD (_MK_MASK_CONST(0xff) << TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SHIFT) #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_RANGE 15:8 #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_WOFFSET 0x0 #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_DEFAULT_MASK _MK_MASK_CONST(0xff) #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SW_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // usec divisor. #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT _MK_SHIFT_CONST(0) #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_FIELD (_MK_MASK_CONST(0xff) << TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT) #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_RANGE 7:0 #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_WOFFSET 0x0 #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT _MK_MASK_CONST(0xc) #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT_MASK _MK_MASK_CONST(0xff) #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SW_DEFAULT _MK_MASK_CONST(0x0) #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) // // REGISTER LIST // #define LIST_ARTIMERUS_REGS(_op_) \ _op_(TIMERUS_CNTR_1US_0) \ _op_(TIMERUS_USEC_CFG_0) // // ADDRESS SPACES // #define BASE_ADDRESS_TIMERUS 0x00000000 // // ARTIMERUS REGISTER BANKS // #define TIMERUS0_FIRST_REG 0x0000 // TIMERUS_CNTR_1US_0 #define TIMERUS0_LAST_REG 0x0004 // TIMERUS_USEC_CFG_0 #ifndef _MK_SHIFT_CONST #define _MK_SHIFT_CONST(_constant_) _constant_ #endif #ifndef _MK_MASK_CONST #define _MK_MASK_CONST(_constant_) _constant_ #endif #ifndef _MK_ENUM_CONST #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) #endif #ifndef _MK_ADDR_CONST #define _MK_ADDR_CONST(_constant_) _constant_ #endif #endif // ifndef ___ARTIMERUS_H_INC_