// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS1012A FRWY Board.
 *
 * Copyright 2018 NXP
 *
 * Pramod Kumar <pramod.kumar_1@nxp.com>
 *
 */
/dts-v1/;

#include "fsl-ls1012a.dtsi"

/ {
	model = "LS1012A FRWY Board";
	compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";

	aliases {
		ethernet0 = &pfe_mac0;
		ethernet1 = &pfe_mac1;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&codec>;
			frame-master;
			bitclock-master;
			system-clock-frequency = <25000000>;
		};
	};
};

&pcie {
	status = "okay";
};

&duart0 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		reg = <0xa>;
		VDDA-supply = <&reg_1p8v>;
		VDDIO-supply = <&reg_1p8v>;
		clocks = <&sys_mclk>;
	};
};

&qspi {
	num-cs = <1>;
	bus-num = <0>;
	status = "okay";

	qflash0: w25q16dw@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		m25p,fast-read;
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&pfe {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pfe_mac0: ethernet@0 {
		compatible = "fsl,pfe-gemac-port";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0>;	/* GEM_ID */
		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
		fsl,mdio-mux-val = <0x0>;
		phy-mode = "sgmii";
		phy-handle = <&sgmii_phy1>;
	};

	pfe_mac1: ethernet@1 {
		compatible = "fsl,pfe-gemac-port";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x1>;	/* GEM_ID */
		fsl,mdio-mux-val = <0x0>;
		phy-mode = "sgmii";
		phy-handle = <&sgmii_phy2>;
	};

	mdio@0 {
		#address-cells = <1>;
		#size-cells = <0>;

		sgmii_phy1: ethernet-phy@2 {
			reg = <0x2>;
		};

		sgmii_phy2: ethernet-phy@1 {
			reg = <0x1>;
		};
	};
};

&sai2 {
	status = "okay";
};