// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2020 NXP.
 */

#include "imx8dxl-evk.dts"

/ {
	panel {
		compatible = "wks,101wx001";
		blctr-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
		pinctrl-assert-gpios = <&pca6416_1 3 GPIO_ACTIVE_LOW>,
				       <&pca6416_1 4 GPIO_ACTIVE_LOW>,
				       <&pca6416_1 6 GPIO_ACTIVE_LOW>,
				       <&pca6416_1 7 GPIO_ACTIVE_LOW>,
				       <&pca6416_1 8 GPIO_ACTIVE_LOW>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&lcdif_out>;
			};
		};
	};
};

&iomuxc {
	pinctrl_hog: hoggrp {
		fsl,pins = <
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  	0x000514a0
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
		>;
	};
};

&sai1 {
	status = "disabled";
};

&m2_uart1_sel {
	status = "disabled";
};

&lpuart1 {
	status = "disabled";
};

&cm40_lpuart {
	status = "disabled";
};

&eqos {
	status = "disabled";
};

&wm8960_1 {
	status = "disabled";
};

&wm8960_2 {
	status = "disabled";
};

&wm8960_3 {
	status = "disabled";
};

&iomuxc {
	pinctrl_lcdif: lcdifgrp {
		fsl,pins = <
			IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00			0xe8000023
			IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01			0xe8000023
			IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02			0xe8000023
			IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03		0xd0000023
			IMX8DXL_UART1_TX_ADMA_LCDIF_D04			0xe8000023
			IMX8DXL_UART1_RX_ADMA_LCDIF_D05			0xe8000023
			IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06		0xe8000023
			IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07		0xe8000023
			IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08			0xe8000023
			IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09			0xe8000023
			IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10			0xe8000023
			IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11			0xe8000023
			IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12			0xe8000023
			IMX8DXL_ADC_IN1_ADMA_LCDIF_D13			0xe8200003
			IMX8DXL_ADC_IN0_ADMA_LCDIF_D14			0xe8200003
			IMX8DXL_ADC_IN3_ADMA_LCDIF_D15			0xe8200003
			IMX8DXL_ADC_IN2_ADMA_LCDIF_D16			0xe8200003
			IMX8DXL_ADC_IN5_ADMA_LCDIF_D17			0xe8200003
			IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC		0xd0000023
			IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET		0xd0000023
			IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN			0xd0000023
			IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC		0xd0000023
			IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK		0xd0000023
		>;
	};
};

&adma_lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif>;
	status = "okay";

	assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
			  <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
			  <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
	assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
				 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
	assigned-clock-rates = <0>, <24000000>, <711000000>;

	port@0 {
		lcdif_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};