// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 */

#include "imx8mp-evk.dts"

/ {
	model = "NXP i.MX8MPlus DDR4 EVK board";
};

&flexspi {
	status = "disabled";
};

&clk {
	assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
			  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
			  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
			  <&clk IMX8MP_AUDIO_PLL1>,
			  <&clk IMX8MP_AUDIO_PLL2>,
			  <&clk IMX8MP_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
				 <&clk IMX8MP_SYS_PLL3_OUT>;
	assigned-clock-rates = <400000000>,
			       <600000000>,
			       <400000000>,
			       <393216000>,
			       <361267200>,
			       <1039500000>;
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
	nand-on-flash-bbt;
};

&gpu_2d {
	assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>,
			  <&clk IMX8MP_CLK_GPU_AXI>,
			  <&clk IMX8MP_CLK_GPU_AHB>,
			  <&clk IMX8MP_GPU_PLL>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
				 <&clk IMX8MP_GPU_PLL_OUT>,
				 <&clk IMX8MP_GPU_PLL_OUT>;
	assigned-clock-rates = <800000000>, <600000000>,
			       <300000000>, <600000000>;
};

&gpu_3d {
	assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>,
			  <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>,
			  <&clk IMX8MP_CLK_GPU_AXI>,
			  <&clk IMX8MP_CLK_GPU_AHB>,
			  <&clk IMX8MP_GPU_PLL>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
				 <&clk IMX8MP_SYS_PLL1_800M>,
				 <&clk IMX8MP_GPU_PLL_OUT>,
				 <&clk IMX8MP_SYS_PLL1_800M>;
	assigned-clock-rates = <800000000>, <800000000>,
			       <600000000>, <300000000>,
			       <600000000>;
};

&ml_vipsi {
	assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>,
			  <&clk IMX8MP_CLK_ML_AXI>,
			  <&clk IMX8MP_CLK_ML_AHB>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
				 <&clk IMX8MP_SYS_PLL1_800M>,
				 <&clk IMX8MP_GPU_PLL_OUT>;
	assigned-clock-rates = <800000000>, <800000000>, <300000000>;
};

&usdhc3 {
	status = "disabled";
};

&vpu_g1 {

	assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>;
	assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_VPU_PLL_OUT>;
	assigned-clock-rates = <600000000>, <600000000>, <600000000>;
};

&vpu_g2 {
	assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_VPU_PLL_OUT>;
	assigned-clock-rates = <500000000>, <600000000>;
};

&vpu_vc8000e {
	assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VPU_PLL_OUT>;
	assigned-clock-rates = <400000000>, <600000000>;
};

&iomuxc {
	pinctrl_gpmi_nand: gpmi-nand {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_ALE__NAND_ALE			0x00000096
			MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B		0x00000096
			MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B		0x00000096
			MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B		0x00000096
			MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B		0x00000096
			MX8MP_IOMUXC_NAND_CLE__NAND_CLE			0x00000096
			MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00		0x00000096
			MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01		0x00000096
			MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02		0x00000096
			MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03		0x00000096
			MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04		0x00000096
			MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05		0x00000096
			MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06		0x00000096
			MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07		0x00000096
			MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B		0x00000096
			MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B		0x00000056
			MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B		0x00000096
			MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B		0x00000096
		>;
	};
};

&lcdif3 {
	thres-low  = <2 3>;             /* (FIFO * 2 / 3) */
	thres-high = <3 3>;             /* (FIFO * 3 / 3) */
	status = "okay";
};