// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2019 NXP.
 */

#include "imx8mq-evk.dts"

/ {
	sound-hdmi {
		status = "disabled";
	};
};

&irqsteer {
	status = "okay";
};

/delete-node/ &hdmi;

&lcdif {
	status = "disabled";
};

&dcss {
	status = "okay";

	clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
		 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
		 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
		 <&clk IMX8MQ_CLK_DC_PIXEL>,
		 <&clk IMX8MQ_CLK_DISP_DTRC>;
	clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
	assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
					  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
					  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
					  <&clk IMX8MQ_CLK_DISP_AXI>,
					  <&clk IMX8MQ_CLK_DISP_RTRM>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
							 <&clk IMX8MQ_VIDEO_PLL1>,
							 <&clk IMX8MQ_CLK_27M>,
							 <&clk IMX8MQ_SYS1_PLL_800M>,
							 <&clk IMX8MQ_SYS1_PLL_800M>;
	assigned-clock-rates = <600000000>, <0>, <0>,
						   <800000000>,
						   <400000000>;

	port@0 {
		dcss_out: endpoint {
			remote-endpoint = <&mipi_dsi_in>;
		};
	};
};

&adv_bridge {
	status = "okay";

	port@0 {
		adv7535_in: endpoint {
			remote-endpoint = <&mipi_dsi_out>;
		};
	};
};

&mipi_dsi {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			mipi_dsi_in: endpoint {
				remote-endpoint = <&dcss_out>;
			};
		};

		port@1 {
			reg = <1>;
			mipi_dsi_out: endpoint {
				remote-endpoint = <&adv7535_in>;
			};
		};
	};
};

&dphy {
	status = "okay";
};

&iomuxc {
	pinctrl_mipi_dsi_en: mipi_dsi_en {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6	0x16
		>;
	};
};