// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 NXP
 */

#include "imx8mq-evk.dts"

/ {
	modem_reset: modem-reset {
		reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
	};

	usdhc2_pwrseq: usdhc2_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
	};
};

&pinctrl_usdhc2 {
	fsl,pins = <
		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
		MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4               0x49
		MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10             0x46
	>;
};

&pinctrl_usdhc2_100mhz {
	fsl,pins = <
		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
		MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4               0x49
	>;
};

&pinctrl_usdhc2_200mhz {
	fsl,pins = <
		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
		MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4               0x49
	>;
};

&pcie0{
	status = "disabled";
};

&pcie1{
	status = "disabled";
};

&usdhc2 {
	pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
	/delete-property/ cd-gpios;
	pm-ignore-notify;
	keep-power-in-suspend;
	non-removable;
	cap-power-off-card;
	mmc-pwrseq = <&usdhc2_pwrseq>;
};