// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM LPDDR4 Validation Board";
	compatible = "fsl,imx8qm-lpddr4-val", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		decoder_boot: decoder_boot@0x84000000 {
			no-map;
			reg = <0 0x84000000 0 0x2000000>;
		};

		encoder_boot: encoder_boot@0x86000000 {
			no-map;
			reg = <0 0x86000000 0 0x400000>;
		};

		/*
		 * reserved-memory layout
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		m4_reserved: m4@0x88000000 {
			no-map;
			reg = <0 0x88000000 0 0x8000000>;
		};

		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90000000 0 0x400000>;
		};

		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x90400000 0 0x100000>;
		};

		decoder_rpc: decoder_rpc@0x92000000 {
			no-map;
			reg = <0 0x92000000 0 0x200000>;
		};

		encoder_rpc: encoder_rpc@0x92200000 {
			no-map;
			reg = <0 0x92200000 0 0x200000>;
		};

		dsp_reserved: dsp@0x92400000 {
			no-map;
			reg = <0 0x92400000 0 0x2000000>;
		};

		encoder_reserved: encoder_reserved@0x94400000 {
			no-map;
			reg = <0 0x94400000 0 0x800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x3c000000>;
			alloc-ranges = <0 0x96000000 0 0x3c000000>;
			linux,cma-default;
		};

	};

	reg_can_en: regulator-can-en {
		compatible = "regulator-fixed";
		regulator-name = "can-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can_stby: regulator-can-stby {
		compatible = "regulator-fixed";
		regulator-name = "can-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can_en>;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_audio: regulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "cs42888_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sound-cs42888 {
		compatible = "fsl,imx8qm-sabreauto-cs42888",
				"fsl,imx-audio-cs42888";
		model = "imx-cs42888";
		esai-controller = <&esai0>;
		audio-codec = <&cs42888>;
		asrc-controller = <&asrc0>;
	};
};

&amix {
	status = "okay";
};

&asrc0 {
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
	assigned-clock-rates = <786432000>, <49152000>, <24576000>;
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&asrc1 {
	fsl,asrc-rate = <48000>;
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
	assigned-clock-rates = <786432000>, <49152000>, <24576000>;

	status = "okay";
};

&esai0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esai0>;
	assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			<&esai0_lpcg 0>;
	assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
	assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
	status = "okay";
};

&dc0_pc {
	status = "okay";
};

&dc0_prg1 {
	status = "okay";
};

&dc0_prg2 {
	status = "okay";

};

&dc0_prg3 {
	status = "okay";
};

&dc0_prg4 {
	status = "okay";
};

&dc0_prg5 {
	status = "okay";
};

&dc0_prg6 {
	status = "okay";
};

&dc0_prg7 {
	status = "okay";
};

&dc0_prg8 {
	status = "okay";
};

&dc0_prg9 {
	status = "okay";
};

&dc0_dpr1_channel1 {
	status = "okay";
};

&dc0_dpr1_channel2 {
	status = "okay";
};

&dc0_dpr1_channel3 {
	status = "okay";
};

&dc0_dpr2_channel1 {
	status = "okay";
};

&dc0_dpr2_channel2 {
	status = "okay";
};

&dc0_dpr2_channel3 {
	status = "okay";
};

&dpu1 {
	status = "okay";
};

&dc1_pc {
	status = "okay";
};

&dc1_prg1 {
	status = "okay";
};

&dc1_prg2 {
	status = "okay";

};

&dc1_prg3 {
	status = "okay";
};

&dc1_prg4 {
	status = "okay";
};

&dc1_prg5 {
	status = "okay";
};

&dc1_prg6 {
	status = "okay";
};

&dc1_prg7 {
	status = "okay";
};

&dc1_prg8 {
	status = "okay";
};

&dc1_prg9 {
	status = "okay";
};

&dc1_dpr1_channel1 {
	status = "okay";
};

&dc1_dpr1_channel2 {
	status = "okay";
};

&dc1_dpr1_channel3 {
	status = "okay";
};

&dc1_dpr2_channel1 {
	status = "okay";
};

&dc1_dpr2_channel2 {
	status = "okay";
};

&dc1_dpr2_channel3 {
	status = "okay";
};

&dpu2 {
	status = "okay";
};

&sai6 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			<&sai6_lpcg 0>;
	assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "okay";
};

&sai7 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			<&sai7_lpcg 0>;
	assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";

	cs42888: cs42888@48 {
		compatible = "cirrus,cs42888";
		reg = <0x48>;
		clocks = <&mclkout0_lpcg 0>;
		clock-names = "mclk";
		VA-supply = <&reg_audio>;
		VD-supply = <&reg_audio>;
		VLS-supply = <&reg_audio>;
		VLC-supply = <&reg_audio>;
		reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				<&mclkout0_lpcg 0>;
		assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>;
		status = "okay";
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";

	pca9557_a: gpio@18 {
		compatible = "nxp,pca9557";
		reg = <0x18>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_b: gpio@19 {
		compatible = "nxp,pca9557";
		reg = <0x19>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_c: gpio@1b {
		compatible = "nxp,pca9557";
		reg = <0x1b>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_d: gpio@1f {
		compatible = "nxp,pca9557";
		reg = <0x1f>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac0>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
};

&flexcan3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan3>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_esai0: esai0grp {
		fsl,pins = <
			IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR				0xc6000040
			IMX8QM_ESAI0_FST_AUD_ESAI0_FST				0xc6000040
			IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR			0xc6000040
			IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT			0xc6000040
			IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0				0xc6000040
			IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1				0xc6000040
			IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3			0xc6000040
			IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2			0xc6000040
			IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1			0xc6000040
			IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0			0xc6000040
			IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0xc6000040
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD		0x000014a0
			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX	0x21
			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX	0x21
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX	0x21
			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX	0x21
		>;
	};

	pinctrl_flexcan3: flexcan3grp {
		fsl,pins = <
			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX	0x21
			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX	0x21
		>;
	};

	pinctrl_lpi2c0: lpi2c0grp {
		fsl,pins = <
			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL			0xc600004c
			IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA			0xc600004c
		>;
	};

	pinctrl_lpi2c1: lpi2c1grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_DMA_I2C1_SCL				0xc600004c
			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA			0xc600004c
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
		fsl,pins = <
			IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21			0x00000021
			IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22			0x00000021
			IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07			0x00000021
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};
			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};
		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};