/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2026 David Yang */ #ifndef _YT_TC_H #define _YT_TC_H #include #include #define YT921X_ACLn_ACT(n) (0x1c0000 + 0x10 * (n)) #define YT921X_ACL_ACTc_STAG_M GENMASK(26, 25) #define YT921X_ACL_ACTc_STAG(x) FIELD_PREP(YT921X_ACL_ACTc_STAG_M, (x)) #define YT921X_ACL_ACTc_STAG_DONTCARE YT921X_ACL_ACTc_STAG(0) #define YT921X_ACL_ACTc_STAG_UNTAG YT921X_ACL_ACTc_STAG(1) #define YT921X_ACL_ACTc_STAG_TAG YT921X_ACL_ACTc_STAG(2) #define YT921X_ACL_ACTc_STAG_KEEP YT921X_ACL_ACTc_STAG(3) #define YT921X_ACL_ACTc_CTAG_M GENMASK(24, 23) #define YT921X_ACL_ACTc_CTAG(x) FIELD_PREP(YT921X_ACL_ACTc_CTAG_M, (x)) #define YT921X_ACL_ACTc_CTAG_DONTCARE YT921X_ACL_ACTc_CTAG(0) #define YT921X_ACL_ACTc_CTAG_UNTAG YT921X_ACL_ACTc_CTAG(1) #define YT921X_ACL_ACTc_CTAG_TAG YT921X_ACL_ACTc_CTAG(2) #define YT921X_ACL_ACTc_CTAG_KEEP YT921X_ACL_ACTc_CTAG(3) #define YT921X_ACL_ACTc_FWD_M GENMASK(22, 21) #define YT921X_ACL_ACTc_FWD(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_M, (x)) #define YT921X_ACL_ACTc_FWD_FWD YT921X_ACL_ACTc_FWD(0) #define YT921X_ACL_ACTc_FWD_COPY YT921X_ACL_ACTc_FWD(1) #define YT921X_ACL_ACTc_FWD_REDIR YT921X_ACL_ACTc_FWD(2) #define YT921X_ACL_ACTc_FWD_TRAP YT921X_ACL_ACTc_FWD(3) #define YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M GENMASK(20, 10) #define YT921X_ACL_ACTc_FWD_REDIR_DPORTS(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M, (x)) #define YT921X_ACL_ACTc_FWD_REDIR_DPORTn(port) BIT((port) + 10) #define YT921X_ACL_ACTc_FWD_EN BIT(9) #define YT921X_ACL_ACTc_SDEI BIT(8) #define YT921X_ACL_ACTc_SDEI_REPLACE BIT(7) #define YT921X_ACL_ACTc_SPRI_M GENMASK(6, 4) #define YT921X_ACL_ACTc_SPRI(x) FIELD_PREP(YT921X_ACL_ACTc_SPRI_M, (x)) #define YT921X_ACL_ACTc_SPRI_REPLACE BIT(3) #define YT921X_ACL_ACTbc_SVID_M GENMASK_ULL(34, 23) #define YT921X_ACL_ACTbc_SVID(x) FIELD_PREP(YT921X_ACL_ACTbc_SVID_M, (x)) #define YT921X_ACL_ACTb_SVID_REPLACE BIT(22) #define YT921X_ACL_ACTb_CDEI BIT(21) #define YT921X_ACL_ACTb_CDEI_REPLACE BIT(20) #define YT921X_ACL_ACTb_CPRI_M GENMASK(19, 17) #define YT921X_ACL_ACTb_CPRI(x) FIELD_PREP(YT921X_ACL_ACTb_CPRI_M, (x)) #define YT921X_ACL_ACTb_CPRI_REPLACE BIT(16) #define YT921X_ACL_ACTb_CVID_M GENMASK(15, 4) #define YT921X_ACL_ACTb_CVID(x) FIELD_PREP(YT921X_ACL_ACTb_CVID_M, (x)) #define YT921X_ACL_ACTb_CVID_REPLACE BIT(3) #define YT921X_ACL_ACTb_PRIO_M GENMASK(2, 0) #define YT921X_ACL_ACTb_PRIO(x) FIELD_PREP(YT921X_ACL_ACTb_PRIO_M, (x)) #define YT921X_ACL_ACTa_PRIO_EN BIT(31) #define YT921X_ACL_ACTa_COLOR_M GENMASK(30, 29) #define YT921X_ACL_ACTa_COLOR(x) FIELD_PREP(YT921X_ACL_ACTa_COLOR_M, (x)) #define YT921X_ACL_ACTa_COLOR_GREEN YT921X_ACL_ACTa_COLOR(0) #define YT921X_ACL_ACTa_COLOR_YELLOW YT921X_ACL_ACTa_COLOR(1) #define YT921X_ACL_ACTa_COLOR_RED YT921X_ACL_ACTa_COLOR(2) #define YT921X_ACL_ACTa_COLOR_EN BIT(28) #define YT921X_ACL_ACTa_DSCP_M GENMASK(27, 22) #define YT921X_ACL_ACTa_DSCP(x) FIELD_PREP(YT921X_ACL_ACTa_DSCP_M, (x)) #define YT921X_ACL_ACTa_DSCP_REPLACE BIT(21) #define YT921X_ACL_ACTa_METER_ID_M GENMASK(20, 15) #define YT921X_ACL_ACTa_METER_ID(x) FIELD_PREP(YT921X_ACL_ACTa_METER_ID_M, (x)) #define YT921X_ACL_ACTa_METER_EN BIT(14) #define YT921X_ACL_ACTa_MIRROR_EN BIT(13) #define YT921X_ACL_ACTa_FLOWSTAT_EN BIT(12) #define YT921X_ACL_ACTa_FLOWSTAT_ID_M GENMASK(11, 6) #define YT921X_ACL_ACTa_FLOWSTAT_ID(x) FIELD_PREP(YT921X_ACL_ACTa_FLOWSTAT_ID_M, (x)) #define YT921X_ACL_ACTa_GPIO_EN BIT(5) #define YT921X_ACL_ACTa_GPIO_PIN_M GENMASK(4, 1) #define YT921X_ACL_ACTa_GPIO_PIN(x) FIELD_PREP(YT921X_ACL_ACTa_GPIO_PIN_M, (x)) #define YT921X_ACL_ACTa_INTR_EN BIT(0) #define YT921X_ACL_BLK_KEEP 0x201000 #define YT921X_ACL_BLK_KEEP_GRPIDn_M(bin) (7 << (4 * (bin) + 1)) #define YT921X_ACL_BLK_KEEP_GRPIDn(bin, x) ((x) << (4 * (bin) + 1)) #define YT921X_ACL_BLK_KEEP_KEEPn(bin) BIT(4 * (bin)) #define YT921X_ACL_PORT 0x202000 #define YT921X_ACL_PORT_PORTS_M GENMASK(10, 0) #define YT921X_ACL_PORT_PORTS(x) FIELD_PREP(YT921X_ACL_PORT_PORTS_M, (x)) #define YT921X_ACL_PORT_PORTn(port) BIT(port) #define YT921X_ACL_BLK_CMD 0x202004 #define YT921X_ACL_BLK_CMD_BLKID_M GENMASK(6, 1) #define YT921X_ACL_BLK_CMD_BLKID(x) FIELD_PREP(YT921X_ACL_BLK_CMD_BLKID_M, (x)) #define YT921X_ACL_BLK_CMD_MODIFY BIT(0) #define YT921X_ACLn_ENTRY(blk) (0x203000 + 4 * (blk)) #define YT921X_ACL_ENTRY_GRPIDm_M(bin) (7 << (4 * (bin) + 1)) #define YT921X_ACL_ENTRY_GRPIDm(bin, x) ((x) << (4 * (bin) + 1)) #define YT921X_ACL_ENTRY_ENm(bin) BIT(4 * (bin)) #define YT921X_ACLn_KEYm(blk, bin) (0x204000 + 0x200 * (bin) + 8 * (blk)) #define YT921X_ACL_KEYb_ORD_M GENMASK(29, 21) #define YT921X_ACL_KEYb_ORD(x) FIELD_PREP(YT921X_ACL_KEYb_ORD_M, (x)) #define YT921X_ACL_KEYb_SPORTS_M GENMASK(20, 10) #define YT921X_ACL_KEYb_SPORTS(x) FIELD_PREP(YT921X_ACL_KEYb_SPORTS_M, (x)) #define YT921X_ACL_KEYb_SPORTn(port) BIT((port) + 10) #define YT921X_ACL_KEYb_REVERSE BIT(9) /* reverse match */ #define YT921X_ACL_KEYb_TYPE_M GENMASK(8, 4) #define YT921X_ACL_KEYb_TYPE(x) FIELD_PREP(YT921X_ACL_KEYb_TYPE_M, (x)) /* KEY_* fields need no masks */ #define YT921X_ACLn_MASKm(blk, bin) (0x205000 + 0x200 * (bin) + 8 * (blk)) enum yt921x_acl_type { YT921X_ACL_TYPE_NA, YT921X_ACL_TYPE_MAC_DA0, YT921X_ACL_TYPE_MAC_SA0, YT921X_ACL_TYPE_MAC_DA1_SA1, YT921X_ACL_TYPE_VLAN, YT921X_ACL_TYPE_VTAG, YT921X_ACL_TYPE_IPV4_DA, YT921X_ACL_TYPE_IPV4_SA, YT921X_ACL_TYPE_IPV6_DA0, YT921X_ACL_TYPE_IPV6_DA1, YT921X_ACL_TYPE_IPV6_DA2, YT921X_ACL_TYPE_IPV6_DA3, YT921X_ACL_TYPE_IPV6_SA0, YT921X_ACL_TYPE_IPV6_SA1, YT921X_ACL_TYPE_IPV6_SA2, YT921X_ACL_TYPE_IPV6_SA3, YT921X_ACL_TYPE_MISC, YT921X_ACL_TYPE_L4, /* Each User Defined Filter entry contains 2 UDF windows (UDF_CTRL 2i * and 2i+1) */ YT921X_ACL_TYPE_UDF0, YT921X_ACL_TYPE_UDF1, YT921X_ACL_TYPE_UDF2, YT921X_ACL_TYPE_UDF3, YT921X_ACL_TYPE_UDF4, YT921X_ACL_TYPE_UDF5, YT921X_ACL_TYPE_UDF6, YT921X_ACL_TYPE_UDF7, YT921X_ACL_TYPE_ETHERTYPE, YT921X_ACL_TYPE_NUM }; /* Range: turn KEY:MASK into MIN:MAX */ #define YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M GENMASK(3, 0) #define YT921X_ACL_BINb_MAC_xA0_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M, (x)) #define YT921X_ACL_BINa_MAC_xA0_MAC_xA0_M GENMASK(31, 0) #define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M GENMASK(2, 0) #define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M, (x)) #define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_DA1_M GENMASK(31, 16) #define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_SA1_M GENMASK(15, 0) #define YT921X_ACL_KEYb_VLAN_SVID_RANGE_EN BIT(31) #define YT921X_ACL_KEYb_VLAN_CVID_RANGE_EN BIT(30) #define YT921X_ACL_BINb_VLAN_CDEI BIT(3) #define YT921X_ACL_BINb_VLAN_CPRI_M GENMASK(2, 0) #define YT921X_ACL_BINb_VLAN_CPRI(x) FIELD_PREP(YT921X_ACL_BINb_VLAN_CPRI_M, (x)) #define YT921X_ACL_BINa_VLAN_CTAG_FMT_M GENMASK(31, 30) #define YT921X_ACL_BINa_VLAN_CTAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CTAG_FMT_M, (x)) #define YT921X_ACL_BINa_VLAN_SDEI BIT(29) #define YT921X_ACL_BINa_VLAN_SPRI_M GENMASK(28, 26) #define YT921X_ACL_BINa_VLAN_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SPRI_M, (x)) #define YT921X_ACL_BINa_VLAN_STAG_FMT_M GENMASK(25, 24) #define YT921X_ACL_BINa_VLAN_STAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_STAG_FMT_M, (x)) #define YT921X_ACL_BINa_VLAN_SVID_M GENMASK(23, 12) #define YT921X_ACL_BINa_VLAN_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SVID_M, (x)) #define YT921X_ACL_BINa_VLAN_CVID_M GENMASK(11, 0) #define YT921X_ACL_BINa_VLAN_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CVID_M, (x)) #define YT921X_ACL_KEYb_VTAG_SVID_RANGE_EN BIT(31) #define YT921X_ACL_KEYb_VTAG_CVID_RANGE_EN BIT(30) #define YT921X_ACL_BINa_VTAG_CDEI BIT(31) #define YT921X_ACL_BINa_VTAG_CPRI_M GENMASK(30, 28) #define YT921X_ACL_BINa_VTAG_CPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CPRI_M, (x)) #define YT921X_ACL_BINa_VTAG_SDEI BIT(27) #define YT921X_ACL_BINa_VTAG_SPRI_M GENMASK(26, 24) #define YT921X_ACL_BINa_VTAG_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SPRI_M, (x)) #define YT921X_ACL_BINa_VTAG_SVID_M GENMASK(23, 12) #define YT921X_ACL_BINa_VTAG_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SVID_M, (x)) #define YT921X_ACL_BINa_VTAG_CVID_M GENMASK(11, 0) #define YT921X_ACL_BINa_VTAG_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CVID_M, (x)) #define YT921X_ACL_KEYb_IPV4_ADDR_RANGE_EN BIT(30) #define YT921X_ACL_BINb_IPV4_FRAG BIT(3) #define YT921X_ACL_BINb_IPV4_L4_TYPE_M GENMASK(2, 0) #define YT921X_ACL_BINb_IPV4_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV4_L4_TYPE_M, (x)) #define YT921X_ACL_BINa_IPV4_ADDR_M GENMASK(31, 0) #define YT921X_ACL_BINb_IPV6_L4_TYPE_M GENMASK(2, 0) #define YT921X_ACL_BINb_IPV6_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV6_L4_TYPE_M, (x)) #define YT921X_ACL_BINa_IPV6_ADDRx_M GENMASK(31, 0) #define YT921X_ACL_BINb_IPV6_xA1_IP_OPTION BIT(3) #define YT921X_ACL_BINb_IPV6_xA2_FIRST_FRAG BIT(3) #define YT921X_ACL_KEYb_IPV6_xA3_ADDR_RANGE_EN BIT(30) #define YT921X_ACL_BINb_IPV6_xA3_FRAG BIT(3) #define YT921X_ACL_BINb_MISC_FRAG BIT(3) #define YT921X_ACL_BINb_MISC_L4_TYPE_M GENMASK(2, 0) #define YT921X_ACL_BINb_MISC_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MISC_L4_TYPE_M, (x)) #define YT921X_ACL_BINa_MISC_PPPOE_FLAG BIT(30) #define YT921X_ACL_BINa_MISC_FIRST_FRAG BIT(29) #define YT921X_ACL_BINa_MISC_IP_OPTION BIT(28) #define YT921X_ACL_BINa_MISC_TCP_FLAGS_M GENMASK(27, 20) #define YT921X_ACL_BINa_MISC_TCP_FLAGS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TCP_FLAGS_M, (x)) #define YT921X_ACL_BINa_MISC_IP_PROTO_M GENMASK(19, 12) #define YT921X_ACL_BINa_MISC_IP_PROTO(x) FIELD_PREP(YT921X_ACL_BINa_MISC_IP_PROTO_M, (x)) #define YT921X_ACL_BINa_MISC_TOS_M GENMASK(11, 4) #define YT921X_ACL_BINa_MISC_TOS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TOS_M, (x)) #define YT921X_ACL_BINa_MISC_L3_TYPE_M GENMASK(3, 0) #define YT921X_ACL_BINa_MISC_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINa_MISC_L3_TYPE_M, (x)) #define YT921X_ACL_KEYb_L4_DPORT_RANGE_EN BIT(31) #define YT921X_ACL_KEYb_L4_SPORT_RANGE_EN BIT(30) #define YT921X_ACL_BINb_L4_FRAG BIT(3) #define YT921X_ACL_BINb_L4_TYPE_M GENMASK(2, 0) #define YT921X_ACL_BINb_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_L4_TYPE_M, (x)) #define YT921X_ACL_BINa_L4_DPORT_M GENMASK(31, 16) #define YT921X_ACL_BINa_L4_SPORT_M GENMASK(15, 0) #define YT921X_ACL_BINb_UDF_IS_IGMP BIT(0) #define YT921X_ACL_BINa_UDF_UDF0_M GENMASK(31, 16) #define YT921X_ACL_BINa_UDF_UDF0(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF0_M, (x)) #define YT921X_ACL_BINa_UDF_UDF1_M GENMASK(15, 0) #define YT921X_ACL_BINa_UDF_UDF1(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF1_M, (x)) #define YT921X_ACL_KEYb_ETHERTYPE_ETHERTYPE_RANGE_EN BIT(30) #define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M GENMASK(2, 0) #define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M, (x)) #define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M GENMASK(15, 0) #define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE(x) FIELD_PREP(YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M, (x)) enum yt921x_l2_type { YT921X_L2_TYPE_ETH, YT921X_L2_TYPE_ETHV2, YT921X_L2_TYPE_ETHSAP, YT921X_L2_TYPE_ETHSNAP, }; enum yt921x_l3_type { YT921X_L3_TYPE_OTHER, YT921X_L3_TYPE_IPV4, YT921X_L3_TYPE_IPV6, YT921X_L3_TYPE_ARP, YT921X_L3_TYPE_LLDP, YT921X_L3_TYPE_PAE, YT921X_L3_TYPE_ERP, YT921X_L3_TYPE_SLOW_PROTOCOL, }; enum yt921x_l4_type { YT921X_L4_TYPE_OTHER, YT921X_L4_TYPE_TCP, YT921X_L4_TYPE_UDP, YT921X_L4_TYPE_UDPLITE, YT921X_L4_TYPE_ICMP, YT921X_L4_TYPE_IGMP, YT921X_L4_TYPE_MLD, YT921X_L4_TYPE_ND, }; #define YT921X_UDFn_CTRL(x) (0x210094 + 4 * (x)) #define YT921X_UDF_CTRL_UDF_TYPE_M GENMASK(8, 7) #define YT921X_UDF_CTRL_UDF_TYPE(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_TYPE_M, (x)) #define YT921X_UDF_CTRL_UDF_OFFSET_M GENMASK(6, 0) #define YT921X_UDF_CTRL_UDF_OFFSET(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_OFFSET_M, (x)) enum yt921x_udf_type { YT921X_UDF_TYPE_L2, YT921X_UDF_TYPE_L3, YT921X_UDF_TYPE_L4, }; #define YT921X_PORTn_RATE(port) (0x220000 + 4 * (port)) #define YT921X_PORT_RATE_GAP_VALUE GENMASK(4, 0) /* default 20 */ #define YT921X_METER_SLOT 0x220104 #define YT921X_METER_SLOT_SLOT_M GENMASK(11, 0) #define YT921X_PORTn_METER(port) (0x220108 + 4 * (port)) #define YT921X_PORT_METER_EN BIT(4) #define YT921X_PORT_METER_ID_M GENMASK(3, 0) #define YT921X_PORT_METER_ID(x) FIELD_PREP(YT921X_PORT_METER_ID_M, (x)) #define YT921X_METERn_CTRL(x) (0x220800 + 0x10 * (x)) #define YT921X_METER_CTRLc_METER_EN BIT(14) #define YT921X_METER_CTRLc_TOKEN_OVERFLOW_EN BIT(13) /* RFC4115: yellow use unused green bw */ #define YT921X_METER_CTRLc_DROP_M GENMASK(12, 11) #define YT921X_METER_CTRLc_DROP(x) FIELD_PREP(YT921X_METER_CTRLc_DROP_M, (x)) #define YT921X_METER_CTRLc_DROP_GYR YT921X_METER_CTRLc_DROP(0) #define YT921X_METER_CTRLc_DROP_YR YT921X_METER_CTRLc_DROP(1) #define YT921X_METER_CTRLc_DROP_R YT921X_METER_CTRLc_DROP(2) #define YT921X_METER_CTRLc_DROP_NONE YT921X_METER_CTRLc_DROP(3) #define YT921X_METER_CTRLc_COLOR_BLIND BIT(10) #define YT921X_METER_CTRLc_UNIT_M GENMASK(9, 7) #define YT921X_METER_CTRLc_UNIT(x) FIELD_PREP(YT921X_METER_CTRLc_UNIT_M, (x)) #define YT921X_METER_CTRLc_BYTE_MODE_INCLUDE_GAP BIT(6) /* +GAP_VALUE bytes each packet */ #define YT921X_METER_CTRLc_PKT_MODE BIT(5) /* 0: byte rate mode */ #define YT921X_METER_CTRLc_RFC2698 BIT(4) /* 0: RFC4115 */ #define YT921X_METER_CTRLbc_CBS_M GENMASK_ULL(35, 20) #define YT921X_METER_CTRLbc_CBS(x) FIELD_PREP(YT921X_METER_CTRLbc_CBS_M, (x)) #define YT921X_METER_CTRLb_CIR_M GENMASK(19, 2) #define YT921X_METER_CTRLb_CIR(x) FIELD_PREP(YT921X_METER_CTRLb_CIR_M, (x)) #define YT921X_METER_CTRLab_EBS_M GENMASK_ULL(33, 18) #define YT921X_METER_CTRLab_EBS(x) FIELD_PREP(YT921X_METER_CTRLab_EBS_M, (x)) #define YT921X_METER_CTRLa_EIR_M GENMASK(17, 0) #define YT921X_METER_CTRLa_EIR(x) FIELD_PREP(YT921X_METER_CTRLa_EIR_M, (x)) #define YT921X_METERn_STAT(x) (0x221000 + 8 * (x)) #define YT921X_MIRROR 0x300300 #define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16) #define YT921X_MIRROR_IGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_IGR_PORTS_M, (x)) #define YT921X_MIRROR_IGR_PORTn(port) BIT((port) + 16) #define YT921X_MIRROR_EGR_PORTS_M GENMASK(14, 4) #define YT921X_MIRROR_EGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_EGR_PORTS_M, (x)) #define YT921X_MIRROR_EGR_PORTn(port) BIT((port) + 4) #define YT921X_MIRROR_PORT_M GENMASK(3, 0) #define YT921X_MIRROR_PORT(x) FIELD_PREP(YT921X_MIRROR_PORT_M, (x)) #define YT921X_PORT_SHAPE_SLOT 0x34000c #define YT921X_PORT_SHAPE_SLOT_SLOT_M GENMASK(11, 0) #define YT921X_PORTn_SHAPE_CTRL(port) (0x354000 + 8 * (port)) #define YT921X_PORT_SHAPE_CTRLb_EN BIT(4) #define YT921X_PORT_SHAPE_CTRLb_PKT_MODE BIT(3) /* 0: byte rate mode */ #define YT921X_PORT_SHAPE_CTRLb_UNIT_M GENMASK(2, 0) #define YT921X_PORT_SHAPE_CTRLb_UNIT(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLb_UNIT_M, (x)) #define YT921X_PORT_SHAPE_CTRLa_CBS_M GENMASK(31, 18) #define YT921X_PORT_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CBS_M, (x)) #define YT921X_PORT_SHAPE_CTRLa_CIR_M GENMASK(17, 0) #define YT921X_PORT_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CIR_M, (x)) #define YT921X_PORTn_SHAPE_STAT(port) (0x356000 + 4 * (port)) #define YT921X_TOKEN_BYTE_C 1 /* 1 token = 2^1 byte */ #define YT921X_TOKEN_PKT_C -6 /* 1 token = 2^-6 packets */ #define YT921X_TOKEN_RATE_C -15 #define YT921X_METER_SLOT_MIN 80 #define YT921X_METER_UNIT_MAX ((1 << 3) - 1) #define YT921X_METER_CIR_MAX ((1 << 18) - 1) #define YT921X_METER_CBS_MAX ((1 << 16) - 1) #define YT921X_PORT_SHAPE_SLOT_MIN 80 #define YT921X_SHAPE_UNIT_MAX ((1 << 3) - 1) #define YT921X_SHAPE_CIR_MAX ((1 << 18) - 1) #define YT921X_SHAPE_CBS_MAX ((1 << 14) - 1) #define YT921X_ACL_ENT_PER_BLK 8 #define YT921X_ACL_NUM 384 #define YT921X_ACL_ORD_NUM 512 struct yt921x_acl_entry { u32 key[2]; u32 mask[2]; }; struct yt921x_acl_rule { unsigned long tag; enum tc_setup_type type; u32 action[3]; bool sw_assisted; u8 mask; struct yt921x_acl_entry entries[YT921X_ACL_ENT_PER_BLK]; }; struct yt921x_acl_blk { struct yt921x_acl_rule *rules[YT921X_ACL_ENT_PER_BLK]; }; void yt921x_dsa_port_policer_del(struct dsa_switch *ds, int port); int yt921x_dsa_port_policer_add(struct dsa_switch *ds, int port, const struct flow_action_police *police, struct netlink_ext_ack *extack); int yt921x_dsa_port_setup_tc(struct dsa_switch *ds, int port, enum tc_setup_type type, void *type_data); int yt921x_dsa_cls_flower_del(struct dsa_switch *ds, int port, struct flow_cls_offload *cls, bool ingress); int yt921x_dsa_cls_flower_add(struct dsa_switch *ds, int port, struct flow_cls_offload *cls, bool ingress); void yt921x_dsa_port_mirror_del(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror); int yt921x_dsa_port_mirror_add(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror, bool ingress, struct netlink_ext_ack *extack); int yt921x_chip_setup_tc(struct yt921x_priv *priv); int yt921x_chip_setup_acl(struct yt921x_priv *priv); #endif