/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2018 NXP
 *   Dong Aisheng <aisheng.dong@nxp.com>
 */

#ifndef __DT_BINDINGS_CLOCK_IMX_H
#define __DT_BINDINGS_CLOCK_IMX_H

#define IMX_ADMA_ACM_AUD_CLK0_SEL			0
#define IMX_ADMA_ACM_AUD_CLK0_CLK			1
#define IMX_ADMA_ACM_AUD_CLK1_SEL			2
#define IMX_ADMA_ACM_AUD_CLK1_CLK			3
#define IMX_ADMA_ACM_MCLKOUT0_SEL			4
#define IMX_ADMA_ACM_MCLKOUT1_SEL			5
#define IMX_ADMA_ACM_ESAI0_MCLK_SEL			6
#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL			7
#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL			8
#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL			9
#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL			10
#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL			11
#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL			12
#define IMX_ADMA_ACM_SAI0_MCLK_SEL			13
#define IMX_ADMA_ACM_SAI1_MCLK_SEL			14
#define IMX_ADMA_ACM_SAI2_MCLK_SEL			15
#define IMX_ADMA_ACM_SAI3_MCLK_SEL			16
#define IMX_ADMA_ACM_SAI4_MCLK_SEL			17
#define IMX_ADMA_ACM_SAI5_MCLK_SEL			18
#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL			19
#define IMX_ADMA_ACM_MQS_TX_CLK_SEL			20
#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL			21
#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL			22

#define IMX_ADMA_EXT_AUD_MCLK0				23
#define IMX_ADMA_EXT_AUD_MCLK1				24
#define IMX_ADMA_ESAI0_RX_CLK				25
#define IMX_ADMA_ESAI0_RX_HF_CLK			26
#define IMX_ADMA_ESAI0_TX_CLK				27
#define IMX_ADMA_ESAI0_TX_HF_CLK			28
#define IMX_ADMA_SPDIF0_RX				29
#define IMX_ADMA_SAI0_RX_BCLK				30
#define IMX_ADMA_SAI0_TX_BCLK				31
#define IMX_ADMA_SAI1_RX_BCLK				32
#define IMX_ADMA_SAI1_TX_BCLK				33
#define IMX_ADMA_SAI2_RX_BCLK				34
#define IMX_ADMA_SAI3_RX_BCLK				35
#define IMX_ADMA_SAI4_RX_BCLK				36
#define IMX_ADMA_SAI5_TX_BCLK				37
#define IMX_ADMA_SAI6_RX_BCLK				38
#define IMX_ADMA_HDMI_RX_MCLK				39
#define IMX_ADMA_MLB_CLK				40
#define IMX_ADMA_SPDIF1_RX				41
#define IMX_ADMA_ESAI1_RX_CLK				42
#define IMX_ADMA_ESAI1_RX_HF_CLK			43
#define IMX_ADMA_ESAI1_TX_CLK				44
#define IMX_ADMA_ESAI1_TX_HF_CLK			45

#define IMX_ADMA_ACM_ESAI1_MCLK_SEL			46
#define IMX_ADMA_ACM_SAI6_MCLK_SEL			47
#define IMX_ADMA_ACM_SAI7_MCLK_SEL			48
#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL			49

#define IMX_ADMA_ACM_CLK_END				50

#endif /* __DT_BINDINGS_CLOCK_IMX_H */